1 1.1 jmcneill /* $NetBSD: tegra_apbreg.h,v 1.1 2015/03/29 10:41:59 jmcneill Exp $ */ 2 1.1 jmcneill 3 1.1 jmcneill /*- 4 1.1 jmcneill * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 1.1 jmcneill * All rights reserved. 6 1.1 jmcneill * 7 1.1 jmcneill * Redistribution and use in source and binary forms, with or without 8 1.1 jmcneill * modification, are permitted provided that the following conditions 9 1.1 jmcneill * are met: 10 1.1 jmcneill * 1. Redistributions of source code must retain the above copyright 11 1.1 jmcneill * notice, this list of conditions and the following disclaimer. 12 1.1 jmcneill * 2. Redistributions in binary form must reproduce the above copyright 13 1.1 jmcneill * notice, this list of conditions and the following disclaimer in the 14 1.1 jmcneill * documentation and/or other materials provided with the distribution. 15 1.1 jmcneill * 16 1.1 jmcneill * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 1.1 jmcneill * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 1.1 jmcneill * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 1.1 jmcneill * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 1.1 jmcneill * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 1.1 jmcneill * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 1.1 jmcneill * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 1.1 jmcneill * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 1.1 jmcneill * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.1 jmcneill * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.1 jmcneill * SUCH DAMAGE. 27 1.1 jmcneill */ 28 1.1 jmcneill 29 1.1 jmcneill #ifndef _ARM_TEGRA_APBREG_H 30 1.1 jmcneill #define _ARM_TEGRA_APBREG_H 31 1.1 jmcneill 32 1.1 jmcneill #define APB_MISC_PP_CONFIG_CTL_0_REG 0x24 33 1.1 jmcneill #define APB_MISC_PP_PINMUX_GLOBAL_0_0_REG 0x40 34 1.1 jmcneill #define APB_MISC_PP_PULLUPDOWN_REG_C_0_REG 0xa8 35 1.1 jmcneill #define APB_MISC_SC1X_PADS_VIP_VCLKCTRL_0_REG 0x428 36 1.1 jmcneill #define APB_MISC_GP_HIDREV_0_REG 0x804 37 1.1 jmcneill #define APB_MISC_GP_MIPI_PAD_CTRL_0_REG 0x820 38 1.1 jmcneill #define APB_MISC_GP_AOCFG1PADCTRL_0_REG 0x868 39 1.1 jmcneill #define APB_MISC_GP_AOCFG2PADCTRL_0_REG 0x86c 40 1.1 jmcneill #define APB_MISC_GP_ATCFG1PADCTRL_0_REG 0x870 41 1.1 jmcneill #define APB_MISC_GP_ATCFG2PADCTRL_0_REG 0x874 42 1.1 jmcneill #define APB_MISC_GP_ATCFG3PADCTRL_0_REG 0x878 43 1.1 jmcneill #define APB_MISC_GP_ATCFG4PADCTRL_0_REG 0x87c 44 1.1 jmcneill #define APB_MISC_GP_ATCFG5PADCTRL_0_REG 0x880 45 1.1 jmcneill #define APB_MISC_GP_CDEV1CFGPADCTRL_0_REG 0x884 46 1.1 jmcneill #define APB_MISC_GP_CDEV2CFGPADCTRL_0_REG 0x888 47 1.1 jmcneill #define APB_MISC_GP_DAP1CFGPADCTRL_0_REG 0x890 48 1.1 jmcneill #define APB_MISC_GP_DAP2CFGPADCTRL_0_REG 0x894 49 1.1 jmcneill #define APB_MISC_GP_DAP3CFGPADCTRL_0_REG 0x898 50 1.1 jmcneill #define APB_MISC_GP_DAP4CFGPADCTRL_0_REG 0x89c 51 1.1 jmcneill #define APB_MISC_GP_DBGCFGPADCTRL_0_REG 0x8a0 52 1.1 jmcneill #define APB_MISC_GP_SDIO3CFGPADCTRL_0_REG 0x8b0 53 1.1 jmcneill #define APB_MISC_GP_SPICFGPADCTRL_0_REG 0x8b4 54 1.1 jmcneill #define APB_MISC_GP_UAACFGPADCTRL_0_REG 0x8b8 55 1.1 jmcneill #define APB_MISC_GP_UABCFGPADCTRL_0_REG 0x8bc 56 1.1 jmcneill #define APB_MISC_GP_UART2CFGPADCTRL_0_REG 0x8c0 57 1.1 jmcneill #define APB_MISC_GP_UART3CFGPADCTRL_0_REG 0x8c4 58 1.1 jmcneill #define APB_MISC_GP_SDIO1CFGPADCTRL_0_REG 0x8ec 59 1.1 jmcneill #define APB_MISC_GP_DDCCFGPADCTRL_0_REG 0x8fc 60 1.1 jmcneill #define APB_MISC_GP_GMCAFGPADCTRL_0_REG 0x900 61 1.1 jmcneill #define APB_MISC_GP_GMECFGPADCTRL_0_REG 0x910 62 1.1 jmcneill #define APB_MISC_GP_GMFCFGPADCTRL_0_REG 0x914 63 1.1 jmcneill #define APB_MISC_GP_GMGCFGPADCTRL_0_REG 0x918 64 1.1 jmcneill #define APB_MISC_GP_GMHCFGPADCTRL_0_REG 0x91c 65 1.1 jmcneill #define APB_MISC_GP_OWRCFGPADCTRL_0_REG 0x920 66 1.1 jmcneill #define APB_MISC_GP_UADCFGPADCTRL_0_REG 0x924 67 1.1 jmcneill #define APB_MISC_GP_GPVCFGPADCTRL_0_REG 0x928 68 1.1 jmcneill #define APB_MISC_GP_DEV3CFGPADCTRL_0_REG 0x92c 69 1.1 jmcneill #define APB_MISC_GP_CECCFGPADCTRL_0_REG 0x938 70 1.1 jmcneill #define APB_MISC_GP_ATCFG6PADCTRL_0_REG 0x994 71 1.1 jmcneill #define APB_MISC_GP_DAP5CFGPADCTRL_0_REG 0x998 72 1.1 jmcneill #define APB_MISC_GP_USB_VBUS_EN_CFGPADCTRL_0_REG 0x99c 73 1.1 jmcneill #define APB_MISC_GP_AOCFG3PADCTRL_0_REG 0x9a8 74 1.1 jmcneill #define APB_MISC_GP_AOCFG0PADCTRL_0_REG 0x9b0 75 1.1 jmcneill #define APB_MISC_GP_HVCFG0PADCTRL_0_REG 0x9b4 76 1.1 jmcneill #define APB_MISC_GP_SDIO4CFGPADCTRL_0_REG 0x9c4 77 1.1 jmcneill #define APB_MISC_GP_AOCFG4PADCTRL_0_REG 0x9c8 78 1.1 jmcneill #define APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG0_0_REG 0xc00 79 1.1 jmcneill #define APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG1_0_REG 0xc04 80 1.1 jmcneill #define APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG2_0_REG 0xc08 81 1.1 jmcneill 82 1.1 jmcneill #define APB_MISC_GP_HIDREV_0_MINORREV __BITS(19,16) 83 1.1 jmcneill #define APB_MISC_GP_HIDREV_0_CHIPID __BITS(15,8) 84 1.1 jmcneill #define APB_MISC_GP_HIDREV_0_MAJORREV __BITS(7,4) 85 1.1 jmcneill #define APB_MISC_GP_HIDREV_0_HIDFAM __BITS(3,0) 86 1.1 jmcneill 87 1.1 jmcneill #endif /* _ARM_TEGRA_APBREG_H */ 88
Indexes created Tue Sep 30 17:09:57 GMT 2025