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tegra_drm.h revision 1.10 
      1 /* $NetBSD: tegra_drm.h,v 1.10 2021/12/19 12:44:14 riastradh Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #ifndef _ARM_TEGRA_DRM_H
     30 #define _ARM_TEGRA_DRM_H
     31 
     32 #include <drm/drm_encoder.h>
     33 #include <drm/drm_fb_helper.h>
     34 #include <drm/drm_gem_cma_helper.h>
     35 
     36 #define DRIVER_AUTHOR		"Jared McNeill"
     37 
     38 #define DRIVER_NAME		"tegra"
     39 #define DRIVER_DESC		"NVIDIA Tegra K1"
     40 #define DRIVER_DATE		"20151108"
     41 
     42 #define DRIVER_MAJOR		0
     43 #define DRIVER_MINOR		1
     44 #define DRIVER_PATCHLEVEL	0
     45 
     46 struct tegra_framebuffer;
     47 
     48 struct tegra_drm_softc {
     49 	device_t		sc_dev;
     50 	struct drm_device	*sc_ddev;
     51 
     52 	bus_space_tag_t		sc_bst;
     53 	bus_dma_tag_t		sc_dmat;
     54 
     55 	int			sc_phandle;
     56 
     57 	struct clk		*sc_clk_host1x;
     58 	struct fdtbus_reset	*sc_rst_host1x;
     59 
     60 	struct clk		*sc_clk_dc[2];
     61 	struct clk		*sc_clk_dc_parent[2];
     62 	struct fdtbus_reset	*sc_rst_dc[2];
     63 
     64 	struct clk		*sc_clk_hdmi;
     65 	struct clk		*sc_clk_hdmi_parent;
     66 	struct fdtbus_reset	*sc_rst_hdmi;
     67 
     68 	i2c_tag_t		sc_ddc;
     69 	struct fdtbus_gpio_pin	*sc_pin_hpd;
     70 
     71 	bool			sc_force_dvi;
     72 
     73 	uint32_t		sc_vbl_received[2];
     74 };
     75 
     76 struct tegra_drmfb_attach_args {
     77 	struct drm_device	*tfa_drm_dev;
     78 	struct drm_fb_helper	*tfa_fb_helper;
     79 	struct drm_fb_helper_surface_size tfa_fb_sizes;
     80 	bus_space_tag_t		tfa_fb_bst;
     81 	bus_dma_tag_t		tfa_fb_dmat;
     82 	uint32_t		tfa_fb_linebytes;
     83 };
     84 
     85 struct tegra_crtc {
     86 	struct drm_crtc		base;
     87 	bus_space_tag_t		bst;
     88 	bus_space_handle_t	bsh;
     89 	bus_size_t		size;
     90 	int			intr;
     91 	int			index;
     92 	void			*ih;
     93 	bool			enabled;
     94 	struct clk		*clk_parent;
     95 
     96 	struct drm_gem_cma_object	*cursor_obj;
     97 	int			cursor_x;
     98 	int			cursor_y;
     99 };
    100 
    101 struct tegra_encoder {
    102 	struct drm_encoder	base;
    103 	bus_space_tag_t		bst;
    104 	bus_space_handle_t	bsh;
    105 	bus_size_t		size;
    106 };
    107 
    108 struct tegra_connector {
    109 	struct drm_connector	base;
    110 	i2c_tag_t		ddc;
    111 	struct i2c_adapter	*adapter;
    112 	struct fdtbus_gpio_pin	*hpd;
    113 
    114 	bool			has_hdmi_sink;
    115 	bool			has_audio;
    116 };
    117 
    118 struct tegra_framebuffer {
    119 	struct drm_framebuffer	base;
    120 	struct drm_gem_cma_object *obj;
    121 };
    122 
    123 struct tegra_fbdev {
    124 	struct drm_fb_helper	helper;
    125 };
    126 
    127 #define HDMI_READ(enc, reg)			\
    128     bus_space_read_4((enc)->bst, (enc)->bsh, (reg))
    129 #define HDMI_WRITE(enc, reg, val)		\
    130     bus_space_write_4((enc)->bst, (enc)->bsh, (reg), (val))
    131 #define HDMI_SET_CLEAR(enc, reg, set, clr)	\
    132     tegra_reg_set_clear((enc)->bst, (enc)->bsh, (reg), (set), (clr))
    133 
    134 #define DC_READ(crtc, reg)			\
    135     bus_space_read_4((crtc)->bst, (crtc)->bsh, (reg))
    136 #define DC_WRITE(crtc, reg, val)		\
    137     bus_space_write_4((crtc)->bst, (crtc)->bsh, (reg), (val))
    138 #define DC_SET_CLEAR(crtc, reg, set, clr)	\
    139     tegra_reg_set_clear((crtc)->bst, (crtc)->bsh, (reg), (set), (clr))
    140 
    141 #define TEGRA_DC_DEPTH		32
    142 
    143 #define tegra_drm_private(ddev)	(ddev)->dev_private
    144 #define to_tegra_crtc(x)	container_of(x, struct tegra_crtc, base)
    145 #define to_tegra_encoder(x)	container_of(x, struct tegra_encoder, base)
    146 #define to_tegra_connector(x)	container_of(x, struct tegra_connector, base)
    147 #define to_tegra_framebuffer(x)	container_of(x, struct tegra_framebuffer, base)
    148 #define to_tegra_fbdev(x)	container_of(x, struct tegra_fbdev, helper)
    149 
    150 int	tegra_drm_mode_init(struct drm_device *);
    151 int	tegra_drm_fb_init(struct drm_device *);
    152 u32	tegra_drm_get_vblank_counter(struct drm_device *, unsigned int);
    153 int	tegra_drm_enable_vblank(struct drm_device *, unsigned int);
    154 void	tegra_drm_disable_vblank(struct drm_device *, unsigned int);
    155 int	tegra_drm_framebuffer_init(struct drm_device *,
    156 	    struct tegra_framebuffer *);
    157 
    158 #endif /* _ARM_TEGRA_DRM_H */
    159