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tegra_drm.h revision 1.8 
      1 /* $NetBSD: tegra_drm.h,v 1.8 2017/12/26 14:54:52 jmcneill Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #ifndef _ARM_TEGRA_DRM_H
     30 #define _ARM_TEGRA_DRM_H
     31 
     32 #include <drm/drm_fb_helper.h>
     33 #include <drm/drm_gem_cma_helper.h>
     34 
     35 #define DRIVER_AUTHOR		"Jared McNeill"
     36 
     37 #define DRIVER_NAME		"tegra"
     38 #define DRIVER_DESC		"NVIDIA Tegra K1"
     39 #define DRIVER_DATE		"20151108"
     40 
     41 #define DRIVER_MAJOR		0
     42 #define DRIVER_MINOR		1
     43 #define DRIVER_PATCHLEVEL	0
     44 
     45 struct tegra_framebuffer;
     46 
     47 struct tegra_drm_softc {
     48 	device_t		sc_dev;
     49 	struct drm_device	*sc_ddev;
     50 
     51 	bus_space_tag_t		sc_bst;
     52 	bus_dma_tag_t		sc_dmat;
     53 
     54 	int			sc_phandle;
     55 
     56 	struct clk		*sc_clk_host1x;
     57 	struct fdtbus_reset	*sc_rst_host1x;
     58 
     59 	struct clk		*sc_clk_dc[2];
     60 	struct clk		*sc_clk_dc_parent[2];
     61 	struct fdtbus_reset	*sc_rst_dc[2];
     62 
     63 	struct clk		*sc_clk_hdmi;
     64 	struct clk		*sc_clk_hdmi_parent;
     65 	struct fdtbus_reset	*sc_rst_hdmi;
     66 
     67 	i2c_tag_t		sc_ddc;
     68 	struct fdtbus_gpio_pin	*sc_pin_hpd;
     69 
     70 	bool			sc_force_dvi;
     71 
     72 	uint32_t		sc_vbl_received[2];
     73 };
     74 
     75 struct tegra_drmfb_attach_args {
     76 	struct drm_device	*tfa_drm_dev;
     77 	struct drm_fb_helper	*tfa_fb_helper;
     78 	struct drm_fb_helper_surface_size tfa_fb_sizes;
     79 	bus_space_tag_t		tfa_fb_bst;
     80 	bus_dma_tag_t		tfa_fb_dmat;
     81 	uint32_t		tfa_fb_linebytes;
     82 };
     83 
     84 struct tegra_crtc {
     85 	struct drm_crtc		base;
     86 	bus_space_tag_t		bst;
     87 	bus_space_handle_t	bsh;
     88 	bus_size_t		size;
     89 	int			intr;
     90 	int			index;
     91 	void			*ih;
     92 	bool			enabled;
     93 	struct clk		*clk_parent;
     94 
     95 	struct drm_gem_cma_object	*cursor_obj;
     96 	int			cursor_x;
     97 	int			cursor_y;
     98 };
     99 
    100 struct tegra_encoder {
    101 	struct drm_encoder	base;
    102 	bus_space_tag_t		bst;
    103 	bus_space_handle_t	bsh;
    104 	bus_size_t		size;
    105 };
    106 
    107 struct tegra_connector {
    108 	struct drm_connector	base;
    109 	i2c_tag_t		ddc;
    110 	struct i2c_adapter	*adapter;
    111 	struct fdtbus_gpio_pin	*hpd;
    112 
    113 	bool			has_hdmi_sink;
    114 	bool			has_audio;
    115 };
    116 
    117 struct tegra_framebuffer {
    118 	struct drm_framebuffer	base;
    119 	struct drm_gem_cma_object *obj;
    120 };
    121 
    122 struct tegra_fbdev {
    123 	struct drm_fb_helper	helper;
    124 };
    125 
    126 #define HDMI_READ(enc, reg)			\
    127     bus_space_read_4((enc)->bst, (enc)->bsh, (reg))
    128 #define HDMI_WRITE(enc, reg, val)		\
    129     bus_space_write_4((enc)->bst, (enc)->bsh, (reg), (val))
    130 #define HDMI_SET_CLEAR(enc, reg, set, clr)	\
    131     tegra_reg_set_clear((enc)->bst, (enc)->bsh, (reg), (set), (clr))
    132 
    133 #define DC_READ(crtc, reg)			\
    134     bus_space_read_4((crtc)->bst, (crtc)->bsh, (reg))
    135 #define DC_WRITE(crtc, reg, val)		\
    136     bus_space_write_4((crtc)->bst, (crtc)->bsh, (reg), (val))
    137 #define DC_SET_CLEAR(crtc, reg, set, clr)	\
    138     tegra_reg_set_clear((crtc)->bst, (crtc)->bsh, (reg), (set), (clr))
    139 
    140 #define TEGRA_DC_DEPTH		32
    141 
    142 #define tegra_drm_private(ddev)	(ddev)->dev_private
    143 #define to_tegra_crtc(x)	container_of(x, struct tegra_crtc, base)
    144 #define to_tegra_encoder(x)	container_of(x, struct tegra_encoder, base)
    145 #define to_tegra_connector(x)	container_of(x, struct tegra_connector, base)
    146 #define to_tegra_framebuffer(x)	container_of(x, struct tegra_framebuffer, base)
    147 #define to_tegra_fbdev(x)	container_of(x, struct tegra_fbdev, helper)
    148 
    149 int	tegra_drm_mode_init(struct drm_device *);
    150 int	tegra_drm_fb_init(struct drm_device *);
    151 u32	tegra_drm_get_vblank_counter(struct drm_device *, int);
    152 int	tegra_drm_enable_vblank(struct drm_device *, int);
    153 void	tegra_drm_disable_vblank(struct drm_device *, int);
    154 int	tegra_drm_framebuffer_init(struct drm_device *,
    155 	    struct tegra_framebuffer *);
    156 
    157 #endif /* _ARM_TEGRA_DRM_H */
    158