tegra_drm_mode.c revision 1.12.6.1
1 /* $NetBSD: tegra_drm_mode.c,v 1.12.6.1 2017/04/21 16:53:23 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_drm_mode.c,v 1.12.6.1 2017/04/21 16:53:23 bouyer Exp $"); 31 32 #include <drm/drmP.h> 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_crtc_helper.h> 35 #include <drm/drm_edid.h> 36 37 #include <dev/i2c/ddcvar.h> 38 39 #include <arm/nvidia/tegra_reg.h> 40 #include <arm/nvidia/tegra_var.h> 41 #include <arm/nvidia/tegra_intr.h> 42 #include <arm/nvidia/tegra_pmcreg.h> 43 #include <arm/nvidia/tegra_dcreg.h> 44 #include <arm/nvidia/tegra_hdmireg.h> 45 #include <arm/nvidia/tegra_drm.h> 46 47 #include <dev/fdt/fdtvar.h> 48 49 static struct drm_framebuffer *tegra_fb_create(struct drm_device *, 50 struct drm_file *, struct drm_mode_fb_cmd2 *); 51 52 static const struct drm_mode_config_funcs tegra_mode_config_funcs = { 53 .fb_create = tegra_fb_create 54 }; 55 56 static int tegra_framebuffer_create_handle(struct drm_framebuffer *, 57 struct drm_file *, unsigned int *); 58 static void tegra_framebuffer_destroy(struct drm_framebuffer *); 59 60 static const struct drm_framebuffer_funcs tegra_framebuffer_funcs = { 61 .create_handle = tegra_framebuffer_create_handle, 62 .destroy = tegra_framebuffer_destroy 63 }; 64 65 static int tegra_crtc_init(struct drm_device *, int); 66 static void tegra_crtc_destroy(struct drm_crtc *); 67 static int tegra_crtc_cursor_set(struct drm_crtc *, struct drm_file *, 68 uint32_t, uint32_t, uint32_t); 69 static int tegra_crtc_cursor_move(struct drm_crtc *, int, int); 70 static int tegra_crtc_intr(void *); 71 72 static const struct drm_crtc_funcs tegra_crtc_funcs = { 73 .cursor_set = tegra_crtc_cursor_set, 74 .cursor_move = tegra_crtc_cursor_move, 75 .set_config = drm_crtc_helper_set_config, 76 .destroy = tegra_crtc_destroy 77 }; 78 79 static void tegra_crtc_dpms(struct drm_crtc *, int); 80 static bool tegra_crtc_mode_fixup(struct drm_crtc *, 81 const struct drm_display_mode *, 82 struct drm_display_mode *); 83 static int tegra_crtc_mode_set(struct drm_crtc *, 84 struct drm_display_mode *, struct drm_display_mode *, 85 int, int, struct drm_framebuffer *); 86 static int tegra_crtc_mode_set_base(struct drm_crtc *, 87 int, int, struct drm_framebuffer *); 88 static int tegra_crtc_mode_set_base_atomic(struct drm_crtc *, 89 struct drm_framebuffer *, int, int, enum mode_set_atomic); 90 static void tegra_crtc_disable(struct drm_crtc *); 91 static void tegra_crtc_prepare(struct drm_crtc *); 92 static void tegra_crtc_commit(struct drm_crtc *); 93 94 static int tegra_crtc_do_set_base(struct drm_crtc *, 95 struct drm_framebuffer *, int, int, int); 96 97 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = { 98 .dpms = tegra_crtc_dpms, 99 .mode_fixup = tegra_crtc_mode_fixup, 100 .mode_set = tegra_crtc_mode_set, 101 .mode_set_base = tegra_crtc_mode_set_base, 102 .mode_set_base_atomic = tegra_crtc_mode_set_base_atomic, 103 .disable = tegra_crtc_disable, 104 .prepare = tegra_crtc_prepare, 105 .commit = tegra_crtc_commit 106 }; 107 108 static int tegra_encoder_init(struct drm_device *); 109 static void tegra_encoder_destroy(struct drm_encoder *); 110 111 static const struct drm_encoder_funcs tegra_encoder_funcs = { 112 .destroy = tegra_encoder_destroy 113 }; 114 115 static void tegra_encoder_dpms(struct drm_encoder *, int); 116 static bool tegra_encoder_mode_fixup(struct drm_encoder *, 117 const struct drm_display_mode *, struct drm_display_mode *); 118 static void tegra_encoder_mode_set(struct drm_encoder *, 119 struct drm_display_mode *, struct drm_display_mode *); 120 static void tegra_encoder_prepare(struct drm_encoder *); 121 static void tegra_encoder_commit(struct drm_encoder *); 122 123 static const struct drm_encoder_helper_funcs tegra_encoder_helper_funcs = { 124 .dpms = tegra_encoder_dpms, 125 .mode_fixup = tegra_encoder_mode_fixup, 126 .prepare = tegra_encoder_prepare, 127 .commit = tegra_encoder_commit, 128 .mode_set = tegra_encoder_mode_set 129 }; 130 131 static int tegra_connector_init(struct drm_device *, struct drm_encoder *); 132 static void tegra_connector_destroy(struct drm_connector *); 133 static enum drm_connector_status tegra_connector_detect(struct drm_connector *, 134 bool); 135 136 static const struct drm_connector_funcs tegra_connector_funcs = { 137 .dpms = drm_helper_connector_dpms, 138 .detect = tegra_connector_detect, 139 .fill_modes = drm_helper_probe_single_connector_modes, 140 .destroy = tegra_connector_destroy 141 }; 142 143 static int tegra_connector_mode_valid(struct drm_connector *, 144 struct drm_display_mode *); 145 static int tegra_connector_get_modes(struct drm_connector *); 146 static struct drm_encoder *tegra_connector_best_encoder(struct drm_connector *); 147 148 static const struct drm_connector_helper_funcs tegra_connector_helper_funcs = { 149 .mode_valid = tegra_connector_mode_valid, 150 .get_modes = tegra_connector_get_modes, 151 .best_encoder = tegra_connector_best_encoder 152 }; 153 154 static const struct tegra_hdmi_tmds_config { 155 u_int dot_clock; 156 uint32_t sor_pll0; 157 uint32_t sor_pll1; 158 uint32_t sor_lane_drive_current; 159 uint32_t pe_current; 160 uint32_t sor_io_peak_current; 161 uint32_t sor_pad_ctls0; 162 uint32_t car_plld_misc; /* XXX unused? */ 163 } tegra_hdmi_tmds_config[] = { 164 /* 480p */ 165 { 27000, 0x01003010, 0x00301b00, 0x1f1f1f1f, 166 0x00000000, 0x03030303, 0x800034bb, 0x40400820 }, 167 /* 720p / 1080i */ 168 { 74250, 0x01003110, 0x00301500, 0x2c2c2c2c, 169 0x00000000, 0x07070707, 0x800034bb, 0x40400820 }, 170 /* 1080p */ 171 { 148500, 0x01003310, 0x00301500, 0x2d2d2d2d, 172 0x00000000, 0x05050505, 0x800034bb, 0x40400820 }, 173 /* 2160p */ 174 { 297000, 0x01003f10, 0x00300f00, 0x37373737, 175 0x00000000, 0x17171717, 0x800036bb, 0x40400f20 }, 176 }; 177 178 int 179 tegra_drm_mode_init(struct drm_device *ddev) 180 { 181 int error; 182 183 drm_mode_config_init(ddev); 184 ddev->mode_config.min_width = 0; 185 ddev->mode_config.min_height = 0; 186 ddev->mode_config.max_width = 4096; 187 ddev->mode_config.max_height = 2160; 188 ddev->mode_config.funcs = &tegra_mode_config_funcs; 189 190 error = tegra_crtc_init(ddev, 0); 191 if (error) 192 return error; 193 194 error = tegra_crtc_init(ddev, 1); 195 if (error) 196 return error; 197 198 error = tegra_encoder_init(ddev); 199 if (error) 200 return error; 201 202 error = drm_vblank_init(ddev, 2); 203 if (error) 204 return error; 205 206 return 0; 207 } 208 209 int 210 tegra_drm_framebuffer_init(struct drm_device *ddev, 211 struct tegra_framebuffer *fb) 212 { 213 return drm_framebuffer_init(ddev, &fb->base, &tegra_framebuffer_funcs); 214 } 215 216 static struct drm_framebuffer * 217 tegra_fb_create(struct drm_device *ddev, struct drm_file *file, 218 struct drm_mode_fb_cmd2 *cmd) 219 { 220 struct tegra_framebuffer *fb; 221 struct drm_gem_object *gem_obj; 222 int error; 223 224 if (cmd->flags) 225 return NULL; 226 if (cmd->pixel_format != DRM_FORMAT_ARGB8888 && 227 cmd->pixel_format != DRM_FORMAT_XRGB8888) { 228 return NULL; 229 } 230 231 gem_obj = drm_gem_object_lookup(ddev, file, cmd->handles[0]); 232 if (gem_obj == NULL) 233 return NULL; 234 235 fb = kmem_zalloc(sizeof(*fb), KM_SLEEP); 236 if (fb == NULL) 237 goto unref; 238 239 fb->obj = to_tegra_gem_obj(gem_obj); 240 fb->base.pitches[0] = cmd->pitches[0]; 241 fb->base.offsets[0] = cmd->offsets[0]; 242 fb->base.width = cmd->width; 243 fb->base.height = cmd->height; 244 fb->base.pixel_format = cmd->pixel_format; 245 drm_fb_get_bpp_depth(cmd->pixel_format, &fb->base.depth, 246 &fb->base.bits_per_pixel); 247 248 error = tegra_drm_framebuffer_init(ddev, fb); 249 if (error) 250 goto dealloc; 251 252 return &fb->base; 253 254 drm_framebuffer_cleanup(&fb->base); 255 dealloc: 256 kmem_free(fb, sizeof(*fb)); 257 unref: 258 drm_gem_object_unreference_unlocked(gem_obj); 259 260 return NULL; 261 } 262 263 static int 264 tegra_framebuffer_create_handle(struct drm_framebuffer *fb, 265 struct drm_file *file, unsigned int *handle) 266 { 267 struct tegra_framebuffer *tegra_fb = to_tegra_framebuffer(fb); 268 269 return drm_gem_handle_create(file, &tegra_fb->obj->base, handle); 270 } 271 272 static void 273 tegra_framebuffer_destroy(struct drm_framebuffer *fb) 274 { 275 struct tegra_framebuffer *tegra_fb = to_tegra_framebuffer(fb); 276 277 drm_framebuffer_cleanup(fb); 278 drm_gem_object_unreference_unlocked(&tegra_fb->obj->base); 279 kmem_free(tegra_fb, sizeof(*tegra_fb)); 280 } 281 282 static int 283 tegra_crtc_init(struct drm_device *ddev, int index) 284 { 285 struct tegra_drm_softc * const sc = tegra_drm_private(ddev); 286 struct tegra_crtc *crtc; 287 bus_addr_t offset; 288 bus_size_t size; 289 u_int intr; 290 int error; 291 292 if (sc->sc_clk_dc[index] == NULL || 293 sc->sc_clk_dc_parent[index] == NULL || 294 sc->sc_rst_dc[index] == NULL) { 295 DRM_ERROR("no clocks configured for crtc %d\n", index); 296 return -EIO; 297 } 298 299 switch (index) { 300 case 0: 301 offset = TEGRA_GHOST_BASE + TEGRA_DISPLAYA_OFFSET; 302 size = TEGRA_DISPLAYA_SIZE; 303 intr = TEGRA_INTR_DISPLAYA; 304 break; 305 case 1: 306 offset = TEGRA_GHOST_BASE + TEGRA_DISPLAYB_OFFSET; 307 size = TEGRA_DISPLAYB_SIZE; 308 intr = TEGRA_INTR_DISPLAYB; 309 break; 310 default: 311 return -EINVAL; 312 } 313 314 crtc = kmem_zalloc(sizeof(*crtc), KM_SLEEP); 315 if (crtc == NULL) 316 return -ENOMEM; 317 318 crtc->index = index; 319 crtc->bst = sc->sc_bst; 320 error = bus_space_map(crtc->bst, offset, size, 0, &crtc->bsh); 321 if (error) { 322 kmem_free(crtc, sizeof(*crtc)); 323 return -error; 324 } 325 crtc->size = size; 326 crtc->intr = intr; 327 crtc->ih = intr_establish(intr, IPL_VM, IST_LEVEL | IST_MPSAFE, 328 tegra_crtc_intr, crtc); 329 if (crtc->ih == NULL) { 330 DRM_ERROR("failed to establish interrupt for crtc %d\n", index); 331 } 332 const size_t cursor_size = 256 * 256 * 4; 333 crtc->cursor_obj = tegra_drm_obj_alloc(ddev, cursor_size); 334 if (crtc->cursor_obj == NULL) { 335 kmem_free(crtc, sizeof(*crtc)); 336 return -ENOMEM; 337 } 338 339 /* Enter reset */ 340 fdtbus_reset_assert(sc->sc_rst_dc[index]); 341 342 /* Turn on power to display partition */ 343 const u_int pmc_partid = index == 0 ? PMC_PARTID_DIS : PMC_PARTID_DISB; 344 tegra_pmc_power(pmc_partid, true); 345 tegra_pmc_remove_clamping(pmc_partid); 346 347 /* Set parent clock */ 348 error = clk_set_parent(sc->sc_clk_dc[index], 349 sc->sc_clk_dc_parent[index]); 350 if (error) { 351 DRM_ERROR("failed to set crtc %d clock parent: %d\n", 352 index, error); 353 return -error; 354 } 355 356 /* Enable DC clock */ 357 error = clk_enable(sc->sc_clk_dc[index]); 358 if (error) { 359 DRM_ERROR("failed to enable crtc %d clock: %d\n", index, error); 360 return -error; 361 } 362 363 /* Leave reset */ 364 fdtbus_reset_deassert(sc->sc_rst_dc[index]); 365 366 crtc->clk_parent = sc->sc_clk_dc_parent[index]; 367 368 DC_WRITE(crtc, DC_CMD_INT_ENABLE_REG, DC_CMD_INT_V_BLANK); 369 370 drm_crtc_init(ddev, &crtc->base, &tegra_crtc_funcs); 371 drm_crtc_helper_add(&crtc->base, &tegra_crtc_helper_funcs); 372 373 return 0; 374 } 375 376 static int 377 tegra_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, 378 uint32_t handle, uint32_t width, uint32_t height) 379 { 380 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 381 struct drm_gem_object *gem_obj = NULL; 382 struct tegra_gem_object *obj; 383 uint32_t cfg, opt; 384 int error; 385 386 if (tegra_crtc->enabled == false) 387 return 0; 388 389 if (handle == 0) { 390 /* hide cursor */ 391 opt = DC_READ(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG); 392 if ((opt & DC_DISP_DISP_WIN_OPTIONS_CURSOR_ENABLE) != 0) { 393 opt &= ~DC_DISP_DISP_WIN_OPTIONS_CURSOR_ENABLE; 394 DC_WRITE(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG, opt); 395 /* Commit settings */ 396 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 397 DC_CMD_STATE_CONTROL_GENERAL_UPDATE); 398 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 399 DC_CMD_STATE_CONTROL_GENERAL_ACT_REQ); 400 } 401 error = 0; 402 goto done; 403 } 404 405 if ((width != height) || 406 (width != 32 && width != 64 && width != 128 && width != 256)) { 407 DRM_ERROR("Cursor dimension %ux%u not supported\n", 408 width, height); 409 error = -EINVAL; 410 goto done; 411 } 412 413 gem_obj = drm_gem_object_lookup(crtc->dev, file_priv, handle); 414 if (gem_obj == NULL) { 415 DRM_ERROR("Cannot find cursor object %#x for crtc %d\n", 416 handle, tegra_crtc->index); 417 error = -ENOENT; 418 goto done; 419 } 420 obj = to_tegra_gem_obj(gem_obj); 421 422 if (obj->base.size < width * height * 4) { 423 DRM_ERROR("Cursor buffer is too small\n"); 424 error = -ENOMEM; 425 goto done; 426 } 427 428 cfg = __SHIFTIN(DC_DISP_CURSOR_START_ADDR_CLIPPING_DISPLAY, 429 DC_DISP_CURSOR_START_ADDR_CLIPPING); 430 switch (width) { 431 case 32: 432 cfg |= __SHIFTIN(DC_DISP_CURSOR_START_ADDR_SIZE_32, 433 DC_DISP_CURSOR_START_ADDR_SIZE); 434 break; 435 case 64: 436 cfg |= __SHIFTIN(DC_DISP_CURSOR_START_ADDR_SIZE_64, 437 DC_DISP_CURSOR_START_ADDR_SIZE); 438 break; 439 case 128: 440 cfg |= __SHIFTIN(DC_DISP_CURSOR_START_ADDR_SIZE_128, 441 DC_DISP_CURSOR_START_ADDR_SIZE); 442 break; 443 case 256: 444 cfg |= __SHIFTIN(DC_DISP_CURSOR_START_ADDR_SIZE_256, 445 DC_DISP_CURSOR_START_ADDR_SIZE); 446 break; 447 } 448 449 /* copy cursor (argb -> rgba) */ 450 struct tegra_gem_object *cursor_obj = tegra_crtc->cursor_obj; 451 uint32_t off, *cp = obj->dmap, *crtc_cp = cursor_obj->dmap; 452 for (off = 0; off < width * height; off++) { 453 crtc_cp[off] = (cp[off] << 8) | (cp[off] >> 24); 454 } 455 456 const uint64_t paddr = cursor_obj->dmasegs[0].ds_addr; 457 458 DC_WRITE(tegra_crtc, DC_DISP_CURSOR_START_ADDR_HI_REG, 459 (paddr >> 32) & 3); 460 cfg |= __SHIFTIN((paddr >> 10) & 0x3fffff, 461 DC_DISP_CURSOR_START_ADDR_ADDRESS_LO); 462 const uint32_t ocfg = 463 DC_READ(tegra_crtc, DC_DISP_CURSOR_START_ADDR_REG); 464 if (cfg != ocfg) { 465 DC_WRITE(tegra_crtc, DC_DISP_CURSOR_START_ADDR_REG, cfg); 466 } 467 468 cfg = DC_READ(tegra_crtc, DC_DISP_BLEND_CURSOR_CONTROL_REG); 469 cfg &= ~DC_DISP_BLEND_CURSOR_CONTROL_DST_BLEND_FACTOR_SEL; 470 cfg |= __SHIFTIN(2, DC_DISP_BLEND_CURSOR_CONTROL_DST_BLEND_FACTOR_SEL); 471 cfg &= ~DC_DISP_BLEND_CURSOR_CONTROL_SRC_BLEND_FACTOR_SEL; 472 cfg |= __SHIFTIN(1, DC_DISP_BLEND_CURSOR_CONTROL_SRC_BLEND_FACTOR_SEL); 473 cfg &= ~DC_DISP_BLEND_CURSOR_CONTROL_ALPHA; 474 cfg |= __SHIFTIN(255, DC_DISP_BLEND_CURSOR_CONTROL_ALPHA); 475 cfg |= DC_DISP_BLEND_CURSOR_CONTROL_MODE_SEL; 476 DC_WRITE(tegra_crtc, DC_DISP_BLEND_CURSOR_CONTROL_REG, cfg); 477 478 /* set cursor position */ 479 DC_WRITE(tegra_crtc, DC_DISP_CURSOR_POSITION_REG, 480 __SHIFTIN(tegra_crtc->cursor_x, DC_DISP_CURSOR_POSITION_H) | 481 __SHIFTIN(tegra_crtc->cursor_y, DC_DISP_CURSOR_POSITION_V)); 482 483 /* Commit settings */ 484 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 485 DC_CMD_STATE_CONTROL_CURSOR_UPDATE); 486 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 487 DC_CMD_STATE_CONTROL_CURSOR_ACT_REQ); 488 489 /* show cursor */ 490 opt = DC_READ(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG); 491 if ((opt & DC_DISP_DISP_WIN_OPTIONS_CURSOR_ENABLE) == 0) { 492 opt |= DC_DISP_DISP_WIN_OPTIONS_CURSOR_ENABLE; 493 DC_WRITE(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG, opt); 494 495 /* Commit settings */ 496 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 497 DC_CMD_STATE_CONTROL_GENERAL_UPDATE); 498 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 499 DC_CMD_STATE_CONTROL_GENERAL_ACT_REQ); 500 } 501 502 error = 0; 503 504 done: 505 if (error == 0) { 506 /* Wait for activation request to complete */ 507 while (DC_READ(tegra_crtc, DC_CMD_STATE_CONTROL_REG) & 508 DC_CMD_STATE_CONTROL_GENERAL_ACT_REQ) 509 ; 510 } 511 512 if (gem_obj) { 513 drm_gem_object_unreference_unlocked(gem_obj); 514 } 515 516 return error; 517 } 518 519 static int 520 tegra_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) 521 { 522 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 523 524 tegra_crtc->cursor_x = x & 0x3fff; 525 tegra_crtc->cursor_y = y & 0x3fff; 526 527 DC_WRITE(tegra_crtc, DC_DISP_CURSOR_POSITION_REG, 528 __SHIFTIN(x & 0x3fff, DC_DISP_CURSOR_POSITION_H) | 529 __SHIFTIN(y & 0x3fff, DC_DISP_CURSOR_POSITION_V)); 530 531 /* Commit settings */ 532 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 533 DC_CMD_STATE_CONTROL_CURSOR_UPDATE); 534 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 535 DC_CMD_STATE_CONTROL_CURSOR_ACT_REQ); 536 537 return 0; 538 } 539 540 static void 541 tegra_crtc_destroy(struct drm_crtc *crtc) 542 { 543 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 544 drm_crtc_cleanup(crtc); 545 if (tegra_crtc->ih) { 546 intr_disestablish(tegra_crtc->ih); 547 } 548 tegra_drm_obj_free(tegra_crtc->cursor_obj); 549 bus_space_unmap(tegra_crtc->bst, tegra_crtc->bsh, tegra_crtc->size); 550 kmem_free(tegra_crtc, sizeof(*tegra_crtc)); 551 } 552 553 static void 554 tegra_crtc_dpms(struct drm_crtc *crtc, int mode) 555 { 556 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 557 558 switch (mode) { 559 case DRM_MODE_DPMS_ON: 560 case DRM_MODE_DPMS_STANDBY: 561 case DRM_MODE_DPMS_SUSPEND: 562 DC_SET_CLEAR(tegra_crtc, DC_WINC_A_WIN_OPTIONS_REG, 563 DC_WINC_A_WIN_OPTIONS_WIN_ENABLE, 0); 564 break; 565 case DRM_MODE_DPMS_OFF: 566 DC_SET_CLEAR(tegra_crtc, DC_WINC_A_WIN_OPTIONS_REG, 567 0, DC_WINC_A_WIN_OPTIONS_WIN_ENABLE); 568 break; 569 } 570 } 571 572 static bool 573 tegra_crtc_mode_fixup(struct drm_crtc *crtc, 574 const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) 575 { 576 return true; 577 } 578 579 static int 580 tegra_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, 581 struct drm_display_mode *adjusted_mode, int x, int y, 582 struct drm_framebuffer *old_fb) 583 { 584 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 585 const u_int hspw = mode->crtc_hsync_end - mode->crtc_hsync_start; 586 const u_int hbp = mode->crtc_htotal - mode->crtc_hsync_end; 587 const u_int hfp = mode->crtc_hsync_start - mode->crtc_hdisplay; 588 const u_int vspw = mode->crtc_vsync_end - mode->crtc_vsync_start; 589 const u_int vbp = mode->crtc_vtotal - mode->crtc_vsync_end; 590 const u_int vfp = mode->crtc_vsync_start - mode->crtc_vdisplay; 591 592 /* Set colour depth to ARGB8888 */ 593 DC_WRITE(tegra_crtc, DC_WINC_A_COLOR_DEPTH_REG, 594 __SHIFTIN(DC_WINC_A_COLOR_DEPTH_DEPTH_T_A8R8G8B8, 595 DC_WINC_A_COLOR_DEPTH_DEPTH)); 596 597 /* Disable byte swapping */ 598 DC_WRITE(tegra_crtc, DC_WINC_A_BYTE_SWAP_REG, 599 __SHIFTIN(DC_WINC_A_BYTE_SWAP_SWAP_NOSWAP, 600 DC_WINC_A_BYTE_SWAP_SWAP)); 601 602 /* Initial DDA */ 603 DC_WRITE(tegra_crtc, DC_WINC_A_H_INITIAL_DDA_REG, 0); 604 DC_WRITE(tegra_crtc, DC_WINC_A_V_INITIAL_DDA_REG, 0); 605 DC_WRITE(tegra_crtc, DC_WINC_A_DDA_INCREMENT_REG, 0x10001000); 606 607 /* Window position, size, stride */ 608 DC_WRITE(tegra_crtc, DC_WINC_A_POSITION_REG, 609 __SHIFTIN(0, DC_WINC_A_POSITION_V) | 610 __SHIFTIN(0, DC_WINC_A_POSITION_H)); 611 DC_WRITE(tegra_crtc, DC_WINC_A_SIZE_REG, 612 __SHIFTIN(mode->crtc_vdisplay, DC_WINC_A_SIZE_V) | 613 __SHIFTIN(mode->crtc_hdisplay, DC_WINC_A_SIZE_H)); 614 DC_WRITE(tegra_crtc, DC_WINC_A_PRESCALED_SIZE_REG, 615 __SHIFTIN(mode->crtc_vdisplay, DC_WINC_A_PRESCALED_SIZE_V) | 616 __SHIFTIN(mode->crtc_hdisplay * (TEGRA_DC_DEPTH / 8), 617 DC_WINC_A_PRESCALED_SIZE_H)); 618 DC_WRITE(tegra_crtc, DC_WINC_A_LINE_STRIDE_REG, 619 __SHIFTIN(mode->crtc_hdisplay * (TEGRA_DC_DEPTH / 8), 620 DC_WINC_A_LINE_STRIDE_LINE_STRIDE)); 621 622 tegra_crtc_do_set_base(crtc, old_fb, x, y, 0); 623 624 /* Enable window A */ 625 DC_WRITE(tegra_crtc, DC_WINC_A_WIN_OPTIONS_REG, 626 DC_WINC_A_WIN_OPTIONS_WIN_ENABLE); 627 628 /* Timing and signal options */ 629 DC_WRITE(tegra_crtc, DC_DISP_DISP_TIMING_OPTIONS_REG, 630 __SHIFTIN(1, DC_DISP_DISP_TIMING_OPTIONS_VSYNC_POS)); 631 DC_WRITE(tegra_crtc, DC_DISP_DISP_COLOR_CONTROL_REG, 632 __SHIFTIN(DC_DISP_DISP_COLOR_CONTROL_BASE_COLOR_SIZE_888, 633 DC_DISP_DISP_COLOR_CONTROL_BASE_COLOR_SIZE)); 634 DC_WRITE(tegra_crtc, DC_DISP_DISP_SIGNAL_OPTIONS0_REG, 635 DC_DISP_DISP_SIGNAL_OPTIONS0_H_PULSE2_ENABLE); 636 DC_WRITE(tegra_crtc, DC_DISP_H_PULSE2_CONTROL_REG, 637 __SHIFTIN(DC_DISP_H_PULSE2_CONTROL_V_QUAL_VACTIVE, 638 DC_DISP_H_PULSE2_CONTROL_V_QUAL) | 639 __SHIFTIN(DC_DISP_H_PULSE2_CONTROL_LAST_END_A, 640 DC_DISP_H_PULSE2_CONTROL_LAST)); 641 642 const u_int pulse_start = 1 + hspw + hbp - 10; 643 DC_WRITE(tegra_crtc, DC_DISP_H_PULSE2_POSITION_A_REG, 644 __SHIFTIN(pulse_start, DC_DISP_H_PULSE2_POSITION_A_START) | 645 __SHIFTIN(pulse_start + 8, DC_DISP_H_PULSE2_POSITION_A_END)); 646 647 /* Pixel clock */ 648 const u_int parent_rate = clk_get_rate(tegra_crtc->clk_parent); 649 const u_int div = (parent_rate * 2) / (mode->crtc_clock * 1000) - 2; 650 DC_WRITE(tegra_crtc, DC_DISP_DISP_CLOCK_CONTROL_REG, 651 __SHIFTIN(0, DC_DISP_DISP_CLOCK_CONTROL_PIXEL_CLK_DIVIDER) | 652 __SHIFTIN(div, DC_DISP_DISP_CLOCK_CONTROL_SHIFT_CLK_DIVIDER)); 653 654 /* Mode timings */ 655 DC_WRITE(tegra_crtc, DC_DISP_REF_TO_SYNC_REG, 656 __SHIFTIN(1, DC_DISP_REF_TO_SYNC_V) | 657 __SHIFTIN(1, DC_DISP_REF_TO_SYNC_H)); 658 DC_WRITE(tegra_crtc, DC_DISP_SYNC_WIDTH_REG, 659 __SHIFTIN(vspw, DC_DISP_SYNC_WIDTH_V) | 660 __SHIFTIN(hspw, DC_DISP_SYNC_WIDTH_H)); 661 DC_WRITE(tegra_crtc, DC_DISP_BACK_PORCH_REG, 662 __SHIFTIN(vbp, DC_DISP_BACK_PORCH_V) | 663 __SHIFTIN(hbp, DC_DISP_BACK_PORCH_H)); 664 DC_WRITE(tegra_crtc, DC_DISP_FRONT_PORCH_REG, 665 __SHIFTIN(vfp, DC_DISP_FRONT_PORCH_V) | 666 __SHIFTIN(hfp, DC_DISP_FRONT_PORCH_H)); 667 DC_WRITE(tegra_crtc, DC_DISP_DISP_ACTIVE_REG, 668 __SHIFTIN(mode->crtc_vdisplay, DC_DISP_DISP_ACTIVE_V) | 669 __SHIFTIN(mode->crtc_hdisplay, DC_DISP_DISP_ACTIVE_H)); 670 671 return 0; 672 } 673 674 static int 675 tegra_crtc_do_set_base(struct drm_crtc *crtc, struct drm_framebuffer *fb, 676 int x, int y, int atomic) 677 { 678 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 679 struct tegra_framebuffer *tegra_fb = atomic ? 680 to_tegra_framebuffer(fb) : 681 to_tegra_framebuffer(crtc->primary->fb); 682 683 uint64_t paddr = (uint64_t)tegra_fb->obj->dmamap->dm_segs[0].ds_addr; 684 685 /* Framebuffer start address */ 686 DC_WRITE(tegra_crtc, DC_WINBUF_A_START_ADDR_HI_REG, (paddr >> 32) & 3); 687 DC_WRITE(tegra_crtc, DC_WINBUF_A_START_ADDR_REG, paddr & 0xffffffff); 688 689 /* Offsets */ 690 DC_WRITE(tegra_crtc, DC_WINBUF_A_ADDR_H_OFFSET_REG, x); 691 DC_WRITE(tegra_crtc, DC_WINBUF_A_ADDR_V_OFFSET_REG, y); 692 693 /* Surface kind */ 694 DC_WRITE(tegra_crtc, DC_WINBUF_A_SURFACE_KIND_REG, 695 __SHIFTIN(DC_WINBUF_A_SURFACE_KIND_SURFACE_KIND_PITCH, 696 DC_WINBUF_A_SURFACE_KIND_SURFACE_KIND)); 697 698 return 0; 699 } 700 701 static int 702 tegra_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 703 struct drm_framebuffer *old_fb) 704 { 705 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 706 707 tegra_crtc_do_set_base(crtc, old_fb, x, y, 0); 708 709 /* Commit settings */ 710 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 711 DC_CMD_STATE_CONTROL_WIN_A_UPDATE); 712 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 713 DC_CMD_STATE_CONTROL_WIN_A_ACT_REQ); 714 715 return 0; 716 } 717 718 static int 719 tegra_crtc_mode_set_base_atomic(struct drm_crtc *crtc, 720 struct drm_framebuffer *fb, int x, int y, enum mode_set_atomic state) 721 { 722 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 723 724 tegra_crtc_do_set_base(crtc, fb, x, y, 1); 725 726 /* Commit settings */ 727 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 728 DC_CMD_STATE_CONTROL_WIN_A_UPDATE); 729 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 730 DC_CMD_STATE_CONTROL_WIN_A_ACT_REQ); 731 732 return 0; 733 } 734 735 static void 736 tegra_crtc_disable(struct drm_crtc *crtc) 737 { 738 } 739 740 static void 741 tegra_crtc_prepare(struct drm_crtc *crtc) 742 { 743 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 744 745 /* Access control */ 746 DC_WRITE(tegra_crtc, DC_CMD_STATE_ACCESS_REG, 0); 747 748 /* Enable window A programming */ 749 DC_WRITE(tegra_crtc, DC_CMD_DISPLAY_WINDOW_HEADER_REG, 750 DC_CMD_DISPLAY_WINDOW_HEADER_WINDOW_A_SELECT); 751 } 752 753 static void 754 tegra_crtc_commit(struct drm_crtc *crtc) 755 { 756 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 757 758 /* Enable continuous display mode */ 759 DC_WRITE(tegra_crtc, DC_CMD_DISPLAY_COMMAND_REG, 760 __SHIFTIN(DC_CMD_DISPLAY_COMMAND_DISPLAY_CTRL_MODE_C_DISPLAY, 761 DC_CMD_DISPLAY_COMMAND_DISPLAY_CTRL_MODE)); 762 763 /* Enable power */ 764 DC_SET_CLEAR(tegra_crtc, DC_CMD_DISPLAY_POWER_CONTROL_REG, 765 DC_CMD_DISPLAY_POWER_CONTROL_PM1_ENABLE | 766 DC_CMD_DISPLAY_POWER_CONTROL_PM0_ENABLE | 767 DC_CMD_DISPLAY_POWER_CONTROL_PW4_ENABLE | 768 DC_CMD_DISPLAY_POWER_CONTROL_PW3_ENABLE | 769 DC_CMD_DISPLAY_POWER_CONTROL_PW2_ENABLE | 770 DC_CMD_DISPLAY_POWER_CONTROL_PW1_ENABLE | 771 DC_CMD_DISPLAY_POWER_CONTROL_PW0_ENABLE, 772 0); 773 774 /* Commit settings */ 775 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 776 DC_CMD_STATE_CONTROL_GENERAL_UPDATE | 777 DC_CMD_STATE_CONTROL_WIN_A_UPDATE); 778 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 779 DC_CMD_STATE_CONTROL_GENERAL_ACT_REQ | 780 DC_CMD_STATE_CONTROL_WIN_A_ACT_REQ); 781 782 tegra_crtc->enabled = true; 783 } 784 785 static int 786 tegra_encoder_init(struct drm_device *ddev) 787 { 788 struct tegra_drm_softc * const sc = tegra_drm_private(ddev); 789 struct tegra_encoder *encoder; 790 int error; 791 792 if (sc->sc_clk_hdmi == NULL || 793 sc->sc_clk_hdmi_parent == NULL || 794 sc->sc_rst_hdmi == NULL) { 795 DRM_ERROR("no clocks configured for hdmi\n"); 796 DRM_ERROR("clk: hdmi %p parent %p\n", sc->sc_clk_hdmi, sc->sc_clk_hdmi_parent); 797 DRM_ERROR("rst: hdmi %p\n", sc->sc_rst_hdmi); 798 return -EIO; 799 } 800 801 encoder = kmem_zalloc(sizeof(*encoder), KM_SLEEP); 802 if (encoder == NULL) 803 return -ENOMEM; 804 805 const bus_addr_t offset = TEGRA_GHOST_BASE + TEGRA_HDMI_OFFSET; 806 const bus_size_t size = TEGRA_HDMI_SIZE; 807 808 encoder->bst = sc->sc_bst; 809 error = bus_space_map(encoder->bst, offset, size, 0, &encoder->bsh); 810 if (error) { 811 kmem_free(encoder, sizeof(*encoder)); 812 return -error; 813 } 814 encoder->size = size; 815 816 tegra_pmc_hdmi_enable(); 817 818 /* Enable parent PLL */ 819 error = clk_set_rate(sc->sc_clk_hdmi_parent, 594000000); 820 if (error) { 821 DRM_ERROR("couldn't set hdmi parent PLL rate: %d\n", error); 822 return -error; 823 } 824 error = clk_enable(sc->sc_clk_hdmi_parent); 825 if (error) { 826 DRM_ERROR("couldn't enable hdmi parent PLL: %d\n", error); 827 return -error; 828 } 829 830 drm_encoder_init(ddev, &encoder->base, &tegra_encoder_funcs, 831 DRM_MODE_ENCODER_TMDS); 832 drm_encoder_helper_add(&encoder->base, &tegra_encoder_helper_funcs); 833 834 encoder->base.possible_crtcs = (1 << 0) | (1 << 1); 835 836 return tegra_connector_init(ddev, &encoder->base); 837 } 838 839 static void 840 tegra_encoder_destroy(struct drm_encoder *encoder) 841 { 842 struct tegra_encoder *tegra_encoder = to_tegra_encoder(encoder); 843 drm_encoder_cleanup(encoder); 844 kmem_free(tegra_encoder, sizeof(*tegra_encoder)); 845 } 846 847 static void 848 tegra_encoder_dpms(struct drm_encoder *encoder, int mode) 849 { 850 struct tegra_encoder *tegra_encoder = to_tegra_encoder(encoder); 851 852 if (encoder->crtc == NULL) 853 return; 854 855 switch (mode) { 856 case DRM_MODE_DPMS_ON: 857 case DRM_MODE_DPMS_STANDBY: 858 case DRM_MODE_DPMS_SUSPEND: 859 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_BLANK_REG, 860 0, HDMI_NV_PDISP_SOR_BLANK_OVERRIDE); 861 break; 862 case DRM_MODE_DPMS_OFF: 863 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_BLANK_REG, 864 HDMI_NV_PDISP_SOR_BLANK_OVERRIDE, 0); 865 break; 866 } 867 } 868 869 static bool 870 tegra_encoder_mode_fixup(struct drm_encoder *encoder, 871 const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) 872 { 873 return true; 874 } 875 876 static int 877 tegra_encoder_hdmi_set_clock(struct drm_encoder *encoder, u_int rate) 878 { 879 struct drm_device *ddev = encoder->dev; 880 struct tegra_drm_softc * const sc = tegra_drm_private(ddev); 881 int error; 882 883 /* Enter reset */ 884 fdtbus_reset_assert(sc->sc_rst_hdmi); 885 886 /* Set HDMI parent clock */ 887 error = clk_set_parent(sc->sc_clk_hdmi, sc->sc_clk_hdmi_parent); 888 if (error) { 889 DRM_ERROR("couldn't set hdmi parent: %d\n", error); 890 return -error; 891 } 892 893 /* Set dot clock frequency */ 894 error = clk_set_rate(sc->sc_clk_hdmi, rate); 895 if (error) { 896 DRM_ERROR("couldn't set hdmi clock: %d\n", error); 897 return -error; 898 } 899 error = clk_enable(sc->sc_clk_hdmi); 900 if (error) { 901 DRM_ERROR("couldn't enable hdmi clock: %d\n", error); 902 return -error; 903 } 904 905 /* Leave reset */ 906 fdtbus_reset_deassert(sc->sc_rst_hdmi); 907 908 return 0; 909 } 910 911 static void 912 tegra_encoder_mode_set(struct drm_encoder *encoder, 913 struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) 914 { 915 struct drm_device *ddev = encoder->dev; 916 struct tegra_encoder *tegra_encoder = to_tegra_encoder(encoder); 917 struct tegra_crtc *tegra_crtc = to_tegra_crtc(encoder->crtc); 918 struct tegra_connector *tegra_connector = NULL; 919 struct drm_connector *connector; 920 const struct tegra_hdmi_tmds_config *tmds = NULL; 921 uint32_t input_ctrl; 922 int retry; 923 u_int i; 924 925 tegra_encoder_hdmi_set_clock(encoder, mode->crtc_clock * 1000); 926 927 /* find the connector for this encoder */ 928 list_for_each_entry(connector, &ddev->mode_config.connector_list, head) { 929 if (connector->encoder == encoder) { 930 tegra_connector = to_tegra_connector(connector); 931 break; 932 } 933 } 934 935 for (i = 0; i < __arraycount(tegra_hdmi_tmds_config); i++) { 936 if (tegra_hdmi_tmds_config[i].dot_clock >= mode->crtc_clock) { 937 break; 938 } 939 } 940 if (i < __arraycount(tegra_hdmi_tmds_config)) { 941 tmds = &tegra_hdmi_tmds_config[i]; 942 } else { 943 tmds = &tegra_hdmi_tmds_config[__arraycount(tegra_hdmi_tmds_config) - 1]; 944 } 945 946 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PLL0_REG, tmds->sor_pll0); 947 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PLL1_REG, tmds->sor_pll1); 948 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT_REG, 949 tmds->sor_lane_drive_current); 950 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_PE_CURRENT_REG, 951 tmds->pe_current); 952 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT_REG, 953 tmds->sor_io_peak_current); 954 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PAD_CTLS0_REG, 955 tmds->sor_pad_ctls0); 956 957 const u_int div = (mode->crtc_clock / 1000) * 4; 958 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_REFCLK_REG, 959 __SHIFTIN(div >> 2, HDMI_NV_PDISP_SOR_REFCLK_DIV_INT) | 960 __SHIFTIN(div & 3, HDMI_NV_PDISP_SOR_REFCLK_DIV_FRAC)); 961 962 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_CSTM_REG, 963 __SHIFTIN(HDMI_NV_PDISP_SOR_CSTM_MODE_TMDS, 964 HDMI_NV_PDISP_SOR_CSTM_MODE) | 965 __SHIFTIN(2, HDMI_NV_PDISP_SOR_CSTM_ROTCLK) | 966 HDMI_NV_PDISP_SOR_CSTM_PLLDIV, 967 HDMI_NV_PDISP_SOR_CSTM_MODE | 968 HDMI_NV_PDISP_SOR_CSTM_ROTCLK | 969 HDMI_NV_PDISP_SOR_CSTM_LVDS_EN); 970 971 const uint32_t inst = 972 HDMI_NV_PDISP_SOR_SEQ_INST_DRIVE_PWM_OUT_LO | 973 HDMI_NV_PDISP_SOR_SEQ_INST_HALT | 974 __SHIFTIN(2, HDMI_NV_PDISP_SOR_SEQ_INST_WAIT_UNITS) | 975 __SHIFTIN(1, HDMI_NV_PDISP_SOR_SEQ_INST_WAIT_TIME); 976 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_SEQ_INST0_REG, inst); 977 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_SEQ_INST8_REG, inst); 978 979 input_ctrl = __SHIFTIN(tegra_crtc->index, 980 HDMI_NV_PDISP_INPUT_CONTROL_HDMI_SRC_SELECT); 981 if (mode->crtc_hdisplay != 640 || mode->crtc_vdisplay != 480) 982 input_ctrl |= HDMI_NV_PDISP_INPUT_CONTROL_ARM_VIDEO_RANGE; 983 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_INPUT_CONTROL_REG, input_ctrl); 984 985 /* Start SOR */ 986 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_PLL0_REG, 987 0, 988 HDMI_NV_PDISP_SOR_PLL0_PWR | 989 HDMI_NV_PDISP_SOR_PLL0_VCOPD | 990 HDMI_NV_PDISP_SOR_PLL0_PULLDOWN); 991 delay(10); 992 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_PLL0_REG, 993 0, 994 HDMI_NV_PDISP_SOR_PLL0_PDBG); 995 996 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PWR_REG, 997 HDMI_NV_PDISP_SOR_PWR_NORMAL_STATE | 998 HDMI_NV_PDISP_SOR_PWR_SETTING_NEW); 999 1000 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PWR_REG, 1001 HDMI_NV_PDISP_SOR_PWR_NORMAL_STATE); 1002 1003 for (retry = 10000; retry > 0; retry--) { 1004 const uint32_t pwr = HDMI_READ(tegra_encoder, 1005 HDMI_NV_PDISP_SOR_PWR_REG); 1006 if ((pwr & HDMI_NV_PDISP_SOR_PWR_SETTING_NEW) == 0) 1007 break; 1008 delay(10); 1009 } 1010 if (retry == 0) { 1011 DRM_ERROR("timeout enabling SOR power\n"); 1012 } 1013 1014 uint32_t state2 = 1015 __SHIFTIN(1, HDMI_NV_PDISP_SOR_STATE2_ASY_OWNER) | 1016 __SHIFTIN(3, HDMI_NV_PDISP_SOR_STATE2_ASY_SUBOWNER) | 1017 __SHIFTIN(1, HDMI_NV_PDISP_SOR_STATE2_ASY_CRCMODE) | 1018 __SHIFTIN(1, HDMI_NV_PDISP_SOR_STATE2_ASY_PROTOCOL); 1019 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 1020 state2 |= HDMI_NV_PDISP_SOR_STATE2_ASY_HSYNCPOL; 1021 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 1022 state2 |= HDMI_NV_PDISP_SOR_STATE2_ASY_VSYNCPOL; 1023 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_STATE2_REG, state2); 1024 1025 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_STATE1_REG, 1026 __SHIFTIN(HDMI_NV_PDISP_SOR_STATE1_ASY_HEAD_OPMODE_AWAKE, 1027 HDMI_NV_PDISP_SOR_STATE1_ASY_HEAD_OPMODE) | 1028 HDMI_NV_PDISP_SOR_STATE1_ASY_ORMODE); 1029 1030 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_STATE0_REG, 0); 1031 1032 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_STATE0_REG, 1033 HDMI_NV_PDISP_SOR_STATE0_UPDATE); 1034 1035 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_STATE1_REG, 1036 HDMI_NV_PDISP_SOR_STATE1_ATTACHED, 0); 1037 1038 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_STATE0_REG, 0); 1039 1040 const u_int rekey = 56; 1041 const u_int hspw = mode->hsync_end - mode->hsync_start; 1042 const u_int hbp = mode->htotal - mode->hsync_end; 1043 const u_int hfp = mode->hsync_start - mode->hdisplay; 1044 const u_int max_ac_packet = (hspw + hbp + hfp - rekey - 18) / 32; 1045 uint32_t ctrl = 1046 __SHIFTIN(rekey, HDMI_NV_PDISP_HDMI_CTRL_REKEY) | 1047 __SHIFTIN(max_ac_packet, HDMI_NV_PDISP_HDMI_CTRL_MAX_AC_PACKET); 1048 if (tegra_connector && tegra_connector->has_hdmi_sink) { 1049 ctrl |= HDMI_NV_PDISP_HDMI_CTRL_ENABLE; /* HDMI ENABLE */ 1050 } 1051 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_HDMI_CTRL_REG, ctrl); 1052 1053 if (tegra_connector && tegra_connector->has_hdmi_sink && 1054 tegra_connector->has_audio) { 1055 struct hdmi_audio_infoframe ai; 1056 struct hdmi_avi_infoframe avii; 1057 uint8_t aibuf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE]; 1058 uint8_t aviibuf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 1059 const u_int n = 6144; /* 48 kHz */ 1060 const u_int cts = ((mode->crtc_clock * 10) * (n / 128)) / 480; 1061 1062 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_REG, 1063 __SHIFTIN(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO, 1064 HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SOURCE_SELECT) | 1065 HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_INJECT_NULLSMPL); 1066 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_AUDIO_N_REG, 1067 HDMI_NV_PDISP_AUDIO_N_RESETF | 1068 HDMI_NV_PDISP_AUDIO_N_GENERATE | 1069 __SHIFTIN(n - 1, HDMI_NV_PDISP_AUDIO_N_VALUE)); 1070 1071 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_HDMI_SPARE_REG, 1072 HDMI_NV_PDISP_HDMI_SPARE_HW_CTS | 1073 HDMI_NV_PDISP_HDMI_SPARE_FORCE_SW_CTS | 1074 __SHIFTIN(1, HDMI_NV_PDISP_HDMI_SPARE_CTS_RESET_VAL)); 1075 1076 /* 1077 * When HW_CTS=1 and FORCE_SW_CTS=1, the CTS is programmed by 1078 * software in the 44.1 kHz register regardless of chosen rate. 1079 */ 1080 HDMI_WRITE(tegra_encoder, 1081 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW_REG, 1082 cts << 8); 1083 HDMI_WRITE(tegra_encoder, 1084 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH_REG, 1085 0x80000000 | n); 1086 1087 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_AUDIO_N_REG, 0, 1088 HDMI_NV_PDISP_AUDIO_N_RESETF); 1089 1090 HDMI_WRITE(tegra_encoder, 1091 HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480_REG, 24000); 1092 1093 hdmi_audio_infoframe_init(&ai); 1094 ai.channels = 2; 1095 hdmi_audio_infoframe_pack(&ai, aibuf, sizeof(aibuf)); 1096 HDMI_WRITE(tegra_encoder, 1097 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER_REG, 1098 aibuf[0] | (aibuf[1] << 8) | (aibuf[2] << 16)); 1099 HDMI_WRITE(tegra_encoder, 1100 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_REG, 1101 aibuf[3] | (aibuf[4] << 8) | 1102 (aibuf[5] << 16) | (aibuf[6] << 24)); 1103 HDMI_WRITE(tegra_encoder, 1104 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_REG, 1105 aibuf[7] | (aibuf[8] << 8) | (aibuf[9] << 16)); 1106 1107 hdmi_avi_infoframe_init(&avii); 1108 drm_hdmi_avi_infoframe_from_display_mode(&avii, mode); 1109 hdmi_avi_infoframe_pack(&avii, aviibuf, sizeof(aviibuf)); 1110 HDMI_WRITE(tegra_encoder, 1111 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER_REG, 1112 aviibuf[0] | (aviibuf[1] << 8) | (aviibuf[2] << 16)); 1113 HDMI_WRITE(tegra_encoder, 1114 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_REG, 1115 aviibuf[3] | (aviibuf[4] << 8) | 1116 (aviibuf[5] << 16) | (aviibuf[6] << 24)); 1117 HDMI_WRITE(tegra_encoder, 1118 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_REG, 1119 aviibuf[7] | (aviibuf[8] << 8) | (aviibuf[9] << 16)); 1120 HDMI_WRITE(tegra_encoder, 1121 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_REG, 1122 aviibuf[10] | (aviibuf[11] << 8) | 1123 (aviibuf[12] << 16) | (aviibuf[13] << 24)); 1124 HDMI_WRITE(tegra_encoder, 1125 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_REG, 1126 aviibuf[14] | (aviibuf[15] << 8) | (aviibuf[16] << 16)); 1127 1128 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_HDMI_GENERIC_CTRL_REG, 1129 HDMI_NV_PDISP_HDMI_GENERIC_CTRL_AUDIO); 1130 HDMI_WRITE(tegra_encoder, 1131 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_REG, 1132 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_ENABLE); 1133 HDMI_WRITE(tegra_encoder, 1134 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_REG, 1135 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_ENABLE); 1136 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_HDMI_ACR_CTRL_REG, 0); 1137 } else { 1138 HDMI_WRITE(tegra_encoder, 1139 HDMI_NV_PDISP_HDMI_GENERIC_CTRL_REG, 0); 1140 HDMI_WRITE(tegra_encoder, 1141 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_REG, 0); 1142 HDMI_WRITE(tegra_encoder, 1143 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_REG, 0); 1144 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_HDMI_ACR_CTRL_REG, 0); 1145 } 1146 1147 /* Enable DC output to HDMI */ 1148 DC_SET_CLEAR(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG, 1149 DC_DISP_DISP_WIN_OPTIONS_HDMI_ENABLE, 0); 1150 1151 /* Commit settings */ 1152 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 1153 DC_CMD_STATE_CONTROL_GENERAL_UPDATE | 1154 DC_CMD_STATE_CONTROL_WIN_A_UPDATE); 1155 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 1156 DC_CMD_STATE_CONTROL_GENERAL_ACT_REQ | 1157 DC_CMD_STATE_CONTROL_WIN_A_ACT_REQ); 1158 } 1159 1160 static void 1161 tegra_encoder_prepare(struct drm_encoder *encoder) 1162 { 1163 } 1164 1165 static void 1166 tegra_encoder_commit(struct drm_encoder *encoder) 1167 { 1168 } 1169 1170 static int 1171 tegra_connector_init(struct drm_device *ddev, struct drm_encoder *encoder) 1172 { 1173 struct tegra_drm_softc * const sc = tegra_drm_private(ddev); 1174 struct tegra_connector *connector; 1175 1176 connector = kmem_zalloc(sizeof(*connector), KM_SLEEP); 1177 if (connector == NULL) 1178 return -ENOMEM; 1179 1180 drm_connector_init(ddev, &connector->base, &tegra_connector_funcs, 1181 DRM_MODE_CONNECTOR_HDMIA); 1182 drm_connector_helper_add(&connector->base, 1183 &tegra_connector_helper_funcs); 1184 1185 connector->base.interlace_allowed = 0; 1186 connector->base.doublescan_allowed = 0; 1187 1188 drm_sysfs_connector_add(&connector->base); 1189 1190 connector->base.polled = 1191 DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 1192 1193 drm_mode_connector_attach_encoder(&connector->base, encoder); 1194 1195 connector->hpd = sc->sc_pin_hpd; 1196 if (!connector->hpd) 1197 DRM_ERROR("failed to find hpd pin for connector\n"); 1198 1199 connector->ddc = sc->sc_ddc; 1200 if (!connector->ddc) 1201 DRM_ERROR("failed to find ddc device for connector\n"); 1202 1203 return 0; 1204 } 1205 1206 static void 1207 tegra_connector_destroy(struct drm_connector *connector) 1208 { 1209 struct tegra_connector *tegra_connector = to_tegra_connector(connector); 1210 1211 drm_sysfs_connector_remove(connector); 1212 drm_connector_cleanup(connector); 1213 kmem_free(tegra_connector, sizeof(*tegra_connector)); 1214 } 1215 1216 static enum drm_connector_status 1217 tegra_connector_detect(struct drm_connector *connector, bool force) 1218 { 1219 struct tegra_connector *tegra_connector = to_tegra_connector(connector); 1220 bool con; 1221 1222 1223 if (!tegra_connector->hpd) { 1224 tegra_connector->has_hdmi_sink = false; 1225 tegra_connector->has_audio = false; 1226 return connector_status_connected; 1227 } 1228 1229 con = fdtbus_gpio_read(tegra_connector->hpd); 1230 if (con) { 1231 return connector_status_connected; 1232 } else { 1233 prop_dictionary_t prop = device_properties(connector->dev->dev); 1234 prop_dictionary_remove(prop, "physical-address"); 1235 tegra_connector->has_hdmi_sink = false; 1236 tegra_connector->has_audio = false; 1237 return connector_status_disconnected; 1238 } 1239 } 1240 1241 static int 1242 tegra_connector_mode_valid(struct drm_connector *connector, 1243 struct drm_display_mode *mode) 1244 { 1245 return MODE_OK; 1246 } 1247 1248 static int 1249 tegra_connector_get_modes(struct drm_connector *connector) 1250 { 1251 struct tegra_connector *tegra_connector = to_tegra_connector(connector); 1252 struct tegra_drm_softc * const sc = tegra_drm_private(connector->dev); 1253 prop_dictionary_t prop = device_properties(connector->dev->dev); 1254 char edid[EDID_LENGTH * 4]; 1255 struct edid *pedid = NULL; 1256 int error, block; 1257 1258 if (tegra_connector->ddc) { 1259 memset(edid, 0, sizeof(edid)); 1260 for (block = 0; block < 4; block++) { 1261 error = ddc_read_edid_block(tegra_connector->ddc, 1262 &edid[block * EDID_LENGTH], EDID_LENGTH, block); 1263 if (error) 1264 break; 1265 if (block == 0) { 1266 pedid = (struct edid *)edid; 1267 if (edid[0x7e] == 0) 1268 break; 1269 } 1270 } 1271 } 1272 1273 if (pedid) { 1274 if (sc->sc_force_dvi) { 1275 tegra_connector->has_hdmi_sink = false; 1276 tegra_connector->has_audio = false; 1277 } else { 1278 tegra_connector->has_hdmi_sink = 1279 drm_detect_hdmi_monitor(pedid); 1280 tegra_connector->has_audio = 1281 drm_detect_monitor_audio(pedid); 1282 } 1283 drm_mode_connector_update_edid_property(connector, pedid); 1284 error = drm_add_edid_modes(connector, pedid); 1285 drm_edid_to_eld(connector, pedid); 1286 if (drm_detect_hdmi_monitor(pedid)) { 1287 prop_dictionary_set_uint16(prop, "physical-address", 1288 connector->physical_address); 1289 } 1290 return error; 1291 } else { 1292 drm_mode_connector_update_edid_property(connector, NULL); 1293 return 0; 1294 } 1295 } 1296 1297 static struct drm_encoder * 1298 tegra_connector_best_encoder(struct drm_connector *connector) 1299 { 1300 int enc_id = connector->encoder_ids[0]; 1301 struct drm_mode_object *obj; 1302 struct drm_encoder *encoder = NULL; 1303 1304 if (enc_id) { 1305 obj = drm_mode_object_find(connector->dev, enc_id, 1306 DRM_MODE_OBJECT_ENCODER); 1307 if (obj == NULL) 1308 return NULL; 1309 encoder = obj_to_encoder(obj); 1310 } 1311 1312 return encoder; 1313 } 1314 1315 static int 1316 tegra_crtc_intr(void *priv) 1317 { 1318 struct tegra_crtc *tegra_crtc = priv; 1319 struct drm_device *ddev = tegra_crtc->base.dev; 1320 struct tegra_drm_softc * const sc = tegra_drm_private(ddev); 1321 int rv = 0; 1322 1323 const uint32_t status = DC_READ(tegra_crtc, DC_CMD_INT_STATUS_REG); 1324 1325 if (status & DC_CMD_INT_V_BLANK) { 1326 DC_WRITE(tegra_crtc, DC_CMD_INT_STATUS_REG, DC_CMD_INT_V_BLANK); 1327 atomic_inc_32(&sc->sc_vbl_received[tegra_crtc->index]); 1328 drm_handle_vblank(ddev, tegra_crtc->index); 1329 rv = 1; 1330 } 1331 1332 return rv; 1333 } 1334 1335 u32 1336 tegra_drm_get_vblank_counter(struct drm_device *ddev, int crtc) 1337 { 1338 struct tegra_drm_softc * const sc = tegra_drm_private(ddev); 1339 1340 if (crtc > 1) 1341 return 0; 1342 1343 return sc->sc_vbl_received[crtc]; 1344 } 1345 1346 int 1347 tegra_drm_enable_vblank(struct drm_device *ddev, int crtc) 1348 { 1349 struct tegra_crtc *tegra_crtc = NULL; 1350 struct drm_crtc *iter; 1351 1352 list_for_each_entry(iter, &ddev->mode_config.crtc_list, head) { 1353 if (to_tegra_crtc(iter)->index == crtc) { 1354 tegra_crtc = to_tegra_crtc(iter); 1355 break; 1356 } 1357 } 1358 if (tegra_crtc == NULL) 1359 return -EINVAL; 1360 1361 DC_SET_CLEAR(tegra_crtc, DC_CMD_INT_MASK_REG, DC_CMD_INT_V_BLANK, 0); 1362 1363 return 0; 1364 } 1365 1366 void 1367 tegra_drm_disable_vblank(struct drm_device *ddev, int crtc) 1368 { 1369 struct tegra_crtc *tegra_crtc = NULL; 1370 struct drm_crtc *iter; 1371 1372 list_for_each_entry(iter, &ddev->mode_config.crtc_list, head) { 1373 if (to_tegra_crtc(iter)->index == crtc) { 1374 tegra_crtc = to_tegra_crtc(iter); 1375 break; 1376 } 1377 } 1378 if (tegra_crtc == NULL) 1379 return; 1380 1381 DC_SET_CLEAR(tegra_crtc, DC_CMD_INT_MASK_REG, 0, DC_CMD_INT_V_BLANK); 1382 DC_WRITE(tegra_crtc, DC_CMD_INT_STATUS_REG, DC_CMD_INT_V_BLANK); 1383 } 1384
Indexes created Fri Oct 17 00:09:41 GMT 2025