tegra_drm_mode.c revision 1.15
1 /* $NetBSD: tegra_drm_mode.c,v 1.15 2017/06/01 02:45:05 chs Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_drm_mode.c,v 1.15 2017/06/01 02:45:05 chs Exp $"); 31 32 #include <drm/drmP.h> 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_crtc_helper.h> 35 #include <drm/drm_edid.h> 36 37 #include <dev/i2c/ddcvar.h> 38 39 #include <arm/nvidia/tegra_reg.h> 40 #include <arm/nvidia/tegra_var.h> 41 #include <arm/nvidia/tegra_intr.h> 42 #include <arm/nvidia/tegra_pmcreg.h> 43 #include <arm/nvidia/tegra_dcreg.h> 44 #include <arm/nvidia/tegra_hdmireg.h> 45 #include <arm/nvidia/tegra_drm.h> 46 47 #include <dev/fdt/fdtvar.h> 48 49 static struct drm_framebuffer *tegra_fb_create(struct drm_device *, 50 struct drm_file *, struct drm_mode_fb_cmd2 *); 51 52 static const struct drm_mode_config_funcs tegra_mode_config_funcs = { 53 .fb_create = tegra_fb_create 54 }; 55 56 static int tegra_framebuffer_create_handle(struct drm_framebuffer *, 57 struct drm_file *, unsigned int *); 58 static void tegra_framebuffer_destroy(struct drm_framebuffer *); 59 60 static const struct drm_framebuffer_funcs tegra_framebuffer_funcs = { 61 .create_handle = tegra_framebuffer_create_handle, 62 .destroy = tegra_framebuffer_destroy 63 }; 64 65 static int tegra_crtc_init(struct drm_device *, int); 66 static void tegra_crtc_destroy(struct drm_crtc *); 67 static int tegra_crtc_cursor_set(struct drm_crtc *, struct drm_file *, 68 uint32_t, uint32_t, uint32_t); 69 static int tegra_crtc_cursor_move(struct drm_crtc *, int, int); 70 static int tegra_crtc_intr(void *); 71 72 static const struct drm_crtc_funcs tegra_crtc_funcs = { 73 .cursor_set = tegra_crtc_cursor_set, 74 .cursor_move = tegra_crtc_cursor_move, 75 .set_config = drm_crtc_helper_set_config, 76 .destroy = tegra_crtc_destroy 77 }; 78 79 static void tegra_crtc_dpms(struct drm_crtc *, int); 80 static bool tegra_crtc_mode_fixup(struct drm_crtc *, 81 const struct drm_display_mode *, 82 struct drm_display_mode *); 83 static int tegra_crtc_mode_set(struct drm_crtc *, 84 struct drm_display_mode *, struct drm_display_mode *, 85 int, int, struct drm_framebuffer *); 86 static int tegra_crtc_mode_set_base(struct drm_crtc *, 87 int, int, struct drm_framebuffer *); 88 static int tegra_crtc_mode_set_base_atomic(struct drm_crtc *, 89 struct drm_framebuffer *, int, int, enum mode_set_atomic); 90 static void tegra_crtc_disable(struct drm_crtc *); 91 static void tegra_crtc_prepare(struct drm_crtc *); 92 static void tegra_crtc_commit(struct drm_crtc *); 93 94 static int tegra_crtc_do_set_base(struct drm_crtc *, 95 struct drm_framebuffer *, int, int, int); 96 97 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = { 98 .dpms = tegra_crtc_dpms, 99 .mode_fixup = tegra_crtc_mode_fixup, 100 .mode_set = tegra_crtc_mode_set, 101 .mode_set_base = tegra_crtc_mode_set_base, 102 .mode_set_base_atomic = tegra_crtc_mode_set_base_atomic, 103 .disable = tegra_crtc_disable, 104 .prepare = tegra_crtc_prepare, 105 .commit = tegra_crtc_commit 106 }; 107 108 static int tegra_encoder_init(struct drm_device *); 109 static void tegra_encoder_destroy(struct drm_encoder *); 110 111 static const struct drm_encoder_funcs tegra_encoder_funcs = { 112 .destroy = tegra_encoder_destroy 113 }; 114 115 static void tegra_encoder_dpms(struct drm_encoder *, int); 116 static bool tegra_encoder_mode_fixup(struct drm_encoder *, 117 const struct drm_display_mode *, struct drm_display_mode *); 118 static void tegra_encoder_mode_set(struct drm_encoder *, 119 struct drm_display_mode *, struct drm_display_mode *); 120 static void tegra_encoder_prepare(struct drm_encoder *); 121 static void tegra_encoder_commit(struct drm_encoder *); 122 123 static const struct drm_encoder_helper_funcs tegra_encoder_helper_funcs = { 124 .dpms = tegra_encoder_dpms, 125 .mode_fixup = tegra_encoder_mode_fixup, 126 .prepare = tegra_encoder_prepare, 127 .commit = tegra_encoder_commit, 128 .mode_set = tegra_encoder_mode_set 129 }; 130 131 static int tegra_connector_init(struct drm_device *, struct drm_encoder *); 132 static void tegra_connector_destroy(struct drm_connector *); 133 static enum drm_connector_status tegra_connector_detect(struct drm_connector *, 134 bool); 135 136 static const struct drm_connector_funcs tegra_connector_funcs = { 137 .dpms = drm_helper_connector_dpms, 138 .detect = tegra_connector_detect, 139 .fill_modes = drm_helper_probe_single_connector_modes, 140 .destroy = tegra_connector_destroy 141 }; 142 143 static int tegra_connector_mode_valid(struct drm_connector *, 144 struct drm_display_mode *); 145 static int tegra_connector_get_modes(struct drm_connector *); 146 static struct drm_encoder *tegra_connector_best_encoder(struct drm_connector *); 147 148 static const struct drm_connector_helper_funcs tegra_connector_helper_funcs = { 149 .mode_valid = tegra_connector_mode_valid, 150 .get_modes = tegra_connector_get_modes, 151 .best_encoder = tegra_connector_best_encoder 152 }; 153 154 static const struct tegra_hdmi_tmds_config { 155 u_int dot_clock; 156 uint32_t sor_pll0; 157 uint32_t sor_pll1; 158 uint32_t sor_lane_drive_current; 159 uint32_t pe_current; 160 uint32_t sor_io_peak_current; 161 uint32_t sor_pad_ctls0; 162 uint32_t car_plld_misc; /* XXX unused? */ 163 } tegra_hdmi_tmds_config[] = { 164 /* 480p */ 165 { 27000, 0x01003010, 0x00301b00, 0x1f1f1f1f, 166 0x00000000, 0x03030303, 0x800034bb, 0x40400820 }, 167 /* 720p / 1080i */ 168 { 74250, 0x01003110, 0x00301500, 0x2c2c2c2c, 169 0x00000000, 0x07070707, 0x800034bb, 0x40400820 }, 170 /* 1080p */ 171 { 148500, 0x01003310, 0x00301500, 0x2d2d2d2d, 172 0x00000000, 0x05050505, 0x800034bb, 0x40400820 }, 173 /* 2160p */ 174 { 297000, 0x01003f10, 0x00300f00, 0x37373737, 175 0x00000000, 0x17171717, 0x800036bb, 0x40400f20 }, 176 }; 177 178 int 179 tegra_drm_mode_init(struct drm_device *ddev) 180 { 181 int error; 182 183 drm_mode_config_init(ddev); 184 ddev->mode_config.min_width = 0; 185 ddev->mode_config.min_height = 0; 186 ddev->mode_config.max_width = 4096; 187 ddev->mode_config.max_height = 2160; 188 ddev->mode_config.funcs = &tegra_mode_config_funcs; 189 190 error = tegra_crtc_init(ddev, 0); 191 if (error) 192 return error; 193 194 error = tegra_crtc_init(ddev, 1); 195 if (error) 196 return error; 197 198 error = tegra_encoder_init(ddev); 199 if (error) 200 return error; 201 202 error = drm_vblank_init(ddev, 2); 203 if (error) 204 return error; 205 206 return 0; 207 } 208 209 int 210 tegra_drm_framebuffer_init(struct drm_device *ddev, 211 struct tegra_framebuffer *fb) 212 { 213 return drm_framebuffer_init(ddev, &fb->base, &tegra_framebuffer_funcs); 214 } 215 216 static struct drm_framebuffer * 217 tegra_fb_create(struct drm_device *ddev, struct drm_file *file, 218 struct drm_mode_fb_cmd2 *cmd) 219 { 220 struct tegra_framebuffer *fb; 221 struct drm_gem_object *gem_obj; 222 int error; 223 224 if (cmd->flags) 225 return NULL; 226 if (cmd->pixel_format != DRM_FORMAT_ARGB8888 && 227 cmd->pixel_format != DRM_FORMAT_XRGB8888) { 228 return NULL; 229 } 230 231 gem_obj = drm_gem_object_lookup(ddev, file, cmd->handles[0]); 232 if (gem_obj == NULL) 233 return NULL; 234 235 fb = kmem_zalloc(sizeof(*fb), KM_SLEEP); 236 fb->obj = to_tegra_gem_obj(gem_obj); 237 fb->base.pitches[0] = cmd->pitches[0]; 238 fb->base.offsets[0] = cmd->offsets[0]; 239 fb->base.width = cmd->width; 240 fb->base.height = cmd->height; 241 fb->base.pixel_format = cmd->pixel_format; 242 drm_fb_get_bpp_depth(cmd->pixel_format, &fb->base.depth, 243 &fb->base.bits_per_pixel); 244 245 error = tegra_drm_framebuffer_init(ddev, fb); 246 if (error) 247 goto dealloc; 248 249 return &fb->base; 250 251 drm_framebuffer_cleanup(&fb->base); 252 dealloc: 253 kmem_free(fb, sizeof(*fb)); 254 drm_gem_object_unreference_unlocked(gem_obj); 255 256 return NULL; 257 } 258 259 static int 260 tegra_framebuffer_create_handle(struct drm_framebuffer *fb, 261 struct drm_file *file, unsigned int *handle) 262 { 263 struct tegra_framebuffer *tegra_fb = to_tegra_framebuffer(fb); 264 265 return drm_gem_handle_create(file, &tegra_fb->obj->base, handle); 266 } 267 268 static void 269 tegra_framebuffer_destroy(struct drm_framebuffer *fb) 270 { 271 struct tegra_framebuffer *tegra_fb = to_tegra_framebuffer(fb); 272 273 drm_framebuffer_cleanup(fb); 274 drm_gem_object_unreference_unlocked(&tegra_fb->obj->base); 275 kmem_free(tegra_fb, sizeof(*tegra_fb)); 276 } 277 278 static int 279 tegra_crtc_init(struct drm_device *ddev, int index) 280 { 281 struct tegra_drm_softc * const sc = tegra_drm_private(ddev); 282 struct tegra_crtc *crtc; 283 bus_addr_t offset; 284 bus_size_t size; 285 u_int intr; 286 int error; 287 288 if (sc->sc_clk_dc[index] == NULL || 289 sc->sc_clk_hdmi_parent == NULL || 290 sc->sc_rst_dc[index] == NULL) { 291 DRM_ERROR("no clocks configured for crtc %d\n", index); 292 return -EIO; 293 } 294 295 switch (index) { 296 case 0: 297 offset = TEGRA_GHOST_BASE + TEGRA_DISPLAYA_OFFSET; 298 size = TEGRA_DISPLAYA_SIZE; 299 intr = TEGRA_INTR_DISPLAYA; 300 break; 301 case 1: 302 offset = TEGRA_GHOST_BASE + TEGRA_DISPLAYB_OFFSET; 303 size = TEGRA_DISPLAYB_SIZE; 304 intr = TEGRA_INTR_DISPLAYB; 305 break; 306 default: 307 return -EINVAL; 308 } 309 310 crtc = kmem_zalloc(sizeof(*crtc), KM_SLEEP); 311 crtc->index = index; 312 crtc->bst = sc->sc_bst; 313 error = bus_space_map(crtc->bst, offset, size, 0, &crtc->bsh); 314 if (error) { 315 kmem_free(crtc, sizeof(*crtc)); 316 return -error; 317 } 318 crtc->size = size; 319 crtc->intr = intr; 320 crtc->ih = intr_establish(intr, IPL_VM, IST_LEVEL | IST_MPSAFE, 321 tegra_crtc_intr, crtc); 322 if (crtc->ih == NULL) { 323 DRM_ERROR("failed to establish interrupt for crtc %d\n", index); 324 } 325 const size_t cursor_size = 256 * 256 * 4; 326 crtc->cursor_obj = tegra_drm_obj_alloc(ddev, cursor_size); 327 if (crtc->cursor_obj == NULL) { 328 kmem_free(crtc, sizeof(*crtc)); 329 return -ENOMEM; 330 } 331 332 /* Enter reset */ 333 fdtbus_reset_assert(sc->sc_rst_dc[index]); 334 335 /* Turn on power to display partition */ 336 const u_int pmc_partid = index == 0 ? PMC_PARTID_DIS : PMC_PARTID_DISB; 337 tegra_pmc_power(pmc_partid, true); 338 tegra_pmc_remove_clamping(pmc_partid); 339 340 /* Set parent clock to the HDMI parent (ignoring DC parent in DT!) */ 341 error = clk_set_parent(sc->sc_clk_dc[index], 342 sc->sc_clk_hdmi_parent); 343 if (error) { 344 DRM_ERROR("failed to set crtc %d clock parent: %d\n", 345 index, error); 346 return -error; 347 } 348 349 /* Enable DC clock */ 350 error = clk_enable(sc->sc_clk_dc[index]); 351 if (error) { 352 DRM_ERROR("failed to enable crtc %d clock: %d\n", index, error); 353 return -error; 354 } 355 356 /* Leave reset */ 357 fdtbus_reset_deassert(sc->sc_rst_dc[index]); 358 359 crtc->clk_parent = sc->sc_clk_hdmi_parent; 360 361 DC_WRITE(crtc, DC_CMD_INT_ENABLE_REG, DC_CMD_INT_V_BLANK); 362 363 drm_crtc_init(ddev, &crtc->base, &tegra_crtc_funcs); 364 drm_crtc_helper_add(&crtc->base, &tegra_crtc_helper_funcs); 365 366 return 0; 367 } 368 369 static int 370 tegra_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, 371 uint32_t handle, uint32_t width, uint32_t height) 372 { 373 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 374 struct drm_gem_object *gem_obj = NULL; 375 struct tegra_gem_object *obj; 376 uint32_t cfg, opt; 377 int error; 378 379 if (tegra_crtc->enabled == false) 380 return 0; 381 382 if (handle == 0) { 383 /* hide cursor */ 384 opt = DC_READ(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG); 385 if ((opt & DC_DISP_DISP_WIN_OPTIONS_CURSOR_ENABLE) != 0) { 386 opt &= ~DC_DISP_DISP_WIN_OPTIONS_CURSOR_ENABLE; 387 DC_WRITE(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG, opt); 388 /* Commit settings */ 389 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 390 DC_CMD_STATE_CONTROL_GENERAL_UPDATE); 391 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 392 DC_CMD_STATE_CONTROL_GENERAL_ACT_REQ); 393 } 394 error = 0; 395 goto done; 396 } 397 398 if ((width != height) || 399 (width != 32 && width != 64 && width != 128 && width != 256)) { 400 DRM_ERROR("Cursor dimension %ux%u not supported\n", 401 width, height); 402 error = -EINVAL; 403 goto done; 404 } 405 406 gem_obj = drm_gem_object_lookup(crtc->dev, file_priv, handle); 407 if (gem_obj == NULL) { 408 DRM_ERROR("Cannot find cursor object %#x for crtc %d\n", 409 handle, tegra_crtc->index); 410 error = -ENOENT; 411 goto done; 412 } 413 obj = to_tegra_gem_obj(gem_obj); 414 415 if (obj->base.size < width * height * 4) { 416 DRM_ERROR("Cursor buffer is too small\n"); 417 error = -ENOMEM; 418 goto done; 419 } 420 421 cfg = __SHIFTIN(DC_DISP_CURSOR_START_ADDR_CLIPPING_DISPLAY, 422 DC_DISP_CURSOR_START_ADDR_CLIPPING); 423 switch (width) { 424 case 32: 425 cfg |= __SHIFTIN(DC_DISP_CURSOR_START_ADDR_SIZE_32, 426 DC_DISP_CURSOR_START_ADDR_SIZE); 427 break; 428 case 64: 429 cfg |= __SHIFTIN(DC_DISP_CURSOR_START_ADDR_SIZE_64, 430 DC_DISP_CURSOR_START_ADDR_SIZE); 431 break; 432 case 128: 433 cfg |= __SHIFTIN(DC_DISP_CURSOR_START_ADDR_SIZE_128, 434 DC_DISP_CURSOR_START_ADDR_SIZE); 435 break; 436 case 256: 437 cfg |= __SHIFTIN(DC_DISP_CURSOR_START_ADDR_SIZE_256, 438 DC_DISP_CURSOR_START_ADDR_SIZE); 439 break; 440 } 441 442 /* copy cursor (argb -> rgba) */ 443 struct tegra_gem_object *cursor_obj = tegra_crtc->cursor_obj; 444 uint32_t off, *cp = obj->dmap, *crtc_cp = cursor_obj->dmap; 445 for (off = 0; off < width * height; off++) { 446 crtc_cp[off] = (cp[off] << 8) | (cp[off] >> 24); 447 } 448 449 const uint64_t paddr = cursor_obj->dmasegs[0].ds_addr; 450 451 DC_WRITE(tegra_crtc, DC_DISP_CURSOR_START_ADDR_HI_REG, 452 (paddr >> 32) & 3); 453 cfg |= __SHIFTIN((paddr >> 10) & 0x3fffff, 454 DC_DISP_CURSOR_START_ADDR_ADDRESS_LO); 455 const uint32_t ocfg = 456 DC_READ(tegra_crtc, DC_DISP_CURSOR_START_ADDR_REG); 457 if (cfg != ocfg) { 458 DC_WRITE(tegra_crtc, DC_DISP_CURSOR_START_ADDR_REG, cfg); 459 } 460 461 cfg = DC_READ(tegra_crtc, DC_DISP_BLEND_CURSOR_CONTROL_REG); 462 cfg &= ~DC_DISP_BLEND_CURSOR_CONTROL_DST_BLEND_FACTOR_SEL; 463 cfg |= __SHIFTIN(2, DC_DISP_BLEND_CURSOR_CONTROL_DST_BLEND_FACTOR_SEL); 464 cfg &= ~DC_DISP_BLEND_CURSOR_CONTROL_SRC_BLEND_FACTOR_SEL; 465 cfg |= __SHIFTIN(1, DC_DISP_BLEND_CURSOR_CONTROL_SRC_BLEND_FACTOR_SEL); 466 cfg &= ~DC_DISP_BLEND_CURSOR_CONTROL_ALPHA; 467 cfg |= __SHIFTIN(255, DC_DISP_BLEND_CURSOR_CONTROL_ALPHA); 468 cfg |= DC_DISP_BLEND_CURSOR_CONTROL_MODE_SEL; 469 DC_WRITE(tegra_crtc, DC_DISP_BLEND_CURSOR_CONTROL_REG, cfg); 470 471 /* set cursor position */ 472 DC_WRITE(tegra_crtc, DC_DISP_CURSOR_POSITION_REG, 473 __SHIFTIN(tegra_crtc->cursor_x, DC_DISP_CURSOR_POSITION_H) | 474 __SHIFTIN(tegra_crtc->cursor_y, DC_DISP_CURSOR_POSITION_V)); 475 476 /* Commit settings */ 477 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 478 DC_CMD_STATE_CONTROL_CURSOR_UPDATE); 479 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 480 DC_CMD_STATE_CONTROL_CURSOR_ACT_REQ); 481 482 /* show cursor */ 483 opt = DC_READ(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG); 484 if ((opt & DC_DISP_DISP_WIN_OPTIONS_CURSOR_ENABLE) == 0) { 485 opt |= DC_DISP_DISP_WIN_OPTIONS_CURSOR_ENABLE; 486 DC_WRITE(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG, opt); 487 488 /* Commit settings */ 489 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 490 DC_CMD_STATE_CONTROL_GENERAL_UPDATE); 491 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 492 DC_CMD_STATE_CONTROL_GENERAL_ACT_REQ); 493 } 494 495 error = 0; 496 497 done: 498 if (error == 0) { 499 /* Wait for activation request to complete */ 500 while (DC_READ(tegra_crtc, DC_CMD_STATE_CONTROL_REG) & 501 DC_CMD_STATE_CONTROL_GENERAL_ACT_REQ) 502 ; 503 } 504 505 if (gem_obj) { 506 drm_gem_object_unreference_unlocked(gem_obj); 507 } 508 509 return error; 510 } 511 512 static int 513 tegra_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) 514 { 515 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 516 517 tegra_crtc->cursor_x = x & 0x3fff; 518 tegra_crtc->cursor_y = y & 0x3fff; 519 520 DC_WRITE(tegra_crtc, DC_DISP_CURSOR_POSITION_REG, 521 __SHIFTIN(x & 0x3fff, DC_DISP_CURSOR_POSITION_H) | 522 __SHIFTIN(y & 0x3fff, DC_DISP_CURSOR_POSITION_V)); 523 524 /* Commit settings */ 525 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 526 DC_CMD_STATE_CONTROL_CURSOR_UPDATE); 527 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 528 DC_CMD_STATE_CONTROL_CURSOR_ACT_REQ); 529 530 return 0; 531 } 532 533 static void 534 tegra_crtc_destroy(struct drm_crtc *crtc) 535 { 536 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 537 drm_crtc_cleanup(crtc); 538 if (tegra_crtc->ih) { 539 intr_disestablish(tegra_crtc->ih); 540 } 541 tegra_drm_obj_free(tegra_crtc->cursor_obj); 542 bus_space_unmap(tegra_crtc->bst, tegra_crtc->bsh, tegra_crtc->size); 543 kmem_free(tegra_crtc, sizeof(*tegra_crtc)); 544 } 545 546 static void 547 tegra_crtc_dpms(struct drm_crtc *crtc, int mode) 548 { 549 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 550 551 switch (mode) { 552 case DRM_MODE_DPMS_ON: 553 case DRM_MODE_DPMS_STANDBY: 554 case DRM_MODE_DPMS_SUSPEND: 555 DC_SET_CLEAR(tegra_crtc, DC_WINC_A_WIN_OPTIONS_REG, 556 DC_WINC_A_WIN_OPTIONS_WIN_ENABLE, 0); 557 break; 558 case DRM_MODE_DPMS_OFF: 559 DC_SET_CLEAR(tegra_crtc, DC_WINC_A_WIN_OPTIONS_REG, 560 0, DC_WINC_A_WIN_OPTIONS_WIN_ENABLE); 561 break; 562 } 563 } 564 565 static bool 566 tegra_crtc_mode_fixup(struct drm_crtc *crtc, 567 const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) 568 { 569 return true; 570 } 571 572 static int 573 tegra_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, 574 struct drm_display_mode *adjusted_mode, int x, int y, 575 struct drm_framebuffer *old_fb) 576 { 577 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 578 const u_int hspw = mode->crtc_hsync_end - mode->crtc_hsync_start; 579 const u_int hbp = mode->crtc_htotal - mode->crtc_hsync_end; 580 const u_int hfp = mode->crtc_hsync_start - mode->crtc_hdisplay; 581 const u_int vspw = mode->crtc_vsync_end - mode->crtc_vsync_start; 582 const u_int vbp = mode->crtc_vtotal - mode->crtc_vsync_end; 583 const u_int vfp = mode->crtc_vsync_start - mode->crtc_vdisplay; 584 585 /* Set colour depth to ARGB8888 */ 586 DC_WRITE(tegra_crtc, DC_WINC_A_COLOR_DEPTH_REG, 587 __SHIFTIN(DC_WINC_A_COLOR_DEPTH_DEPTH_T_A8R8G8B8, 588 DC_WINC_A_COLOR_DEPTH_DEPTH)); 589 590 /* Disable byte swapping */ 591 DC_WRITE(tegra_crtc, DC_WINC_A_BYTE_SWAP_REG, 592 __SHIFTIN(DC_WINC_A_BYTE_SWAP_SWAP_NOSWAP, 593 DC_WINC_A_BYTE_SWAP_SWAP)); 594 595 /* Initial DDA */ 596 DC_WRITE(tegra_crtc, DC_WINC_A_H_INITIAL_DDA_REG, 0); 597 DC_WRITE(tegra_crtc, DC_WINC_A_V_INITIAL_DDA_REG, 0); 598 DC_WRITE(tegra_crtc, DC_WINC_A_DDA_INCREMENT_REG, 0x10001000); 599 600 /* Window position, size, stride */ 601 DC_WRITE(tegra_crtc, DC_WINC_A_POSITION_REG, 602 __SHIFTIN(0, DC_WINC_A_POSITION_V) | 603 __SHIFTIN(0, DC_WINC_A_POSITION_H)); 604 DC_WRITE(tegra_crtc, DC_WINC_A_SIZE_REG, 605 __SHIFTIN(mode->crtc_vdisplay, DC_WINC_A_SIZE_V) | 606 __SHIFTIN(mode->crtc_hdisplay, DC_WINC_A_SIZE_H)); 607 DC_WRITE(tegra_crtc, DC_WINC_A_PRESCALED_SIZE_REG, 608 __SHIFTIN(mode->crtc_vdisplay, DC_WINC_A_PRESCALED_SIZE_V) | 609 __SHIFTIN(mode->crtc_hdisplay * (TEGRA_DC_DEPTH / 8), 610 DC_WINC_A_PRESCALED_SIZE_H)); 611 DC_WRITE(tegra_crtc, DC_WINC_A_LINE_STRIDE_REG, 612 __SHIFTIN(mode->crtc_hdisplay * (TEGRA_DC_DEPTH / 8), 613 DC_WINC_A_LINE_STRIDE_LINE_STRIDE)); 614 615 tegra_crtc_do_set_base(crtc, old_fb, x, y, 0); 616 617 /* Enable window A */ 618 DC_WRITE(tegra_crtc, DC_WINC_A_WIN_OPTIONS_REG, 619 DC_WINC_A_WIN_OPTIONS_WIN_ENABLE); 620 621 /* Timing and signal options */ 622 DC_WRITE(tegra_crtc, DC_DISP_DISP_TIMING_OPTIONS_REG, 623 __SHIFTIN(1, DC_DISP_DISP_TIMING_OPTIONS_VSYNC_POS)); 624 DC_WRITE(tegra_crtc, DC_DISP_DISP_COLOR_CONTROL_REG, 625 __SHIFTIN(DC_DISP_DISP_COLOR_CONTROL_BASE_COLOR_SIZE_888, 626 DC_DISP_DISP_COLOR_CONTROL_BASE_COLOR_SIZE)); 627 DC_WRITE(tegra_crtc, DC_DISP_DISP_SIGNAL_OPTIONS0_REG, 628 DC_DISP_DISP_SIGNAL_OPTIONS0_H_PULSE2_ENABLE); 629 DC_WRITE(tegra_crtc, DC_DISP_H_PULSE2_CONTROL_REG, 630 __SHIFTIN(DC_DISP_H_PULSE2_CONTROL_V_QUAL_VACTIVE, 631 DC_DISP_H_PULSE2_CONTROL_V_QUAL) | 632 __SHIFTIN(DC_DISP_H_PULSE2_CONTROL_LAST_END_A, 633 DC_DISP_H_PULSE2_CONTROL_LAST)); 634 635 const u_int pulse_start = 1 + hspw + hbp - 10; 636 DC_WRITE(tegra_crtc, DC_DISP_H_PULSE2_POSITION_A_REG, 637 __SHIFTIN(pulse_start, DC_DISP_H_PULSE2_POSITION_A_START) | 638 __SHIFTIN(pulse_start + 8, DC_DISP_H_PULSE2_POSITION_A_END)); 639 640 /* Pixel clock */ 641 const u_int parent_rate = clk_get_rate(tegra_crtc->clk_parent); 642 const u_int div = (parent_rate * 2) / (mode->crtc_clock * 1000) - 2; 643 DC_WRITE(tegra_crtc, DC_DISP_DISP_CLOCK_CONTROL_REG, 644 __SHIFTIN(0, DC_DISP_DISP_CLOCK_CONTROL_PIXEL_CLK_DIVIDER) | 645 __SHIFTIN(div, DC_DISP_DISP_CLOCK_CONTROL_SHIFT_CLK_DIVIDER)); 646 647 /* Mode timings */ 648 DC_WRITE(tegra_crtc, DC_DISP_REF_TO_SYNC_REG, 649 __SHIFTIN(1, DC_DISP_REF_TO_SYNC_V) | 650 __SHIFTIN(1, DC_DISP_REF_TO_SYNC_H)); 651 DC_WRITE(tegra_crtc, DC_DISP_SYNC_WIDTH_REG, 652 __SHIFTIN(vspw, DC_DISP_SYNC_WIDTH_V) | 653 __SHIFTIN(hspw, DC_DISP_SYNC_WIDTH_H)); 654 DC_WRITE(tegra_crtc, DC_DISP_BACK_PORCH_REG, 655 __SHIFTIN(vbp, DC_DISP_BACK_PORCH_V) | 656 __SHIFTIN(hbp, DC_DISP_BACK_PORCH_H)); 657 DC_WRITE(tegra_crtc, DC_DISP_FRONT_PORCH_REG, 658 __SHIFTIN(vfp, DC_DISP_FRONT_PORCH_V) | 659 __SHIFTIN(hfp, DC_DISP_FRONT_PORCH_H)); 660 DC_WRITE(tegra_crtc, DC_DISP_DISP_ACTIVE_REG, 661 __SHIFTIN(mode->crtc_vdisplay, DC_DISP_DISP_ACTIVE_V) | 662 __SHIFTIN(mode->crtc_hdisplay, DC_DISP_DISP_ACTIVE_H)); 663 664 return 0; 665 } 666 667 static int 668 tegra_crtc_do_set_base(struct drm_crtc *crtc, struct drm_framebuffer *fb, 669 int x, int y, int atomic) 670 { 671 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 672 struct tegra_framebuffer *tegra_fb = atomic ? 673 to_tegra_framebuffer(fb) : 674 to_tegra_framebuffer(crtc->primary->fb); 675 676 uint64_t paddr = (uint64_t)tegra_fb->obj->dmamap->dm_segs[0].ds_addr; 677 678 /* Framebuffer start address */ 679 DC_WRITE(tegra_crtc, DC_WINBUF_A_START_ADDR_HI_REG, (paddr >> 32) & 3); 680 DC_WRITE(tegra_crtc, DC_WINBUF_A_START_ADDR_REG, paddr & 0xffffffff); 681 682 /* Offsets */ 683 DC_WRITE(tegra_crtc, DC_WINBUF_A_ADDR_H_OFFSET_REG, x); 684 DC_WRITE(tegra_crtc, DC_WINBUF_A_ADDR_V_OFFSET_REG, y); 685 686 /* Surface kind */ 687 DC_WRITE(tegra_crtc, DC_WINBUF_A_SURFACE_KIND_REG, 688 __SHIFTIN(DC_WINBUF_A_SURFACE_KIND_SURFACE_KIND_PITCH, 689 DC_WINBUF_A_SURFACE_KIND_SURFACE_KIND)); 690 691 return 0; 692 } 693 694 static int 695 tegra_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 696 struct drm_framebuffer *old_fb) 697 { 698 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 699 700 tegra_crtc_do_set_base(crtc, old_fb, x, y, 0); 701 702 /* Commit settings */ 703 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 704 DC_CMD_STATE_CONTROL_WIN_A_UPDATE); 705 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 706 DC_CMD_STATE_CONTROL_WIN_A_ACT_REQ); 707 708 return 0; 709 } 710 711 static int 712 tegra_crtc_mode_set_base_atomic(struct drm_crtc *crtc, 713 struct drm_framebuffer *fb, int x, int y, enum mode_set_atomic state) 714 { 715 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 716 717 tegra_crtc_do_set_base(crtc, fb, x, y, 1); 718 719 /* Commit settings */ 720 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 721 DC_CMD_STATE_CONTROL_WIN_A_UPDATE); 722 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 723 DC_CMD_STATE_CONTROL_WIN_A_ACT_REQ); 724 725 return 0; 726 } 727 728 static void 729 tegra_crtc_disable(struct drm_crtc *crtc) 730 { 731 } 732 733 static void 734 tegra_crtc_prepare(struct drm_crtc *crtc) 735 { 736 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 737 738 /* Access control */ 739 DC_WRITE(tegra_crtc, DC_CMD_STATE_ACCESS_REG, 0); 740 741 /* Enable window A programming */ 742 DC_WRITE(tegra_crtc, DC_CMD_DISPLAY_WINDOW_HEADER_REG, 743 DC_CMD_DISPLAY_WINDOW_HEADER_WINDOW_A_SELECT); 744 } 745 746 static void 747 tegra_crtc_commit(struct drm_crtc *crtc) 748 { 749 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 750 751 /* Enable continuous display mode */ 752 DC_WRITE(tegra_crtc, DC_CMD_DISPLAY_COMMAND_REG, 753 __SHIFTIN(DC_CMD_DISPLAY_COMMAND_DISPLAY_CTRL_MODE_C_DISPLAY, 754 DC_CMD_DISPLAY_COMMAND_DISPLAY_CTRL_MODE)); 755 756 /* Enable power */ 757 DC_SET_CLEAR(tegra_crtc, DC_CMD_DISPLAY_POWER_CONTROL_REG, 758 DC_CMD_DISPLAY_POWER_CONTROL_PM1_ENABLE | 759 DC_CMD_DISPLAY_POWER_CONTROL_PM0_ENABLE | 760 DC_CMD_DISPLAY_POWER_CONTROL_PW4_ENABLE | 761 DC_CMD_DISPLAY_POWER_CONTROL_PW3_ENABLE | 762 DC_CMD_DISPLAY_POWER_CONTROL_PW2_ENABLE | 763 DC_CMD_DISPLAY_POWER_CONTROL_PW1_ENABLE | 764 DC_CMD_DISPLAY_POWER_CONTROL_PW0_ENABLE, 765 0); 766 767 /* Commit settings */ 768 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 769 DC_CMD_STATE_CONTROL_GENERAL_UPDATE | 770 DC_CMD_STATE_CONTROL_WIN_A_UPDATE); 771 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 772 DC_CMD_STATE_CONTROL_GENERAL_ACT_REQ | 773 DC_CMD_STATE_CONTROL_WIN_A_ACT_REQ); 774 775 tegra_crtc->enabled = true; 776 } 777 778 static int 779 tegra_encoder_init(struct drm_device *ddev) 780 { 781 struct tegra_drm_softc * const sc = tegra_drm_private(ddev); 782 struct tegra_encoder *encoder; 783 int error; 784 785 if (sc->sc_clk_hdmi == NULL || 786 sc->sc_clk_hdmi_parent == NULL || 787 sc->sc_rst_hdmi == NULL) { 788 DRM_ERROR("no clocks configured for hdmi\n"); 789 DRM_ERROR("clk: hdmi %p parent %p\n", sc->sc_clk_hdmi, sc->sc_clk_hdmi_parent); 790 DRM_ERROR("rst: hdmi %p\n", sc->sc_rst_hdmi); 791 return -EIO; 792 } 793 794 const bus_addr_t offset = TEGRA_GHOST_BASE + TEGRA_HDMI_OFFSET; 795 const bus_size_t size = TEGRA_HDMI_SIZE; 796 797 encoder = kmem_zalloc(sizeof(*encoder), KM_SLEEP); 798 encoder->bst = sc->sc_bst; 799 error = bus_space_map(encoder->bst, offset, size, 0, &encoder->bsh); 800 if (error) { 801 kmem_free(encoder, sizeof(*encoder)); 802 return -error; 803 } 804 encoder->size = size; 805 806 tegra_pmc_hdmi_enable(); 807 808 /* Enable parent PLL */ 809 error = clk_set_rate(sc->sc_clk_hdmi_parent, 594000000); 810 if (error) { 811 DRM_ERROR("couldn't set hdmi parent PLL rate: %d\n", error); 812 return -error; 813 } 814 error = clk_enable(sc->sc_clk_hdmi_parent); 815 if (error) { 816 DRM_ERROR("couldn't enable hdmi parent PLL: %d\n", error); 817 return -error; 818 } 819 820 drm_encoder_init(ddev, &encoder->base, &tegra_encoder_funcs, 821 DRM_MODE_ENCODER_TMDS); 822 drm_encoder_helper_add(&encoder->base, &tegra_encoder_helper_funcs); 823 824 encoder->base.possible_crtcs = (1 << 0) | (1 << 1); 825 826 return tegra_connector_init(ddev, &encoder->base); 827 } 828 829 static void 830 tegra_encoder_destroy(struct drm_encoder *encoder) 831 { 832 struct tegra_encoder *tegra_encoder = to_tegra_encoder(encoder); 833 drm_encoder_cleanup(encoder); 834 kmem_free(tegra_encoder, sizeof(*tegra_encoder)); 835 } 836 837 static void 838 tegra_encoder_dpms(struct drm_encoder *encoder, int mode) 839 { 840 struct tegra_encoder *tegra_encoder = to_tegra_encoder(encoder); 841 842 if (encoder->crtc == NULL) 843 return; 844 845 switch (mode) { 846 case DRM_MODE_DPMS_ON: 847 case DRM_MODE_DPMS_STANDBY: 848 case DRM_MODE_DPMS_SUSPEND: 849 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_BLANK_REG, 850 0, HDMI_NV_PDISP_SOR_BLANK_OVERRIDE); 851 break; 852 case DRM_MODE_DPMS_OFF: 853 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_BLANK_REG, 854 HDMI_NV_PDISP_SOR_BLANK_OVERRIDE, 0); 855 break; 856 } 857 } 858 859 static bool 860 tegra_encoder_mode_fixup(struct drm_encoder *encoder, 861 const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) 862 { 863 return true; 864 } 865 866 static int 867 tegra_encoder_hdmi_set_clock(struct drm_encoder *encoder, u_int rate) 868 { 869 struct drm_device *ddev = encoder->dev; 870 struct tegra_drm_softc * const sc = tegra_drm_private(ddev); 871 int error; 872 873 /* Enter reset */ 874 fdtbus_reset_assert(sc->sc_rst_hdmi); 875 876 /* Set HDMI parent clock */ 877 error = clk_set_parent(sc->sc_clk_hdmi, sc->sc_clk_hdmi_parent); 878 if (error) { 879 DRM_ERROR("couldn't set hdmi parent: %d\n", error); 880 return -error; 881 } 882 883 /* Set dot clock frequency */ 884 error = clk_set_rate(sc->sc_clk_hdmi, rate); 885 if (error) { 886 DRM_ERROR("couldn't set hdmi clock: %d\n", error); 887 return -error; 888 } 889 error = clk_enable(sc->sc_clk_hdmi); 890 if (error) { 891 DRM_ERROR("couldn't enable hdmi clock: %d\n", error); 892 return -error; 893 } 894 895 /* Leave reset */ 896 fdtbus_reset_deassert(sc->sc_rst_hdmi); 897 898 return 0; 899 } 900 901 static void 902 tegra_encoder_mode_set(struct drm_encoder *encoder, 903 struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) 904 { 905 struct drm_device *ddev = encoder->dev; 906 struct tegra_encoder *tegra_encoder = to_tegra_encoder(encoder); 907 struct tegra_crtc *tegra_crtc = to_tegra_crtc(encoder->crtc); 908 struct tegra_connector *tegra_connector = NULL; 909 struct drm_connector *connector; 910 const struct tegra_hdmi_tmds_config *tmds = NULL; 911 uint32_t input_ctrl; 912 int retry; 913 u_int i; 914 915 tegra_encoder_hdmi_set_clock(encoder, mode->crtc_clock * 1000); 916 917 /* find the connector for this encoder */ 918 list_for_each_entry(connector, &ddev->mode_config.connector_list, head) { 919 if (connector->encoder == encoder) { 920 tegra_connector = to_tegra_connector(connector); 921 break; 922 } 923 } 924 925 for (i = 0; i < __arraycount(tegra_hdmi_tmds_config); i++) { 926 if (tegra_hdmi_tmds_config[i].dot_clock >= mode->crtc_clock) { 927 break; 928 } 929 } 930 if (i < __arraycount(tegra_hdmi_tmds_config)) { 931 tmds = &tegra_hdmi_tmds_config[i]; 932 } else { 933 tmds = &tegra_hdmi_tmds_config[__arraycount(tegra_hdmi_tmds_config) - 1]; 934 } 935 936 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PLL0_REG, tmds->sor_pll0); 937 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PLL1_REG, tmds->sor_pll1); 938 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT_REG, 939 tmds->sor_lane_drive_current); 940 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_PE_CURRENT_REG, 941 tmds->pe_current); 942 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT_REG, 943 tmds->sor_io_peak_current); 944 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PAD_CTLS0_REG, 945 tmds->sor_pad_ctls0); 946 947 const u_int div = (mode->crtc_clock / 1000) * 4; 948 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_REFCLK_REG, 949 __SHIFTIN(div >> 2, HDMI_NV_PDISP_SOR_REFCLK_DIV_INT) | 950 __SHIFTIN(div & 3, HDMI_NV_PDISP_SOR_REFCLK_DIV_FRAC)); 951 952 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_CSTM_REG, 953 __SHIFTIN(HDMI_NV_PDISP_SOR_CSTM_MODE_TMDS, 954 HDMI_NV_PDISP_SOR_CSTM_MODE) | 955 __SHIFTIN(2, HDMI_NV_PDISP_SOR_CSTM_ROTCLK) | 956 HDMI_NV_PDISP_SOR_CSTM_PLLDIV, 957 HDMI_NV_PDISP_SOR_CSTM_MODE | 958 HDMI_NV_PDISP_SOR_CSTM_ROTCLK | 959 HDMI_NV_PDISP_SOR_CSTM_LVDS_EN); 960 961 const uint32_t inst = 962 HDMI_NV_PDISP_SOR_SEQ_INST_DRIVE_PWM_OUT_LO | 963 HDMI_NV_PDISP_SOR_SEQ_INST_HALT | 964 __SHIFTIN(2, HDMI_NV_PDISP_SOR_SEQ_INST_WAIT_UNITS) | 965 __SHIFTIN(1, HDMI_NV_PDISP_SOR_SEQ_INST_WAIT_TIME); 966 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_SEQ_INST0_REG, inst); 967 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_SEQ_INST8_REG, inst); 968 969 input_ctrl = __SHIFTIN(tegra_crtc->index, 970 HDMI_NV_PDISP_INPUT_CONTROL_HDMI_SRC_SELECT); 971 if (mode->crtc_hdisplay != 640 || mode->crtc_vdisplay != 480) 972 input_ctrl |= HDMI_NV_PDISP_INPUT_CONTROL_ARM_VIDEO_RANGE; 973 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_INPUT_CONTROL_REG, input_ctrl); 974 975 /* Start SOR */ 976 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_PLL0_REG, 977 0, 978 HDMI_NV_PDISP_SOR_PLL0_PWR | 979 HDMI_NV_PDISP_SOR_PLL0_VCOPD | 980 HDMI_NV_PDISP_SOR_PLL0_PULLDOWN); 981 delay(10); 982 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_PLL0_REG, 983 0, 984 HDMI_NV_PDISP_SOR_PLL0_PDBG); 985 986 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PWR_REG, 987 HDMI_NV_PDISP_SOR_PWR_NORMAL_STATE | 988 HDMI_NV_PDISP_SOR_PWR_SETTING_NEW); 989 990 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PWR_REG, 991 HDMI_NV_PDISP_SOR_PWR_NORMAL_STATE); 992 993 for (retry = 10000; retry > 0; retry--) { 994 const uint32_t pwr = HDMI_READ(tegra_encoder, 995 HDMI_NV_PDISP_SOR_PWR_REG); 996 if ((pwr & HDMI_NV_PDISP_SOR_PWR_SETTING_NEW) == 0) 997 break; 998 delay(10); 999 } 1000 if (retry == 0) { 1001 DRM_ERROR("timeout enabling SOR power\n"); 1002 } 1003 1004 uint32_t state2 = 1005 __SHIFTIN(1, HDMI_NV_PDISP_SOR_STATE2_ASY_OWNER) | 1006 __SHIFTIN(3, HDMI_NV_PDISP_SOR_STATE2_ASY_SUBOWNER) | 1007 __SHIFTIN(1, HDMI_NV_PDISP_SOR_STATE2_ASY_CRCMODE) | 1008 __SHIFTIN(1, HDMI_NV_PDISP_SOR_STATE2_ASY_PROTOCOL); 1009 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 1010 state2 |= HDMI_NV_PDISP_SOR_STATE2_ASY_HSYNCPOL; 1011 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 1012 state2 |= HDMI_NV_PDISP_SOR_STATE2_ASY_VSYNCPOL; 1013 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_STATE2_REG, state2); 1014 1015 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_STATE1_REG, 1016 __SHIFTIN(HDMI_NV_PDISP_SOR_STATE1_ASY_HEAD_OPMODE_AWAKE, 1017 HDMI_NV_PDISP_SOR_STATE1_ASY_HEAD_OPMODE) | 1018 HDMI_NV_PDISP_SOR_STATE1_ASY_ORMODE); 1019 1020 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_STATE0_REG, 0); 1021 1022 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_STATE0_REG, 1023 HDMI_NV_PDISP_SOR_STATE0_UPDATE); 1024 1025 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_STATE1_REG, 1026 HDMI_NV_PDISP_SOR_STATE1_ATTACHED, 0); 1027 1028 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_STATE0_REG, 0); 1029 1030 const u_int rekey = 56; 1031 const u_int hspw = mode->hsync_end - mode->hsync_start; 1032 const u_int hbp = mode->htotal - mode->hsync_end; 1033 const u_int hfp = mode->hsync_start - mode->hdisplay; 1034 const u_int max_ac_packet = (hspw + hbp + hfp - rekey - 18) / 32; 1035 uint32_t ctrl = 1036 __SHIFTIN(rekey, HDMI_NV_PDISP_HDMI_CTRL_REKEY) | 1037 __SHIFTIN(max_ac_packet, HDMI_NV_PDISP_HDMI_CTRL_MAX_AC_PACKET); 1038 if (tegra_connector && tegra_connector->has_hdmi_sink) { 1039 ctrl |= HDMI_NV_PDISP_HDMI_CTRL_ENABLE; /* HDMI ENABLE */ 1040 } 1041 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_HDMI_CTRL_REG, ctrl); 1042 1043 if (tegra_connector && tegra_connector->has_hdmi_sink && 1044 tegra_connector->has_audio) { 1045 struct hdmi_audio_infoframe ai; 1046 struct hdmi_avi_infoframe avii; 1047 uint8_t aibuf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE]; 1048 uint8_t aviibuf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 1049 const u_int n = 6144; /* 48 kHz */ 1050 const u_int cts = ((mode->crtc_clock * 10) * (n / 128)) / 480; 1051 1052 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_REG, 1053 __SHIFTIN(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO, 1054 HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SOURCE_SELECT) | 1055 HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_INJECT_NULLSMPL); 1056 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_AUDIO_N_REG, 1057 HDMI_NV_PDISP_AUDIO_N_RESETF | 1058 HDMI_NV_PDISP_AUDIO_N_GENERATE | 1059 __SHIFTIN(n - 1, HDMI_NV_PDISP_AUDIO_N_VALUE)); 1060 1061 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_HDMI_SPARE_REG, 1062 HDMI_NV_PDISP_HDMI_SPARE_HW_CTS | 1063 HDMI_NV_PDISP_HDMI_SPARE_FORCE_SW_CTS | 1064 __SHIFTIN(1, HDMI_NV_PDISP_HDMI_SPARE_CTS_RESET_VAL)); 1065 1066 /* 1067 * When HW_CTS=1 and FORCE_SW_CTS=1, the CTS is programmed by 1068 * software in the 44.1 kHz register regardless of chosen rate. 1069 */ 1070 HDMI_WRITE(tegra_encoder, 1071 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW_REG, 1072 cts << 8); 1073 HDMI_WRITE(tegra_encoder, 1074 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH_REG, 1075 0x80000000 | n); 1076 1077 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_AUDIO_N_REG, 0, 1078 HDMI_NV_PDISP_AUDIO_N_RESETF); 1079 1080 HDMI_WRITE(tegra_encoder, 1081 HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480_REG, 24000); 1082 1083 hdmi_audio_infoframe_init(&ai); 1084 ai.channels = 2; 1085 hdmi_audio_infoframe_pack(&ai, aibuf, sizeof(aibuf)); 1086 HDMI_WRITE(tegra_encoder, 1087 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER_REG, 1088 aibuf[0] | (aibuf[1] << 8) | (aibuf[2] << 16)); 1089 HDMI_WRITE(tegra_encoder, 1090 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_REG, 1091 aibuf[3] | (aibuf[4] << 8) | 1092 (aibuf[5] << 16) | (aibuf[6] << 24)); 1093 HDMI_WRITE(tegra_encoder, 1094 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_REG, 1095 aibuf[7] | (aibuf[8] << 8) | (aibuf[9] << 16)); 1096 1097 hdmi_avi_infoframe_init(&avii); 1098 drm_hdmi_avi_infoframe_from_display_mode(&avii, mode); 1099 hdmi_avi_infoframe_pack(&avii, aviibuf, sizeof(aviibuf)); 1100 HDMI_WRITE(tegra_encoder, 1101 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER_REG, 1102 aviibuf[0] | (aviibuf[1] << 8) | (aviibuf[2] << 16)); 1103 HDMI_WRITE(tegra_encoder, 1104 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_REG, 1105 aviibuf[3] | (aviibuf[4] << 8) | 1106 (aviibuf[5] << 16) | (aviibuf[6] << 24)); 1107 HDMI_WRITE(tegra_encoder, 1108 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_REG, 1109 aviibuf[7] | (aviibuf[8] << 8) | (aviibuf[9] << 16)); 1110 HDMI_WRITE(tegra_encoder, 1111 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_REG, 1112 aviibuf[10] | (aviibuf[11] << 8) | 1113 (aviibuf[12] << 16) | (aviibuf[13] << 24)); 1114 HDMI_WRITE(tegra_encoder, 1115 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_REG, 1116 aviibuf[14] | (aviibuf[15] << 8) | (aviibuf[16] << 16)); 1117 1118 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_HDMI_GENERIC_CTRL_REG, 1119 HDMI_NV_PDISP_HDMI_GENERIC_CTRL_AUDIO); 1120 HDMI_WRITE(tegra_encoder, 1121 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_REG, 1122 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_ENABLE); 1123 HDMI_WRITE(tegra_encoder, 1124 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_REG, 1125 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_ENABLE); 1126 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_HDMI_ACR_CTRL_REG, 0); 1127 } else { 1128 HDMI_WRITE(tegra_encoder, 1129 HDMI_NV_PDISP_HDMI_GENERIC_CTRL_REG, 0); 1130 HDMI_WRITE(tegra_encoder, 1131 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_REG, 0); 1132 HDMI_WRITE(tegra_encoder, 1133 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_REG, 0); 1134 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_HDMI_ACR_CTRL_REG, 0); 1135 } 1136 1137 /* Enable DC output to HDMI */ 1138 DC_SET_CLEAR(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG, 1139 DC_DISP_DISP_WIN_OPTIONS_HDMI_ENABLE, 0); 1140 1141 /* Commit settings */ 1142 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 1143 DC_CMD_STATE_CONTROL_GENERAL_UPDATE | 1144 DC_CMD_STATE_CONTROL_WIN_A_UPDATE); 1145 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 1146 DC_CMD_STATE_CONTROL_GENERAL_ACT_REQ | 1147 DC_CMD_STATE_CONTROL_WIN_A_ACT_REQ); 1148 } 1149 1150 static void 1151 tegra_encoder_prepare(struct drm_encoder *encoder) 1152 { 1153 } 1154 1155 static void 1156 tegra_encoder_commit(struct drm_encoder *encoder) 1157 { 1158 } 1159 1160 static int 1161 tegra_connector_init(struct drm_device *ddev, struct drm_encoder *encoder) 1162 { 1163 struct tegra_drm_softc * const sc = tegra_drm_private(ddev); 1164 struct tegra_connector *connector; 1165 1166 connector = kmem_zalloc(sizeof(*connector), KM_SLEEP); 1167 1168 drm_connector_init(ddev, &connector->base, &tegra_connector_funcs, 1169 DRM_MODE_CONNECTOR_HDMIA); 1170 drm_connector_helper_add(&connector->base, 1171 &tegra_connector_helper_funcs); 1172 1173 connector->base.interlace_allowed = 0; 1174 connector->base.doublescan_allowed = 0; 1175 1176 drm_sysfs_connector_add(&connector->base); 1177 1178 connector->base.polled = 1179 DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 1180 1181 drm_mode_connector_attach_encoder(&connector->base, encoder); 1182 1183 connector->hpd = sc->sc_pin_hpd; 1184 if (!connector->hpd) 1185 DRM_ERROR("failed to find hpd pin for connector\n"); 1186 1187 connector->ddc = sc->sc_ddc; 1188 if (!connector->ddc) 1189 DRM_ERROR("failed to find ddc device for connector\n"); 1190 1191 return 0; 1192 } 1193 1194 static void 1195 tegra_connector_destroy(struct drm_connector *connector) 1196 { 1197 struct tegra_connector *tegra_connector = to_tegra_connector(connector); 1198 1199 drm_sysfs_connector_remove(connector); 1200 drm_connector_cleanup(connector); 1201 kmem_free(tegra_connector, sizeof(*tegra_connector)); 1202 } 1203 1204 static enum drm_connector_status 1205 tegra_connector_detect(struct drm_connector *connector, bool force) 1206 { 1207 struct tegra_connector *tegra_connector = to_tegra_connector(connector); 1208 bool con; 1209 1210 1211 if (!tegra_connector->hpd) { 1212 tegra_connector->has_hdmi_sink = false; 1213 tegra_connector->has_audio = false; 1214 return connector_status_connected; 1215 } 1216 1217 con = fdtbus_gpio_read(tegra_connector->hpd); 1218 if (con) { 1219 return connector_status_connected; 1220 } else { 1221 prop_dictionary_t prop = device_properties(connector->dev->dev); 1222 prop_dictionary_remove(prop, "physical-address"); 1223 tegra_connector->has_hdmi_sink = false; 1224 tegra_connector->has_audio = false; 1225 return connector_status_disconnected; 1226 } 1227 } 1228 1229 static int 1230 tegra_connector_mode_valid(struct drm_connector *connector, 1231 struct drm_display_mode *mode) 1232 { 1233 return MODE_OK; 1234 } 1235 1236 static int 1237 tegra_connector_get_modes(struct drm_connector *connector) 1238 { 1239 struct tegra_connector *tegra_connector = to_tegra_connector(connector); 1240 struct tegra_drm_softc * const sc = tegra_drm_private(connector->dev); 1241 prop_dictionary_t prop = device_properties(connector->dev->dev); 1242 char edid[EDID_LENGTH * 4]; 1243 struct edid *pedid = NULL; 1244 int error, block; 1245 1246 if (tegra_connector->ddc) { 1247 memset(edid, 0, sizeof(edid)); 1248 for (block = 0; block < 4; block++) { 1249 error = ddc_read_edid_block(tegra_connector->ddc, 1250 &edid[block * EDID_LENGTH], EDID_LENGTH, block); 1251 if (error) 1252 break; 1253 if (block == 0) { 1254 pedid = (struct edid *)edid; 1255 if (edid[0x7e] == 0) 1256 break; 1257 } 1258 } 1259 } 1260 1261 if (pedid) { 1262 if (sc->sc_force_dvi) { 1263 tegra_connector->has_hdmi_sink = false; 1264 tegra_connector->has_audio = false; 1265 } else { 1266 tegra_connector->has_hdmi_sink = 1267 drm_detect_hdmi_monitor(pedid); 1268 tegra_connector->has_audio = 1269 drm_detect_monitor_audio(pedid); 1270 } 1271 drm_mode_connector_update_edid_property(connector, pedid); 1272 error = drm_add_edid_modes(connector, pedid); 1273 drm_edid_to_eld(connector, pedid); 1274 if (drm_detect_hdmi_monitor(pedid)) { 1275 prop_dictionary_set_uint16(prop, "physical-address", 1276 connector->physical_address); 1277 } 1278 return error; 1279 } else { 1280 drm_mode_connector_update_edid_property(connector, NULL); 1281 return 0; 1282 } 1283 } 1284 1285 static struct drm_encoder * 1286 tegra_connector_best_encoder(struct drm_connector *connector) 1287 { 1288 int enc_id = connector->encoder_ids[0]; 1289 struct drm_mode_object *obj; 1290 struct drm_encoder *encoder = NULL; 1291 1292 if (enc_id) { 1293 obj = drm_mode_object_find(connector->dev, enc_id, 1294 DRM_MODE_OBJECT_ENCODER); 1295 if (obj == NULL) 1296 return NULL; 1297 encoder = obj_to_encoder(obj); 1298 } 1299 1300 return encoder; 1301 } 1302 1303 static int 1304 tegra_crtc_intr(void *priv) 1305 { 1306 struct tegra_crtc *tegra_crtc = priv; 1307 struct drm_device *ddev = tegra_crtc->base.dev; 1308 struct tegra_drm_softc * const sc = tegra_drm_private(ddev); 1309 int rv = 0; 1310 1311 const uint32_t status = DC_READ(tegra_crtc, DC_CMD_INT_STATUS_REG); 1312 1313 if (status & DC_CMD_INT_V_BLANK) { 1314 DC_WRITE(tegra_crtc, DC_CMD_INT_STATUS_REG, DC_CMD_INT_V_BLANK); 1315 atomic_inc_32(&sc->sc_vbl_received[tegra_crtc->index]); 1316 drm_handle_vblank(ddev, tegra_crtc->index); 1317 rv = 1; 1318 } 1319 1320 return rv; 1321 } 1322 1323 u32 1324 tegra_drm_get_vblank_counter(struct drm_device *ddev, int crtc) 1325 { 1326 struct tegra_drm_softc * const sc = tegra_drm_private(ddev); 1327 1328 if (crtc > 1) 1329 return 0; 1330 1331 return sc->sc_vbl_received[crtc]; 1332 } 1333 1334 int 1335 tegra_drm_enable_vblank(struct drm_device *ddev, int crtc) 1336 { 1337 struct tegra_crtc *tegra_crtc = NULL; 1338 struct drm_crtc *iter; 1339 1340 list_for_each_entry(iter, &ddev->mode_config.crtc_list, head) { 1341 if (to_tegra_crtc(iter)->index == crtc) { 1342 tegra_crtc = to_tegra_crtc(iter); 1343 break; 1344 } 1345 } 1346 if (tegra_crtc == NULL) 1347 return -EINVAL; 1348 1349 DC_SET_CLEAR(tegra_crtc, DC_CMD_INT_MASK_REG, DC_CMD_INT_V_BLANK, 0); 1350 1351 return 0; 1352 } 1353 1354 void 1355 tegra_drm_disable_vblank(struct drm_device *ddev, int crtc) 1356 { 1357 struct tegra_crtc *tegra_crtc = NULL; 1358 struct drm_crtc *iter; 1359 1360 list_for_each_entry(iter, &ddev->mode_config.crtc_list, head) { 1361 if (to_tegra_crtc(iter)->index == crtc) { 1362 tegra_crtc = to_tegra_crtc(iter); 1363 break; 1364 } 1365 } 1366 if (tegra_crtc == NULL) 1367 return; 1368 1369 DC_SET_CLEAR(tegra_crtc, DC_CMD_INT_MASK_REG, 0, DC_CMD_INT_V_BLANK); 1370 DC_WRITE(tegra_crtc, DC_CMD_INT_STATUS_REG, DC_CMD_INT_V_BLANK); 1371 } 1372
Indexes created Fri Oct 17 00:09:41 GMT 2025