tegra_drm_mode.c revision 1.19.8.1
1 /* $NetBSD: tegra_drm_mode.c,v 1.19.8.1 2021/04/03 22:28:17 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_drm_mode.c,v 1.19.8.1 2021/04/03 22:28:17 thorpej Exp $"); 31 32 #include <drm/drmP.h> 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_crtc_helper.h> 35 #include <drm/drm_edid.h> 36 #include <drm/drm_plane_helper.h> 37 38 #include <dev/i2c/ddcvar.h> 39 40 #include <arm/nvidia/tegra_reg.h> 41 #include <arm/nvidia/tegra_var.h> 42 #include <arm/nvidia/tegra_intr.h> 43 #include <arm/nvidia/tegra_pmcreg.h> 44 #include <arm/nvidia/tegra_dcreg.h> 45 #include <arm/nvidia/tegra_hdmireg.h> 46 #include <arm/nvidia/tegra_drm.h> 47 48 #include <dev/fdt/fdtvar.h> 49 50 #include <external/bsd/drm2/dist/drm/drm_internal.h> 51 52 static struct drm_framebuffer *tegra_fb_create(struct drm_device *, 53 struct drm_file *, struct drm_mode_fb_cmd2 *); 54 55 static const struct drm_mode_config_funcs tegra_mode_config_funcs = { 56 .fb_create = tegra_fb_create 57 }; 58 59 static int tegra_framebuffer_create_handle(struct drm_framebuffer *, 60 struct drm_file *, unsigned int *); 61 static void tegra_framebuffer_destroy(struct drm_framebuffer *); 62 63 static const struct drm_framebuffer_funcs tegra_framebuffer_funcs = { 64 .create_handle = tegra_framebuffer_create_handle, 65 .destroy = tegra_framebuffer_destroy 66 }; 67 68 static int tegra_crtc_init(struct drm_device *, int); 69 static void tegra_crtc_destroy(struct drm_crtc *); 70 static int tegra_crtc_cursor_set(struct drm_crtc *, struct drm_file *, 71 uint32_t, uint32_t, uint32_t); 72 static int tegra_crtc_cursor_move(struct drm_crtc *, int, int); 73 static int tegra_crtc_intr(void *); 74 75 static const struct drm_crtc_funcs tegra_crtc_funcs = { 76 .cursor_set = tegra_crtc_cursor_set, 77 .cursor_move = tegra_crtc_cursor_move, 78 .set_config = drm_crtc_helper_set_config, 79 .destroy = tegra_crtc_destroy 80 }; 81 82 static void tegra_crtc_dpms(struct drm_crtc *, int); 83 static bool tegra_crtc_mode_fixup(struct drm_crtc *, 84 const struct drm_display_mode *, 85 struct drm_display_mode *); 86 static int tegra_crtc_mode_set(struct drm_crtc *, 87 struct drm_display_mode *, struct drm_display_mode *, 88 int, int, struct drm_framebuffer *); 89 static int tegra_crtc_mode_set_base(struct drm_crtc *, 90 int, int, struct drm_framebuffer *); 91 static int tegra_crtc_mode_set_base_atomic(struct drm_crtc *, 92 struct drm_framebuffer *, int, int, enum mode_set_atomic); 93 static void tegra_crtc_disable(struct drm_crtc *); 94 static void tegra_crtc_prepare(struct drm_crtc *); 95 static void tegra_crtc_commit(struct drm_crtc *); 96 97 static int tegra_crtc_do_set_base(struct drm_crtc *, 98 struct drm_framebuffer *, int, int, int); 99 100 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = { 101 .dpms = tegra_crtc_dpms, 102 .mode_fixup = tegra_crtc_mode_fixup, 103 .mode_set = tegra_crtc_mode_set, 104 .mode_set_base = tegra_crtc_mode_set_base, 105 .mode_set_base_atomic = tegra_crtc_mode_set_base_atomic, 106 .disable = tegra_crtc_disable, 107 .prepare = tegra_crtc_prepare, 108 .commit = tegra_crtc_commit 109 }; 110 111 static int tegra_encoder_init(struct drm_device *); 112 static void tegra_encoder_destroy(struct drm_encoder *); 113 114 static const struct drm_encoder_funcs tegra_encoder_funcs = { 115 .destroy = tegra_encoder_destroy 116 }; 117 118 static void tegra_encoder_dpms(struct drm_encoder *, int); 119 static bool tegra_encoder_mode_fixup(struct drm_encoder *, 120 const struct drm_display_mode *, struct drm_display_mode *); 121 static void tegra_encoder_mode_set(struct drm_encoder *, 122 struct drm_display_mode *, struct drm_display_mode *); 123 static void tegra_encoder_prepare(struct drm_encoder *); 124 static void tegra_encoder_commit(struct drm_encoder *); 125 126 static const struct drm_encoder_helper_funcs tegra_encoder_helper_funcs = { 127 .dpms = tegra_encoder_dpms, 128 .mode_fixup = tegra_encoder_mode_fixup, 129 .prepare = tegra_encoder_prepare, 130 .commit = tegra_encoder_commit, 131 .mode_set = tegra_encoder_mode_set 132 }; 133 134 static int tegra_connector_init(struct drm_device *, struct drm_encoder *); 135 static void tegra_connector_destroy(struct drm_connector *); 136 static enum drm_connector_status tegra_connector_detect(struct drm_connector *, 137 bool); 138 139 static const struct drm_connector_funcs tegra_connector_funcs = { 140 .dpms = drm_helper_connector_dpms, 141 .detect = tegra_connector_detect, 142 .fill_modes = drm_helper_probe_single_connector_modes, 143 .destroy = tegra_connector_destroy 144 }; 145 146 static int tegra_connector_mode_valid(struct drm_connector *, 147 struct drm_display_mode *); 148 static int tegra_connector_get_modes(struct drm_connector *); 149 static struct drm_encoder *tegra_connector_best_encoder(struct drm_connector *); 150 151 static const struct drm_connector_helper_funcs tegra_connector_helper_funcs = { 152 .mode_valid = tegra_connector_mode_valid, 153 .get_modes = tegra_connector_get_modes, 154 .best_encoder = tegra_connector_best_encoder 155 }; 156 157 static const struct tegra_hdmi_tmds_config { 158 u_int dot_clock; 159 uint32_t sor_pll0; 160 uint32_t sor_pll1; 161 uint32_t sor_lane_drive_current; 162 uint32_t pe_current; 163 uint32_t sor_io_peak_current; 164 uint32_t sor_pad_ctls0; 165 uint32_t car_plld_misc; /* XXX unused? */ 166 } tegra_hdmi_tmds_config[] = { 167 /* 480p */ 168 { 27000, 0x01003010, 0x00301b00, 0x1f1f1f1f, 169 0x00000000, 0x03030303, 0x800034bb, 0x40400820 }, 170 /* 720p / 1080i */ 171 { 74250, 0x01003110, 0x00301500, 0x2c2c2c2c, 172 0x00000000, 0x07070707, 0x800034bb, 0x40400820 }, 173 /* 1080p */ 174 { 148500, 0x01003310, 0x00301500, 0x2d2d2d2d, 175 0x00000000, 0x05050505, 0x800034bb, 0x40400820 }, 176 /* 2160p */ 177 { 297000, 0x01003f10, 0x00300f00, 0x37373737, 178 0x00000000, 0x17171717, 0x800036bb, 0x40400f20 }, 179 }; 180 181 int 182 tegra_drm_mode_init(struct drm_device *ddev) 183 { 184 int error; 185 186 drm_mode_config_init(ddev); 187 ddev->mode_config.min_width = 0; 188 ddev->mode_config.min_height = 0; 189 ddev->mode_config.max_width = 4096; 190 ddev->mode_config.max_height = 2160; 191 ddev->mode_config.funcs = &tegra_mode_config_funcs; 192 193 error = tegra_crtc_init(ddev, 0); 194 if (error) 195 return error; 196 197 error = tegra_crtc_init(ddev, 1); 198 if (error) 199 return error; 200 201 error = tegra_encoder_init(ddev); 202 if (error) 203 return error; 204 205 error = drm_vblank_init(ddev, 2); 206 if (error) 207 return error; 208 209 return 0; 210 } 211 212 int 213 tegra_drm_framebuffer_init(struct drm_device *ddev, 214 struct tegra_framebuffer *fb) 215 { 216 return drm_framebuffer_init(ddev, &fb->base, &tegra_framebuffer_funcs); 217 } 218 219 static struct drm_framebuffer * 220 tegra_fb_create(struct drm_device *ddev, struct drm_file *file, 221 struct drm_mode_fb_cmd2 *cmd) 222 { 223 struct tegra_framebuffer *fb; 224 struct drm_gem_object *gem_obj; 225 int error; 226 227 if (cmd->flags) 228 return NULL; 229 if (cmd->pixel_format != DRM_FORMAT_ARGB8888 && 230 cmd->pixel_format != DRM_FORMAT_XRGB8888) { 231 return NULL; 232 } 233 234 gem_obj = drm_gem_object_lookup(ddev, file, cmd->handles[0]); 235 if (gem_obj == NULL) 236 return NULL; 237 238 fb = kmem_zalloc(sizeof(*fb), KM_SLEEP); 239 fb->obj = to_drm_gem_cma_obj(gem_obj); 240 fb->base.pitches[0] = cmd->pitches[0]; 241 fb->base.offsets[0] = cmd->offsets[0]; 242 fb->base.width = cmd->width; 243 fb->base.height = cmd->height; 244 fb->base.pixel_format = cmd->pixel_format; 245 drm_fb_get_bpp_depth(cmd->pixel_format, &fb->base.depth, 246 &fb->base.bits_per_pixel); 247 248 error = tegra_drm_framebuffer_init(ddev, fb); 249 if (error) 250 goto dealloc; 251 252 return &fb->base; 253 254 drm_framebuffer_cleanup(&fb->base); 255 dealloc: 256 kmem_free(fb, sizeof(*fb)); 257 drm_gem_object_unreference_unlocked(gem_obj); 258 259 return NULL; 260 } 261 262 static int 263 tegra_framebuffer_create_handle(struct drm_framebuffer *fb, 264 struct drm_file *file, unsigned int *handle) 265 { 266 struct tegra_framebuffer *tegra_fb = to_tegra_framebuffer(fb); 267 268 return drm_gem_handle_create(file, &tegra_fb->obj->base, handle); 269 } 270 271 static void 272 tegra_framebuffer_destroy(struct drm_framebuffer *fb) 273 { 274 struct tegra_framebuffer *tegra_fb = to_tegra_framebuffer(fb); 275 276 drm_framebuffer_cleanup(fb); 277 drm_gem_object_unreference_unlocked(&tegra_fb->obj->base); 278 kmem_free(tegra_fb, sizeof(*tegra_fb)); 279 } 280 281 static int 282 tegra_crtc_init(struct drm_device *ddev, int index) 283 { 284 struct tegra_drm_softc * const sc = tegra_drm_private(ddev); 285 struct tegra_crtc *crtc; 286 bus_addr_t offset; 287 bus_size_t size; 288 u_int intr; 289 int error; 290 291 if (sc->sc_clk_dc[index] == NULL || 292 sc->sc_clk_hdmi_parent == NULL || 293 sc->sc_rst_dc[index] == NULL) { 294 DRM_ERROR("no clocks configured for crtc %d\n", index); 295 return -EIO; 296 } 297 298 switch (index) { 299 case 0: 300 offset = TEGRA_GHOST_BASE + TEGRA_DISPLAYA_OFFSET; 301 size = TEGRA_DISPLAYA_SIZE; 302 intr = TEGRA_INTR_DISPLAYA; 303 break; 304 case 1: 305 offset = TEGRA_GHOST_BASE + TEGRA_DISPLAYB_OFFSET; 306 size = TEGRA_DISPLAYB_SIZE; 307 intr = TEGRA_INTR_DISPLAYB; 308 break; 309 default: 310 return -EINVAL; 311 } 312 313 crtc = kmem_zalloc(sizeof(*crtc), KM_SLEEP); 314 crtc->index = index; 315 crtc->bst = sc->sc_bst; 316 error = bus_space_map(crtc->bst, offset, size, 0, &crtc->bsh); 317 if (error) { 318 kmem_free(crtc, sizeof(*crtc)); 319 return -error; 320 } 321 crtc->size = size; 322 crtc->intr = intr; 323 crtc->ih = intr_establish_xname(intr, IPL_VM, IST_LEVEL | IST_MPSAFE, 324 tegra_crtc_intr, crtc, device_xname(self)); /* XXX */ 325 if (crtc->ih == NULL) { 326 DRM_ERROR("failed to establish interrupt for crtc %d\n", index); 327 } 328 const size_t cursor_size = 256 * 256 * 4; 329 crtc->cursor_obj = drm_gem_cma_create(ddev, cursor_size); 330 if (crtc->cursor_obj == NULL) { 331 kmem_free(crtc, sizeof(*crtc)); 332 return -ENOMEM; 333 } 334 335 /* Enter reset */ 336 fdtbus_reset_assert(sc->sc_rst_dc[index]); 337 338 /* Turn on power to display partition */ 339 const u_int pmc_partid = index == 0 ? PMC_PARTID_DIS : PMC_PARTID_DISB; 340 tegra_pmc_power(pmc_partid, true); 341 tegra_pmc_remove_clamping(pmc_partid); 342 343 /* Set parent clock to the HDMI parent (ignoring DC parent in DT!) */ 344 error = clk_set_parent(sc->sc_clk_dc[index], 345 sc->sc_clk_hdmi_parent); 346 if (error) { 347 DRM_ERROR("failed to set crtc %d clock parent: %d\n", 348 index, error); 349 return -error; 350 } 351 352 /* Enable DC clock */ 353 error = clk_enable(sc->sc_clk_dc[index]); 354 if (error) { 355 DRM_ERROR("failed to enable crtc %d clock: %d\n", index, error); 356 return -error; 357 } 358 359 /* Leave reset */ 360 fdtbus_reset_deassert(sc->sc_rst_dc[index]); 361 362 crtc->clk_parent = sc->sc_clk_hdmi_parent; 363 364 DC_WRITE(crtc, DC_CMD_INT_ENABLE_REG, DC_CMD_INT_V_BLANK); 365 366 drm_crtc_init(ddev, &crtc->base, &tegra_crtc_funcs); 367 drm_crtc_helper_add(&crtc->base, &tegra_crtc_helper_funcs); 368 369 return 0; 370 } 371 372 static int 373 tegra_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, 374 uint32_t handle, uint32_t width, uint32_t height) 375 { 376 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 377 struct drm_gem_object *gem_obj = NULL; 378 struct drm_gem_cma_object *obj; 379 uint32_t cfg, opt; 380 int error; 381 382 if (tegra_crtc->enabled == false) 383 return 0; 384 385 if (handle == 0) { 386 /* hide cursor */ 387 opt = DC_READ(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG); 388 if ((opt & DC_DISP_DISP_WIN_OPTIONS_CURSOR_ENABLE) != 0) { 389 opt &= ~DC_DISP_DISP_WIN_OPTIONS_CURSOR_ENABLE; 390 DC_WRITE(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG, opt); 391 /* Commit settings */ 392 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 393 DC_CMD_STATE_CONTROL_GENERAL_UPDATE); 394 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 395 DC_CMD_STATE_CONTROL_GENERAL_ACT_REQ); 396 } 397 error = 0; 398 goto done; 399 } 400 401 if ((width != height) || 402 (width != 32 && width != 64 && width != 128 && width != 256)) { 403 DRM_ERROR("Cursor dimension %ux%u not supported\n", 404 width, height); 405 error = -EINVAL; 406 goto done; 407 } 408 409 gem_obj = drm_gem_object_lookup(crtc->dev, file_priv, handle); 410 if (gem_obj == NULL) { 411 DRM_ERROR("Cannot find cursor object %#x for crtc %d\n", 412 handle, tegra_crtc->index); 413 error = -ENOENT; 414 goto done; 415 } 416 obj = to_drm_gem_cma_obj(gem_obj); 417 418 if (obj->base.size < width * height * 4) { 419 DRM_ERROR("Cursor buffer is too small\n"); 420 error = -ENOMEM; 421 goto done; 422 } 423 424 cfg = __SHIFTIN(DC_DISP_CURSOR_START_ADDR_CLIPPING_DISPLAY, 425 DC_DISP_CURSOR_START_ADDR_CLIPPING); 426 switch (width) { 427 case 32: 428 cfg |= __SHIFTIN(DC_DISP_CURSOR_START_ADDR_SIZE_32, 429 DC_DISP_CURSOR_START_ADDR_SIZE); 430 break; 431 case 64: 432 cfg |= __SHIFTIN(DC_DISP_CURSOR_START_ADDR_SIZE_64, 433 DC_DISP_CURSOR_START_ADDR_SIZE); 434 break; 435 case 128: 436 cfg |= __SHIFTIN(DC_DISP_CURSOR_START_ADDR_SIZE_128, 437 DC_DISP_CURSOR_START_ADDR_SIZE); 438 break; 439 case 256: 440 cfg |= __SHIFTIN(DC_DISP_CURSOR_START_ADDR_SIZE_256, 441 DC_DISP_CURSOR_START_ADDR_SIZE); 442 break; 443 } 444 445 /* copy cursor (argb -> rgba) */ 446 struct drm_gem_cma_object *cursor_obj = tegra_crtc->cursor_obj; 447 uint32_t off, *cp = obj->vaddr, *crtc_cp = cursor_obj->vaddr; 448 for (off = 0; off < width * height; off++) { 449 crtc_cp[off] = (cp[off] << 8) | (cp[off] >> 24); 450 } 451 452 const uint64_t paddr = cursor_obj->dmasegs[0].ds_addr; 453 454 DC_WRITE(tegra_crtc, DC_DISP_CURSOR_START_ADDR_HI_REG, 455 (paddr >> 32) & 3); 456 cfg |= __SHIFTIN((paddr >> 10) & 0x3fffff, 457 DC_DISP_CURSOR_START_ADDR_ADDRESS_LO); 458 const uint32_t ocfg = 459 DC_READ(tegra_crtc, DC_DISP_CURSOR_START_ADDR_REG); 460 if (cfg != ocfg) { 461 DC_WRITE(tegra_crtc, DC_DISP_CURSOR_START_ADDR_REG, cfg); 462 } 463 464 cfg = DC_READ(tegra_crtc, DC_DISP_BLEND_CURSOR_CONTROL_REG); 465 cfg &= ~DC_DISP_BLEND_CURSOR_CONTROL_DST_BLEND_FACTOR_SEL; 466 cfg |= __SHIFTIN(2, DC_DISP_BLEND_CURSOR_CONTROL_DST_BLEND_FACTOR_SEL); 467 cfg &= ~DC_DISP_BLEND_CURSOR_CONTROL_SRC_BLEND_FACTOR_SEL; 468 cfg |= __SHIFTIN(1, DC_DISP_BLEND_CURSOR_CONTROL_SRC_BLEND_FACTOR_SEL); 469 cfg &= ~DC_DISP_BLEND_CURSOR_CONTROL_ALPHA; 470 cfg |= __SHIFTIN(255, DC_DISP_BLEND_CURSOR_CONTROL_ALPHA); 471 cfg |= DC_DISP_BLEND_CURSOR_CONTROL_MODE_SEL; 472 DC_WRITE(tegra_crtc, DC_DISP_BLEND_CURSOR_CONTROL_REG, cfg); 473 474 /* set cursor position */ 475 DC_WRITE(tegra_crtc, DC_DISP_CURSOR_POSITION_REG, 476 __SHIFTIN(tegra_crtc->cursor_x, DC_DISP_CURSOR_POSITION_H) | 477 __SHIFTIN(tegra_crtc->cursor_y, DC_DISP_CURSOR_POSITION_V)); 478 479 /* Commit settings */ 480 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 481 DC_CMD_STATE_CONTROL_CURSOR_UPDATE); 482 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 483 DC_CMD_STATE_CONTROL_CURSOR_ACT_REQ); 484 485 /* show cursor */ 486 opt = DC_READ(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG); 487 if ((opt & DC_DISP_DISP_WIN_OPTIONS_CURSOR_ENABLE) == 0) { 488 opt |= DC_DISP_DISP_WIN_OPTIONS_CURSOR_ENABLE; 489 DC_WRITE(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG, opt); 490 491 /* Commit settings */ 492 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 493 DC_CMD_STATE_CONTROL_GENERAL_UPDATE); 494 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 495 DC_CMD_STATE_CONTROL_GENERAL_ACT_REQ); 496 } 497 498 error = 0; 499 500 done: 501 if (error == 0) { 502 /* Wait for activation request to complete */ 503 while (DC_READ(tegra_crtc, DC_CMD_STATE_CONTROL_REG) & 504 DC_CMD_STATE_CONTROL_GENERAL_ACT_REQ) 505 ; 506 } 507 508 if (gem_obj) { 509 drm_gem_object_unreference_unlocked(gem_obj); 510 } 511 512 return error; 513 } 514 515 static int 516 tegra_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) 517 { 518 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 519 520 tegra_crtc->cursor_x = x & 0x3fff; 521 tegra_crtc->cursor_y = y & 0x3fff; 522 523 DC_WRITE(tegra_crtc, DC_DISP_CURSOR_POSITION_REG, 524 __SHIFTIN(x & 0x3fff, DC_DISP_CURSOR_POSITION_H) | 525 __SHIFTIN(y & 0x3fff, DC_DISP_CURSOR_POSITION_V)); 526 527 /* Commit settings */ 528 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 529 DC_CMD_STATE_CONTROL_CURSOR_UPDATE); 530 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 531 DC_CMD_STATE_CONTROL_CURSOR_ACT_REQ); 532 533 return 0; 534 } 535 536 static void 537 tegra_crtc_destroy(struct drm_crtc *crtc) 538 { 539 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 540 drm_crtc_cleanup(crtc); 541 if (tegra_crtc->ih) { 542 intr_disestablish(tegra_crtc->ih); 543 } 544 drm_gem_cma_free_object(&tegra_crtc->cursor_obj->base); 545 bus_space_unmap(tegra_crtc->bst, tegra_crtc->bsh, tegra_crtc->size); 546 kmem_free(tegra_crtc, sizeof(*tegra_crtc)); 547 } 548 549 static void 550 tegra_crtc_dpms(struct drm_crtc *crtc, int mode) 551 { 552 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 553 554 switch (mode) { 555 case DRM_MODE_DPMS_ON: 556 case DRM_MODE_DPMS_STANDBY: 557 case DRM_MODE_DPMS_SUSPEND: 558 DC_SET_CLEAR(tegra_crtc, DC_WINC_A_WIN_OPTIONS_REG, 559 DC_WINC_A_WIN_OPTIONS_WIN_ENABLE, 0); 560 break; 561 case DRM_MODE_DPMS_OFF: 562 DC_SET_CLEAR(tegra_crtc, DC_WINC_A_WIN_OPTIONS_REG, 563 0, DC_WINC_A_WIN_OPTIONS_WIN_ENABLE); 564 break; 565 } 566 } 567 568 static bool 569 tegra_crtc_mode_fixup(struct drm_crtc *crtc, 570 const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) 571 { 572 return true; 573 } 574 575 static int 576 tegra_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, 577 struct drm_display_mode *adjusted_mode, int x, int y, 578 struct drm_framebuffer *old_fb) 579 { 580 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 581 const u_int hspw = mode->crtc_hsync_end - mode->crtc_hsync_start; 582 const u_int hbp = mode->crtc_htotal - mode->crtc_hsync_end; 583 const u_int hfp = mode->crtc_hsync_start - mode->crtc_hdisplay; 584 const u_int vspw = mode->crtc_vsync_end - mode->crtc_vsync_start; 585 const u_int vbp = mode->crtc_vtotal - mode->crtc_vsync_end; 586 const u_int vfp = mode->crtc_vsync_start - mode->crtc_vdisplay; 587 588 /* Set colour depth to ARGB8888 */ 589 DC_WRITE(tegra_crtc, DC_WINC_A_COLOR_DEPTH_REG, 590 __SHIFTIN(DC_WINC_A_COLOR_DEPTH_DEPTH_T_A8R8G8B8, 591 DC_WINC_A_COLOR_DEPTH_DEPTH)); 592 593 /* Disable byte swapping */ 594 DC_WRITE(tegra_crtc, DC_WINC_A_BYTE_SWAP_REG, 595 __SHIFTIN(DC_WINC_A_BYTE_SWAP_SWAP_NOSWAP, 596 DC_WINC_A_BYTE_SWAP_SWAP)); 597 598 /* Initial DDA */ 599 DC_WRITE(tegra_crtc, DC_WINC_A_H_INITIAL_DDA_REG, 0); 600 DC_WRITE(tegra_crtc, DC_WINC_A_V_INITIAL_DDA_REG, 0); 601 DC_WRITE(tegra_crtc, DC_WINC_A_DDA_INCREMENT_REG, 0x10001000); 602 603 /* Window position, size, stride */ 604 DC_WRITE(tegra_crtc, DC_WINC_A_POSITION_REG, 605 __SHIFTIN(0, DC_WINC_A_POSITION_V) | 606 __SHIFTIN(0, DC_WINC_A_POSITION_H)); 607 DC_WRITE(tegra_crtc, DC_WINC_A_SIZE_REG, 608 __SHIFTIN(mode->crtc_vdisplay, DC_WINC_A_SIZE_V) | 609 __SHIFTIN(mode->crtc_hdisplay, DC_WINC_A_SIZE_H)); 610 DC_WRITE(tegra_crtc, DC_WINC_A_PRESCALED_SIZE_REG, 611 __SHIFTIN(mode->crtc_vdisplay, DC_WINC_A_PRESCALED_SIZE_V) | 612 __SHIFTIN(mode->crtc_hdisplay * (TEGRA_DC_DEPTH / 8), 613 DC_WINC_A_PRESCALED_SIZE_H)); 614 DC_WRITE(tegra_crtc, DC_WINC_A_LINE_STRIDE_REG, 615 __SHIFTIN(mode->crtc_hdisplay * (TEGRA_DC_DEPTH / 8), 616 DC_WINC_A_LINE_STRIDE_LINE_STRIDE)); 617 618 tegra_crtc_do_set_base(crtc, old_fb, x, y, 0); 619 620 /* Enable window A */ 621 DC_WRITE(tegra_crtc, DC_WINC_A_WIN_OPTIONS_REG, 622 DC_WINC_A_WIN_OPTIONS_WIN_ENABLE); 623 624 /* Timing and signal options */ 625 DC_WRITE(tegra_crtc, DC_DISP_DISP_TIMING_OPTIONS_REG, 626 __SHIFTIN(1, DC_DISP_DISP_TIMING_OPTIONS_VSYNC_POS)); 627 DC_WRITE(tegra_crtc, DC_DISP_DISP_COLOR_CONTROL_REG, 628 __SHIFTIN(DC_DISP_DISP_COLOR_CONTROL_BASE_COLOR_SIZE_888, 629 DC_DISP_DISP_COLOR_CONTROL_BASE_COLOR_SIZE)); 630 DC_WRITE(tegra_crtc, DC_DISP_DISP_SIGNAL_OPTIONS0_REG, 631 DC_DISP_DISP_SIGNAL_OPTIONS0_H_PULSE2_ENABLE); 632 DC_WRITE(tegra_crtc, DC_DISP_H_PULSE2_CONTROL_REG, 633 __SHIFTIN(DC_DISP_H_PULSE2_CONTROL_V_QUAL_VACTIVE, 634 DC_DISP_H_PULSE2_CONTROL_V_QUAL) | 635 __SHIFTIN(DC_DISP_H_PULSE2_CONTROL_LAST_END_A, 636 DC_DISP_H_PULSE2_CONTROL_LAST)); 637 638 const u_int pulse_start = 1 + hspw + hbp - 10; 639 DC_WRITE(tegra_crtc, DC_DISP_H_PULSE2_POSITION_A_REG, 640 __SHIFTIN(pulse_start, DC_DISP_H_PULSE2_POSITION_A_START) | 641 __SHIFTIN(pulse_start + 8, DC_DISP_H_PULSE2_POSITION_A_END)); 642 643 /* Pixel clock */ 644 const u_int parent_rate = clk_get_rate(tegra_crtc->clk_parent); 645 const u_int div = (parent_rate * 2) / (mode->crtc_clock * 1000) - 2; 646 DC_WRITE(tegra_crtc, DC_DISP_DISP_CLOCK_CONTROL_REG, 647 __SHIFTIN(0, DC_DISP_DISP_CLOCK_CONTROL_PIXEL_CLK_DIVIDER) | 648 __SHIFTIN(div, DC_DISP_DISP_CLOCK_CONTROL_SHIFT_CLK_DIVIDER)); 649 650 /* Mode timings */ 651 DC_WRITE(tegra_crtc, DC_DISP_REF_TO_SYNC_REG, 652 __SHIFTIN(1, DC_DISP_REF_TO_SYNC_V) | 653 __SHIFTIN(1, DC_DISP_REF_TO_SYNC_H)); 654 DC_WRITE(tegra_crtc, DC_DISP_SYNC_WIDTH_REG, 655 __SHIFTIN(vspw, DC_DISP_SYNC_WIDTH_V) | 656 __SHIFTIN(hspw, DC_DISP_SYNC_WIDTH_H)); 657 DC_WRITE(tegra_crtc, DC_DISP_BACK_PORCH_REG, 658 __SHIFTIN(vbp, DC_DISP_BACK_PORCH_V) | 659 __SHIFTIN(hbp, DC_DISP_BACK_PORCH_H)); 660 DC_WRITE(tegra_crtc, DC_DISP_FRONT_PORCH_REG, 661 __SHIFTIN(vfp, DC_DISP_FRONT_PORCH_V) | 662 __SHIFTIN(hfp, DC_DISP_FRONT_PORCH_H)); 663 DC_WRITE(tegra_crtc, DC_DISP_DISP_ACTIVE_REG, 664 __SHIFTIN(mode->crtc_vdisplay, DC_DISP_DISP_ACTIVE_V) | 665 __SHIFTIN(mode->crtc_hdisplay, DC_DISP_DISP_ACTIVE_H)); 666 667 return 0; 668 } 669 670 static int 671 tegra_crtc_do_set_base(struct drm_crtc *crtc, struct drm_framebuffer *fb, 672 int x, int y, int atomic) 673 { 674 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 675 struct tegra_framebuffer *tegra_fb = atomic ? 676 to_tegra_framebuffer(fb) : 677 to_tegra_framebuffer(crtc->primary->fb); 678 679 uint64_t paddr = (uint64_t)tegra_fb->obj->dmamap->dm_segs[0].ds_addr; 680 681 /* Framebuffer start address */ 682 DC_WRITE(tegra_crtc, DC_WINBUF_A_START_ADDR_HI_REG, (paddr >> 32) & 3); 683 DC_WRITE(tegra_crtc, DC_WINBUF_A_START_ADDR_REG, paddr & 0xffffffff); 684 685 /* Offsets */ 686 DC_WRITE(tegra_crtc, DC_WINBUF_A_ADDR_H_OFFSET_REG, x); 687 DC_WRITE(tegra_crtc, DC_WINBUF_A_ADDR_V_OFFSET_REG, y); 688 689 /* Surface kind */ 690 DC_WRITE(tegra_crtc, DC_WINBUF_A_SURFACE_KIND_REG, 691 __SHIFTIN(DC_WINBUF_A_SURFACE_KIND_SURFACE_KIND_PITCH, 692 DC_WINBUF_A_SURFACE_KIND_SURFACE_KIND)); 693 694 return 0; 695 } 696 697 static int 698 tegra_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 699 struct drm_framebuffer *old_fb) 700 { 701 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 702 703 tegra_crtc_do_set_base(crtc, old_fb, x, y, 0); 704 705 /* Commit settings */ 706 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 707 DC_CMD_STATE_CONTROL_WIN_A_UPDATE); 708 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 709 DC_CMD_STATE_CONTROL_WIN_A_ACT_REQ); 710 711 return 0; 712 } 713 714 static int 715 tegra_crtc_mode_set_base_atomic(struct drm_crtc *crtc, 716 struct drm_framebuffer *fb, int x, int y, enum mode_set_atomic state) 717 { 718 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 719 720 tegra_crtc_do_set_base(crtc, fb, x, y, 1); 721 722 /* Commit settings */ 723 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 724 DC_CMD_STATE_CONTROL_WIN_A_UPDATE); 725 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 726 DC_CMD_STATE_CONTROL_WIN_A_ACT_REQ); 727 728 return 0; 729 } 730 731 static void 732 tegra_crtc_disable(struct drm_crtc *crtc) 733 { 734 } 735 736 static void 737 tegra_crtc_prepare(struct drm_crtc *crtc) 738 { 739 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 740 741 /* Access control */ 742 DC_WRITE(tegra_crtc, DC_CMD_STATE_ACCESS_REG, 0); 743 744 /* Enable window A programming */ 745 DC_WRITE(tegra_crtc, DC_CMD_DISPLAY_WINDOW_HEADER_REG, 746 DC_CMD_DISPLAY_WINDOW_HEADER_WINDOW_A_SELECT); 747 } 748 749 static void 750 tegra_crtc_commit(struct drm_crtc *crtc) 751 { 752 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc); 753 754 /* Enable continuous display mode */ 755 DC_WRITE(tegra_crtc, DC_CMD_DISPLAY_COMMAND_REG, 756 __SHIFTIN(DC_CMD_DISPLAY_COMMAND_DISPLAY_CTRL_MODE_C_DISPLAY, 757 DC_CMD_DISPLAY_COMMAND_DISPLAY_CTRL_MODE)); 758 759 /* Enable power */ 760 DC_SET_CLEAR(tegra_crtc, DC_CMD_DISPLAY_POWER_CONTROL_REG, 761 DC_CMD_DISPLAY_POWER_CONTROL_PM1_ENABLE | 762 DC_CMD_DISPLAY_POWER_CONTROL_PM0_ENABLE | 763 DC_CMD_DISPLAY_POWER_CONTROL_PW4_ENABLE | 764 DC_CMD_DISPLAY_POWER_CONTROL_PW3_ENABLE | 765 DC_CMD_DISPLAY_POWER_CONTROL_PW2_ENABLE | 766 DC_CMD_DISPLAY_POWER_CONTROL_PW1_ENABLE | 767 DC_CMD_DISPLAY_POWER_CONTROL_PW0_ENABLE, 768 0); 769 770 /* Commit settings */ 771 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 772 DC_CMD_STATE_CONTROL_GENERAL_UPDATE | 773 DC_CMD_STATE_CONTROL_WIN_A_UPDATE); 774 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 775 DC_CMD_STATE_CONTROL_GENERAL_ACT_REQ | 776 DC_CMD_STATE_CONTROL_WIN_A_ACT_REQ); 777 778 tegra_crtc->enabled = true; 779 } 780 781 static int 782 tegra_encoder_init(struct drm_device *ddev) 783 { 784 struct tegra_drm_softc * const sc = tegra_drm_private(ddev); 785 struct tegra_encoder *encoder; 786 int error; 787 788 if (sc->sc_clk_hdmi == NULL || 789 sc->sc_clk_hdmi_parent == NULL || 790 sc->sc_rst_hdmi == NULL) { 791 DRM_ERROR("no clocks configured for hdmi\n"); 792 DRM_ERROR("clk: hdmi %p parent %p\n", sc->sc_clk_hdmi, sc->sc_clk_hdmi_parent); 793 DRM_ERROR("rst: hdmi %p\n", sc->sc_rst_hdmi); 794 return -EIO; 795 } 796 797 const bus_addr_t offset = TEGRA_GHOST_BASE + TEGRA_HDMI_OFFSET; 798 const bus_size_t size = TEGRA_HDMI_SIZE; 799 800 encoder = kmem_zalloc(sizeof(*encoder), KM_SLEEP); 801 encoder->bst = sc->sc_bst; 802 error = bus_space_map(encoder->bst, offset, size, 0, &encoder->bsh); 803 if (error) { 804 kmem_free(encoder, sizeof(*encoder)); 805 return -error; 806 } 807 encoder->size = size; 808 809 tegra_pmc_hdmi_enable(); 810 811 /* Enable parent PLL */ 812 error = clk_set_rate(sc->sc_clk_hdmi_parent, 594000000); 813 if (error) { 814 DRM_ERROR("couldn't set hdmi parent PLL rate: %d\n", error); 815 return -error; 816 } 817 error = clk_enable(sc->sc_clk_hdmi_parent); 818 if (error) { 819 DRM_ERROR("couldn't enable hdmi parent PLL: %d\n", error); 820 return -error; 821 } 822 823 drm_encoder_init(ddev, &encoder->base, &tegra_encoder_funcs, 824 DRM_MODE_ENCODER_TMDS); 825 drm_encoder_helper_add(&encoder->base, &tegra_encoder_helper_funcs); 826 827 encoder->base.possible_crtcs = (1 << 0) | (1 << 1); 828 829 return tegra_connector_init(ddev, &encoder->base); 830 } 831 832 static void 833 tegra_encoder_destroy(struct drm_encoder *encoder) 834 { 835 struct tegra_encoder *tegra_encoder = to_tegra_encoder(encoder); 836 drm_encoder_cleanup(encoder); 837 kmem_free(tegra_encoder, sizeof(*tegra_encoder)); 838 } 839 840 static void 841 tegra_encoder_dpms(struct drm_encoder *encoder, int mode) 842 { 843 struct tegra_encoder *tegra_encoder = to_tegra_encoder(encoder); 844 845 if (encoder->crtc == NULL) 846 return; 847 848 switch (mode) { 849 case DRM_MODE_DPMS_ON: 850 case DRM_MODE_DPMS_STANDBY: 851 case DRM_MODE_DPMS_SUSPEND: 852 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_BLANK_REG, 853 0, HDMI_NV_PDISP_SOR_BLANK_OVERRIDE); 854 break; 855 case DRM_MODE_DPMS_OFF: 856 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_BLANK_REG, 857 HDMI_NV_PDISP_SOR_BLANK_OVERRIDE, 0); 858 break; 859 } 860 } 861 862 static bool 863 tegra_encoder_mode_fixup(struct drm_encoder *encoder, 864 const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) 865 { 866 return true; 867 } 868 869 static int 870 tegra_encoder_hdmi_set_clock(struct drm_encoder *encoder, u_int rate) 871 { 872 struct drm_device *ddev = encoder->dev; 873 struct tegra_drm_softc * const sc = tegra_drm_private(ddev); 874 int error; 875 876 /* Enter reset */ 877 fdtbus_reset_assert(sc->sc_rst_hdmi); 878 879 /* Set HDMI parent clock */ 880 error = clk_set_parent(sc->sc_clk_hdmi, sc->sc_clk_hdmi_parent); 881 if (error) { 882 DRM_ERROR("couldn't set hdmi parent: %d\n", error); 883 return -error; 884 } 885 886 /* Set dot clock frequency */ 887 error = clk_set_rate(sc->sc_clk_hdmi, rate); 888 if (error) { 889 DRM_ERROR("couldn't set hdmi clock: %d\n", error); 890 return -error; 891 } 892 error = clk_enable(sc->sc_clk_hdmi); 893 if (error) { 894 DRM_ERROR("couldn't enable hdmi clock: %d\n", error); 895 return -error; 896 } 897 898 /* Leave reset */ 899 fdtbus_reset_deassert(sc->sc_rst_hdmi); 900 901 return 0; 902 } 903 904 static void 905 tegra_encoder_mode_set(struct drm_encoder *encoder, 906 struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) 907 { 908 struct drm_device *ddev = encoder->dev; 909 struct tegra_encoder *tegra_encoder = to_tegra_encoder(encoder); 910 struct tegra_crtc *tegra_crtc = to_tegra_crtc(encoder->crtc); 911 struct tegra_connector *tegra_connector = NULL; 912 struct drm_connector *connector; 913 const struct tegra_hdmi_tmds_config *tmds = NULL; 914 uint32_t input_ctrl; 915 int retry; 916 u_int i; 917 918 tegra_encoder_hdmi_set_clock(encoder, mode->crtc_clock * 1000); 919 920 /* find the connector for this encoder */ 921 list_for_each_entry(connector, &ddev->mode_config.connector_list, head) { 922 if (connector->encoder == encoder) { 923 tegra_connector = to_tegra_connector(connector); 924 break; 925 } 926 } 927 928 for (i = 0; i < __arraycount(tegra_hdmi_tmds_config); i++) { 929 if (tegra_hdmi_tmds_config[i].dot_clock >= mode->crtc_clock) { 930 break; 931 } 932 } 933 if (i < __arraycount(tegra_hdmi_tmds_config)) { 934 tmds = &tegra_hdmi_tmds_config[i]; 935 } else { 936 tmds = &tegra_hdmi_tmds_config[__arraycount(tegra_hdmi_tmds_config) - 1]; 937 } 938 939 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PLL0_REG, tmds->sor_pll0); 940 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PLL1_REG, tmds->sor_pll1); 941 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT_REG, 942 tmds->sor_lane_drive_current); 943 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_PE_CURRENT_REG, 944 tmds->pe_current); 945 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT_REG, 946 tmds->sor_io_peak_current); 947 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PAD_CTLS0_REG, 948 tmds->sor_pad_ctls0); 949 950 const u_int div = (mode->crtc_clock / 1000) * 4; 951 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_REFCLK_REG, 952 __SHIFTIN(div >> 2, HDMI_NV_PDISP_SOR_REFCLK_DIV_INT) | 953 __SHIFTIN(div & 3, HDMI_NV_PDISP_SOR_REFCLK_DIV_FRAC)); 954 955 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_CSTM_REG, 956 __SHIFTIN(HDMI_NV_PDISP_SOR_CSTM_MODE_TMDS, 957 HDMI_NV_PDISP_SOR_CSTM_MODE) | 958 __SHIFTIN(2, HDMI_NV_PDISP_SOR_CSTM_ROTCLK) | 959 HDMI_NV_PDISP_SOR_CSTM_PLLDIV, 960 HDMI_NV_PDISP_SOR_CSTM_MODE | 961 HDMI_NV_PDISP_SOR_CSTM_ROTCLK | 962 HDMI_NV_PDISP_SOR_CSTM_LVDS_EN); 963 964 const uint32_t inst = 965 HDMI_NV_PDISP_SOR_SEQ_INST_DRIVE_PWM_OUT_LO | 966 HDMI_NV_PDISP_SOR_SEQ_INST_HALT | 967 __SHIFTIN(2, HDMI_NV_PDISP_SOR_SEQ_INST_WAIT_UNITS) | 968 __SHIFTIN(1, HDMI_NV_PDISP_SOR_SEQ_INST_WAIT_TIME); 969 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_SEQ_INST0_REG, inst); 970 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_SEQ_INST8_REG, inst); 971 972 input_ctrl = __SHIFTIN(tegra_crtc->index, 973 HDMI_NV_PDISP_INPUT_CONTROL_HDMI_SRC_SELECT); 974 if (mode->crtc_hdisplay != 640 || mode->crtc_vdisplay != 480) 975 input_ctrl |= HDMI_NV_PDISP_INPUT_CONTROL_ARM_VIDEO_RANGE; 976 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_INPUT_CONTROL_REG, input_ctrl); 977 978 /* Start SOR */ 979 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_PLL0_REG, 980 0, 981 HDMI_NV_PDISP_SOR_PLL0_PWR | 982 HDMI_NV_PDISP_SOR_PLL0_VCOPD | 983 HDMI_NV_PDISP_SOR_PLL0_PULLDOWN); 984 delay(10); 985 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_PLL0_REG, 986 0, 987 HDMI_NV_PDISP_SOR_PLL0_PDBG); 988 989 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PWR_REG, 990 HDMI_NV_PDISP_SOR_PWR_NORMAL_STATE | 991 HDMI_NV_PDISP_SOR_PWR_SETTING_NEW); 992 993 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PWR_REG, 994 HDMI_NV_PDISP_SOR_PWR_NORMAL_STATE); 995 996 for (retry = 10000; retry > 0; retry--) { 997 const uint32_t pwr = HDMI_READ(tegra_encoder, 998 HDMI_NV_PDISP_SOR_PWR_REG); 999 if ((pwr & HDMI_NV_PDISP_SOR_PWR_SETTING_NEW) == 0) 1000 break; 1001 delay(10); 1002 } 1003 if (retry == 0) { 1004 DRM_ERROR("timeout enabling SOR power\n"); 1005 } 1006 1007 uint32_t state2 = 1008 __SHIFTIN(1, HDMI_NV_PDISP_SOR_STATE2_ASY_OWNER) | 1009 __SHIFTIN(3, HDMI_NV_PDISP_SOR_STATE2_ASY_SUBOWNER) | 1010 __SHIFTIN(1, HDMI_NV_PDISP_SOR_STATE2_ASY_CRCMODE) | 1011 __SHIFTIN(1, HDMI_NV_PDISP_SOR_STATE2_ASY_PROTOCOL); 1012 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 1013 state2 |= HDMI_NV_PDISP_SOR_STATE2_ASY_HSYNCPOL; 1014 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 1015 state2 |= HDMI_NV_PDISP_SOR_STATE2_ASY_VSYNCPOL; 1016 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_STATE2_REG, state2); 1017 1018 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_STATE1_REG, 1019 __SHIFTIN(HDMI_NV_PDISP_SOR_STATE1_ASY_HEAD_OPMODE_AWAKE, 1020 HDMI_NV_PDISP_SOR_STATE1_ASY_HEAD_OPMODE) | 1021 HDMI_NV_PDISP_SOR_STATE1_ASY_ORMODE); 1022 1023 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_STATE0_REG, 0); 1024 1025 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_STATE0_REG, 1026 HDMI_NV_PDISP_SOR_STATE0_UPDATE); 1027 1028 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_STATE1_REG, 1029 HDMI_NV_PDISP_SOR_STATE1_ATTACHED, 0); 1030 1031 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_STATE0_REG, 0); 1032 1033 const u_int rekey = 56; 1034 const u_int hspw = mode->hsync_end - mode->hsync_start; 1035 const u_int hbp = mode->htotal - mode->hsync_end; 1036 const u_int hfp = mode->hsync_start - mode->hdisplay; 1037 const u_int max_ac_packet = (hspw + hbp + hfp - rekey - 18) / 32; 1038 uint32_t ctrl = 1039 __SHIFTIN(rekey, HDMI_NV_PDISP_HDMI_CTRL_REKEY) | 1040 __SHIFTIN(max_ac_packet, HDMI_NV_PDISP_HDMI_CTRL_MAX_AC_PACKET); 1041 if (tegra_connector && tegra_connector->has_hdmi_sink) { 1042 ctrl |= HDMI_NV_PDISP_HDMI_CTRL_ENABLE; /* HDMI ENABLE */ 1043 } 1044 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_HDMI_CTRL_REG, ctrl); 1045 1046 if (tegra_connector && tegra_connector->has_hdmi_sink && 1047 tegra_connector->has_audio) { 1048 struct hdmi_audio_infoframe ai; 1049 struct hdmi_avi_infoframe avii; 1050 uint8_t aibuf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE]; 1051 uint8_t aviibuf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 1052 const u_int n = 6144; /* 48 kHz */ 1053 const u_int cts = ((mode->crtc_clock * 10) * (n / 128)) / 480; 1054 1055 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_REG, 1056 __SHIFTIN(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO, 1057 HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SOURCE_SELECT) | 1058 HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_INJECT_NULLSMPL); 1059 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_AUDIO_N_REG, 1060 HDMI_NV_PDISP_AUDIO_N_RESETF | 1061 HDMI_NV_PDISP_AUDIO_N_GENERATE | 1062 __SHIFTIN(n - 1, HDMI_NV_PDISP_AUDIO_N_VALUE)); 1063 1064 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_HDMI_SPARE_REG, 1065 HDMI_NV_PDISP_HDMI_SPARE_HW_CTS | 1066 HDMI_NV_PDISP_HDMI_SPARE_FORCE_SW_CTS | 1067 __SHIFTIN(1, HDMI_NV_PDISP_HDMI_SPARE_CTS_RESET_VAL)); 1068 1069 /* 1070 * When HW_CTS=1 and FORCE_SW_CTS=1, the CTS is programmed by 1071 * software in the 44.1 kHz register regardless of chosen rate. 1072 */ 1073 HDMI_WRITE(tegra_encoder, 1074 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW_REG, 1075 cts << 8); 1076 HDMI_WRITE(tegra_encoder, 1077 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH_REG, 1078 0x80000000 | n); 1079 1080 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_AUDIO_N_REG, 0, 1081 HDMI_NV_PDISP_AUDIO_N_RESETF); 1082 1083 HDMI_WRITE(tegra_encoder, 1084 HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480_REG, 24000); 1085 1086 hdmi_audio_infoframe_init(&ai); 1087 ai.channels = 2; 1088 hdmi_audio_infoframe_pack(&ai, aibuf, sizeof(aibuf)); 1089 HDMI_WRITE(tegra_encoder, 1090 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER_REG, 1091 aibuf[0] | (aibuf[1] << 8) | (aibuf[2] << 16)); 1092 HDMI_WRITE(tegra_encoder, 1093 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_REG, 1094 aibuf[3] | (aibuf[4] << 8) | 1095 (aibuf[5] << 16) | (aibuf[6] << 24)); 1096 HDMI_WRITE(tegra_encoder, 1097 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_REG, 1098 aibuf[7] | (aibuf[8] << 8) | (aibuf[9] << 16)); 1099 1100 hdmi_avi_infoframe_init(&avii); 1101 drm_hdmi_avi_infoframe_from_display_mode(&avii, mode); 1102 hdmi_avi_infoframe_pack(&avii, aviibuf, sizeof(aviibuf)); 1103 HDMI_WRITE(tegra_encoder, 1104 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER_REG, 1105 aviibuf[0] | (aviibuf[1] << 8) | (aviibuf[2] << 16)); 1106 HDMI_WRITE(tegra_encoder, 1107 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_REG, 1108 aviibuf[3] | (aviibuf[4] << 8) | 1109 (aviibuf[5] << 16) | (aviibuf[6] << 24)); 1110 HDMI_WRITE(tegra_encoder, 1111 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_REG, 1112 aviibuf[7] | (aviibuf[8] << 8) | (aviibuf[9] << 16)); 1113 HDMI_WRITE(tegra_encoder, 1114 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_REG, 1115 aviibuf[10] | (aviibuf[11] << 8) | 1116 (aviibuf[12] << 16) | (aviibuf[13] << 24)); 1117 HDMI_WRITE(tegra_encoder, 1118 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_REG, 1119 aviibuf[14] | (aviibuf[15] << 8) | (aviibuf[16] << 16)); 1120 1121 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_HDMI_GENERIC_CTRL_REG, 1122 HDMI_NV_PDISP_HDMI_GENERIC_CTRL_AUDIO); 1123 HDMI_WRITE(tegra_encoder, 1124 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_REG, 1125 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_ENABLE); 1126 HDMI_WRITE(tegra_encoder, 1127 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_REG, 1128 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_ENABLE); 1129 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_HDMI_ACR_CTRL_REG, 0); 1130 } else { 1131 HDMI_WRITE(tegra_encoder, 1132 HDMI_NV_PDISP_HDMI_GENERIC_CTRL_REG, 0); 1133 HDMI_WRITE(tegra_encoder, 1134 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_REG, 0); 1135 HDMI_WRITE(tegra_encoder, 1136 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_REG, 0); 1137 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_HDMI_ACR_CTRL_REG, 0); 1138 } 1139 1140 /* Enable DC output to HDMI */ 1141 DC_SET_CLEAR(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG, 1142 DC_DISP_DISP_WIN_OPTIONS_HDMI_ENABLE, 0); 1143 1144 /* Commit settings */ 1145 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 1146 DC_CMD_STATE_CONTROL_GENERAL_UPDATE | 1147 DC_CMD_STATE_CONTROL_WIN_A_UPDATE); 1148 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG, 1149 DC_CMD_STATE_CONTROL_GENERAL_ACT_REQ | 1150 DC_CMD_STATE_CONTROL_WIN_A_ACT_REQ); 1151 } 1152 1153 static void 1154 tegra_encoder_prepare(struct drm_encoder *encoder) 1155 { 1156 } 1157 1158 static void 1159 tegra_encoder_commit(struct drm_encoder *encoder) 1160 { 1161 } 1162 1163 static int 1164 tegra_connector_init(struct drm_device *ddev, struct drm_encoder *encoder) 1165 { 1166 struct tegra_drm_softc * const sc = tegra_drm_private(ddev); 1167 struct tegra_connector *connector; 1168 1169 connector = kmem_zalloc(sizeof(*connector), KM_SLEEP); 1170 1171 drm_connector_init(ddev, &connector->base, &tegra_connector_funcs, 1172 DRM_MODE_CONNECTOR_HDMIA); 1173 drm_connector_helper_add(&connector->base, 1174 &tegra_connector_helper_funcs); 1175 1176 connector->base.interlace_allowed = 0; 1177 connector->base.doublescan_allowed = 0; 1178 1179 drm_sysfs_connector_add(&connector->base); 1180 1181 connector->base.polled = 1182 DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 1183 1184 drm_mode_connector_attach_encoder(&connector->base, encoder); 1185 1186 connector->hpd = sc->sc_pin_hpd; 1187 if (!connector->hpd) 1188 DRM_ERROR("failed to find hpd pin for connector\n"); 1189 1190 connector->ddc = sc->sc_ddc; 1191 if (!connector->ddc) 1192 DRM_ERROR("failed to find ddc device for connector\n"); 1193 1194 return drm_connector_register(&connector->base); 1195 } 1196 1197 static void 1198 tegra_connector_destroy(struct drm_connector *connector) 1199 { 1200 struct tegra_connector *tegra_connector = to_tegra_connector(connector); 1201 1202 drm_sysfs_connector_remove(connector); 1203 drm_connector_cleanup(connector); 1204 kmem_free(tegra_connector, sizeof(*tegra_connector)); 1205 } 1206 1207 static enum drm_connector_status 1208 tegra_connector_detect(struct drm_connector *connector, bool force) 1209 { 1210 struct tegra_connector *tegra_connector = to_tegra_connector(connector); 1211 bool con; 1212 1213 1214 if (!tegra_connector->hpd) { 1215 tegra_connector->has_hdmi_sink = false; 1216 tegra_connector->has_audio = false; 1217 return connector_status_connected; 1218 } 1219 1220 con = fdtbus_gpio_read(tegra_connector->hpd); 1221 if (con) { 1222 return connector_status_connected; 1223 } else { 1224 prop_dictionary_t prop = device_properties(connector->dev->dev); 1225 prop_dictionary_remove(prop, "physical-address"); 1226 tegra_connector->has_hdmi_sink = false; 1227 tegra_connector->has_audio = false; 1228 return connector_status_disconnected; 1229 } 1230 } 1231 1232 static int 1233 tegra_connector_mode_valid(struct drm_connector *connector, 1234 struct drm_display_mode *mode) 1235 { 1236 return MODE_OK; 1237 } 1238 1239 static int 1240 tegra_connector_get_modes(struct drm_connector *connector) 1241 { 1242 struct tegra_connector *tegra_connector = to_tegra_connector(connector); 1243 struct tegra_drm_softc * const sc = tegra_drm_private(connector->dev); 1244 prop_dictionary_t prop = device_properties(connector->dev->dev); 1245 char edid[EDID_LENGTH * 4]; 1246 struct edid *pedid = NULL; 1247 int error, block; 1248 1249 if (tegra_connector->ddc) { 1250 memset(edid, 0, sizeof(edid)); 1251 for (block = 0; block < 4; block++) { 1252 error = ddc_read_edid_block(tegra_connector->ddc, 1253 &edid[block * EDID_LENGTH], EDID_LENGTH, block); 1254 if (error) 1255 break; 1256 if (block == 0) { 1257 pedid = (struct edid *)edid; 1258 if (edid[0x7e] == 0) 1259 break; 1260 } 1261 } 1262 } 1263 1264 if (pedid) { 1265 if (sc->sc_force_dvi) { 1266 tegra_connector->has_hdmi_sink = false; 1267 tegra_connector->has_audio = false; 1268 } else { 1269 tegra_connector->has_hdmi_sink = 1270 drm_detect_hdmi_monitor(pedid); 1271 tegra_connector->has_audio = 1272 drm_detect_monitor_audio(pedid); 1273 } 1274 drm_mode_connector_update_edid_property(connector, pedid); 1275 error = drm_add_edid_modes(connector, pedid); 1276 drm_edid_to_eld(connector, pedid); 1277 if (drm_detect_hdmi_monitor(pedid)) { 1278 prop_dictionary_set_uint16(prop, "physical-address", 1279 connector->physical_address); 1280 } 1281 return error; 1282 } else { 1283 drm_mode_connector_update_edid_property(connector, NULL); 1284 return 0; 1285 } 1286 } 1287 1288 static struct drm_encoder * 1289 tegra_connector_best_encoder(struct drm_connector *connector) 1290 { 1291 int enc_id = connector->encoder_ids[0]; 1292 struct drm_mode_object *obj; 1293 struct drm_encoder *encoder = NULL; 1294 1295 if (enc_id) { 1296 obj = drm_mode_object_find(connector->dev, enc_id, 1297 DRM_MODE_OBJECT_ENCODER); 1298 if (obj == NULL) 1299 return NULL; 1300 encoder = obj_to_encoder(obj); 1301 } 1302 1303 return encoder; 1304 } 1305 1306 static int 1307 tegra_crtc_intr(void *priv) 1308 { 1309 struct tegra_crtc *tegra_crtc = priv; 1310 struct drm_device *ddev = tegra_crtc->base.dev; 1311 struct tegra_drm_softc * const sc = tegra_drm_private(ddev); 1312 int rv = 0; 1313 1314 const uint32_t status = DC_READ(tegra_crtc, DC_CMD_INT_STATUS_REG); 1315 1316 if (status & DC_CMD_INT_V_BLANK) { 1317 DC_WRITE(tegra_crtc, DC_CMD_INT_STATUS_REG, DC_CMD_INT_V_BLANK); 1318 atomic_inc_32(&sc->sc_vbl_received[tegra_crtc->index]); 1319 drm_handle_vblank(ddev, tegra_crtc->index); 1320 rv = 1; 1321 } 1322 1323 return rv; 1324 } 1325 1326 u32 1327 tegra_drm_get_vblank_counter(struct drm_device *ddev, unsigned int crtc) 1328 { 1329 struct tegra_drm_softc * const sc = tegra_drm_private(ddev); 1330 1331 if (crtc > 1) 1332 return 0; 1333 1334 return sc->sc_vbl_received[crtc]; 1335 } 1336 1337 int 1338 tegra_drm_enable_vblank(struct drm_device *ddev, unsigned int crtc) 1339 { 1340 struct tegra_crtc *tegra_crtc = NULL; 1341 struct drm_crtc *iter; 1342 1343 list_for_each_entry(iter, &ddev->mode_config.crtc_list, head) { 1344 if (to_tegra_crtc(iter)->index == crtc) { 1345 tegra_crtc = to_tegra_crtc(iter); 1346 break; 1347 } 1348 } 1349 if (tegra_crtc == NULL) 1350 return -EINVAL; 1351 1352 DC_SET_CLEAR(tegra_crtc, DC_CMD_INT_MASK_REG, DC_CMD_INT_V_BLANK, 0); 1353 1354 return 0; 1355 } 1356 1357 void 1358 tegra_drm_disable_vblank(struct drm_device *ddev, unsigned int crtc) 1359 { 1360 struct tegra_crtc *tegra_crtc = NULL; 1361 struct drm_crtc *iter; 1362 1363 list_for_each_entry(iter, &ddev->mode_config.crtc_list, head) { 1364 if (to_tegra_crtc(iter)->index == crtc) { 1365 tegra_crtc = to_tegra_crtc(iter); 1366 break; 1367 } 1368 } 1369 if (tegra_crtc == NULL) 1370 return; 1371 1372 DC_SET_CLEAR(tegra_crtc, DC_CMD_INT_MASK_REG, 0, DC_CMD_INT_V_BLANK); 1373 DC_WRITE(tegra_crtc, DC_CMD_INT_STATUS_REG, DC_CMD_INT_V_BLANK); 1374 } 1375
Indexes created Fri Oct 17 00:09:41 GMT 2025