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tegra_ehci.c revision 1.5
      1  1.5     skrll /* $NetBSD: tegra_ehci.c,v 1.5 2015/05/18 09:56:43 skrll Exp $ */
      2  1.1  jmcneill 
      3  1.1  jmcneill /*-
      4  1.1  jmcneill  * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca>
      5  1.1  jmcneill  * All rights reserved.
      6  1.1  jmcneill  *
      7  1.1  jmcneill  * Redistribution and use in source and binary forms, with or without
      8  1.1  jmcneill  * modification, are permitted provided that the following conditions
      9  1.1  jmcneill  * are met:
     10  1.1  jmcneill  * 1. Redistributions of source code must retain the above copyright
     11  1.1  jmcneill  *    notice, this list of conditions and the following disclaimer.
     12  1.1  jmcneill  * 2. Redistributions in binary form must reproduce the above copyright
     13  1.1  jmcneill  *    notice, this list of conditions and the following disclaimer in the
     14  1.1  jmcneill  *    documentation and/or other materials provided with the distribution.
     15  1.1  jmcneill  *
     16  1.1  jmcneill  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  1.1  jmcneill  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  1.1  jmcneill  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  1.1  jmcneill  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  1.1  jmcneill  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  1.1  jmcneill  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  1.1  jmcneill  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  1.1  jmcneill  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  1.1  jmcneill  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  1.1  jmcneill  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  1.1  jmcneill  * SUCH DAMAGE.
     27  1.1  jmcneill  */
     28  1.1  jmcneill 
     29  1.1  jmcneill #include "locators.h"
     30  1.1  jmcneill 
     31  1.1  jmcneill #include <sys/cdefs.h>
     32  1.5     skrll __KERNEL_RCSID(0, "$NetBSD: tegra_ehci.c,v 1.5 2015/05/18 09:56:43 skrll Exp $");
     33  1.1  jmcneill 
     34  1.1  jmcneill #include <sys/param.h>
     35  1.1  jmcneill #include <sys/bus.h>
     36  1.1  jmcneill #include <sys/device.h>
     37  1.1  jmcneill #include <sys/intr.h>
     38  1.1  jmcneill #include <sys/systm.h>
     39  1.1  jmcneill #include <sys/kernel.h>
     40  1.1  jmcneill 
     41  1.1  jmcneill #include <dev/usb/usb.h>
     42  1.1  jmcneill #include <dev/usb/usbdi.h>
     43  1.1  jmcneill #include <dev/usb/usbdivar.h>
     44  1.1  jmcneill #include <dev/usb/usb_mem.h>
     45  1.1  jmcneill #include <dev/usb/ehcireg.h>
     46  1.1  jmcneill #include <dev/usb/ehcivar.h>
     47  1.1  jmcneill 
     48  1.1  jmcneill #include <arm/nvidia/tegra_var.h>
     49  1.4  jmcneill #include <arm/nvidia/tegra_ehcireg.h>
     50  1.1  jmcneill 
     51  1.2  jmcneill #define TEGRA_EHCI_REG_OFFSET	0x100
     52  1.2  jmcneill 
     53  1.1  jmcneill static int	tegra_ehci_match(device_t, cfdata_t, void *);
     54  1.1  jmcneill static void	tegra_ehci_attach(device_t, device_t, void *);
     55  1.1  jmcneill 
     56  1.4  jmcneill static void	tegra_ehci_init(struct ehci_softc *);
     57  1.4  jmcneill 
     58  1.1  jmcneill struct tegra_ehci_softc {
     59  1.1  jmcneill 	struct ehci_softc	sc;
     60  1.4  jmcneill 	bus_space_tag_t		sc_bst;
     61  1.4  jmcneill 	bus_space_handle_t	sc_bsh;
     62  1.1  jmcneill 	void			*sc_ih;
     63  1.4  jmcneill 	u_int			sc_port;
     64  1.3  jmcneill 
     65  1.3  jmcneill 	struct tegra_gpio_pin	*sc_pin_vbus;
     66  1.1  jmcneill };
     67  1.1  jmcneill 
     68  1.4  jmcneill static void	tegra_ehci_utmip_init(struct tegra_ehci_softc *);
     69  1.5     skrll static int	tegra_ehci_port_status(struct ehci_softc *sc, uint32_t v,
     70  1.5     skrll 		    int i);
     71  1.4  jmcneill 
     72  1.1  jmcneill CFATTACH_DECL2_NEW(tegra_ehci, sizeof(struct tegra_ehci_softc),
     73  1.1  jmcneill 	tegra_ehci_match, tegra_ehci_attach, NULL,
     74  1.1  jmcneill 	ehci_activate, NULL, ehci_childdet);
     75  1.1  jmcneill 
     76  1.1  jmcneill static int
     77  1.1  jmcneill tegra_ehci_match(device_t parent, cfdata_t cf, void *aux)
     78  1.1  jmcneill {
     79  1.1  jmcneill 	return 1;
     80  1.1  jmcneill }
     81  1.1  jmcneill 
     82  1.1  jmcneill static void
     83  1.1  jmcneill tegra_ehci_attach(device_t parent, device_t self, void *aux)
     84  1.1  jmcneill {
     85  1.1  jmcneill 	struct tegra_ehci_softc * const sc = device_private(self);
     86  1.1  jmcneill 	struct tegraio_attach_args * const tio = aux;
     87  1.1  jmcneill 	const struct tegra_locators * const loc = &tio->tio_loc;
     88  1.3  jmcneill 	prop_dictionary_t prop = device_properties(self);
     89  1.3  jmcneill 	const char *pin;
     90  1.1  jmcneill 	int error;
     91  1.1  jmcneill 
     92  1.4  jmcneill 	sc->sc_bst = tio->tio_bst;
     93  1.4  jmcneill 	bus_space_subregion(tio->tio_bst, tio->tio_bsh,
     94  1.4  jmcneill 	    loc->loc_offset, loc->loc_size, &sc->sc_bsh);
     95  1.4  jmcneill 	sc->sc_port = loc->loc_port;
     96  1.4  jmcneill 
     97  1.1  jmcneill 	sc->sc.sc_dev = self;
     98  1.1  jmcneill 	sc->sc.sc_bus.hci_private = &sc->sc;
     99  1.1  jmcneill 	sc->sc.sc_bus.dmatag = tio->tio_dmat;
    100  1.1  jmcneill 	sc->sc.sc_bus.usbrev = USBREV_2_0;
    101  1.5     skrll 	sc->sc.sc_vendor_port_status = tegra_ehci_port_status;
    102  1.5     skrll 	sc->sc.sc_ncomp = 0;
    103  1.5     skrll 	sc->sc.sc_flags = EHCIF_ETTF;
    104  1.1  jmcneill 	sc->sc.sc_id_vendor = 0x10de;
    105  1.1  jmcneill 	strlcpy(sc->sc.sc_vendor, "Tegra", sizeof(sc->sc.sc_vendor));
    106  1.1  jmcneill 	sc->sc.sc_size = loc->loc_size;
    107  1.1  jmcneill 	sc->sc.iot = tio->tio_bst;
    108  1.1  jmcneill 	bus_space_subregion(tio->tio_bst, tio->tio_bsh,
    109  1.2  jmcneill 	    loc->loc_offset + TEGRA_EHCI_REG_OFFSET,
    110  1.2  jmcneill 	    loc->loc_size - TEGRA_EHCI_REG_OFFSET, &sc->sc.ioh);
    111  1.4  jmcneill 	sc->sc.sc_vendor_init = tegra_ehci_init;
    112  1.1  jmcneill 
    113  1.1  jmcneill 	aprint_naive("\n");
    114  1.1  jmcneill 	aprint_normal(": USB%d\n", loc->loc_port + 1);
    115  1.1  jmcneill 
    116  1.4  jmcneill 	tegra_car_periph_usb_enable(sc->sc_port);
    117  1.4  jmcneill 	delay(2);
    118  1.4  jmcneill 
    119  1.4  jmcneill 	tegra_ehci_utmip_init(sc);
    120  1.4  jmcneill 
    121  1.3  jmcneill 	if (prop_dictionary_get_cstring_nocopy(prop, "vbus-gpio", &pin)) {
    122  1.4  jmcneill 		const uint32_t v = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
    123  1.4  jmcneill 		    TEGRA_EHCI_PHY_VBUS_SENSORS_REG);
    124  1.4  jmcneill 		if ((v & TEGRA_EHCI_PHY_VBUS_SENSORS_A_VBUS_VLD_STS) == 0) {
    125  1.4  jmcneill 			sc->sc_pin_vbus = tegra_gpio_acquire(pin,
    126  1.4  jmcneill 			    GPIO_PIN_OUTPUT | GPIO_PIN_OPENDRAIN);
    127  1.4  jmcneill 			if (sc->sc_pin_vbus)
    128  1.4  jmcneill 				tegra_gpio_write(sc->sc_pin_vbus, 1);
    129  1.4  jmcneill 		} else {
    130  1.4  jmcneill 			aprint_normal_dev(self, "VBUS input active\n");
    131  1.4  jmcneill 		}
    132  1.3  jmcneill         }
    133  1.3  jmcneill 
    134  1.1  jmcneill 	sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH);
    135  1.1  jmcneill 
    136  1.1  jmcneill 	sc->sc_ih = intr_establish(loc->loc_intr, IPL_USB, IST_LEVEL,
    137  1.1  jmcneill 	    ehci_intr, &sc->sc);
    138  1.1  jmcneill 	if (sc->sc_ih == NULL) {
    139  1.1  jmcneill 		aprint_error_dev(self, "couldn't establish interrupt %d\n",
    140  1.1  jmcneill 		    loc->loc_intr);
    141  1.1  jmcneill 		return;
    142  1.1  jmcneill 	}
    143  1.1  jmcneill 	aprint_normal_dev(self, "interrupting on irq %d\n", loc->loc_intr);
    144  1.1  jmcneill 
    145  1.1  jmcneill 	error = ehci_init(&sc->sc);
    146  1.1  jmcneill 	if (error != USBD_NORMAL_COMPLETION) {
    147  1.1  jmcneill 		aprint_error_dev(self, "init failed, error = %d\n", error);
    148  1.1  jmcneill 		return;
    149  1.1  jmcneill 	}
    150  1.1  jmcneill 
    151  1.1  jmcneill 	sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint);
    152  1.1  jmcneill }
    153  1.4  jmcneill 
    154  1.4  jmcneill static void
    155  1.4  jmcneill tegra_ehci_init(struct ehci_softc *esc)
    156  1.4  jmcneill {
    157  1.4  jmcneill 	struct tegra_ehci_softc * const sc = device_private(esc->sc_dev);
    158  1.4  jmcneill 	uint32_t usbmode;
    159  1.4  jmcneill 
    160  1.4  jmcneill 	usbmode = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
    161  1.4  jmcneill 	    TEGRA_EHCI_USBMODE_REG);
    162  1.4  jmcneill 
    163  1.4  jmcneill 	const u_int cm = __SHIFTOUT(usbmode, TEGRA_EHCI_USBMODE_CM);
    164  1.4  jmcneill 	if (cm != TEGRA_EHCI_USBMODE_CM_HOST) {
    165  1.4  jmcneill 		aprint_verbose_dev(esc->sc_dev, "switching to host mode\n");
    166  1.4  jmcneill 		usbmode &= ~TEGRA_EHCI_USBMODE_CM;
    167  1.4  jmcneill 		usbmode |= __SHIFTIN(TEGRA_EHCI_USBMODE_CM_HOST,
    168  1.4  jmcneill 				     TEGRA_EHCI_USBMODE_CM);
    169  1.4  jmcneill 		bus_space_write_4(sc->sc_bst, sc->sc_bsh,
    170  1.4  jmcneill 		    TEGRA_EHCI_USBMODE_REG, usbmode);
    171  1.4  jmcneill 	}
    172  1.4  jmcneill 
    173  1.4  jmcneill 	/* Parallel transceiver select */
    174  1.4  jmcneill 	tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh,
    175  1.4  jmcneill 	    TEGRA_EHCI_HOSTPC1_DEVLC_REG,
    176  1.4  jmcneill 	    __SHIFTIN(TEGRA_EHCI_HOSTPC1_DEVLC_PTS_UTMI,
    177  1.4  jmcneill 		      TEGRA_EHCI_HOSTPC1_DEVLC_PTS),
    178  1.4  jmcneill 	    TEGRA_EHCI_HOSTPC1_DEVLC_PTS |
    179  1.4  jmcneill 	    TEGRA_EHCI_HOSTPC1_DEVLC_STS);
    180  1.4  jmcneill 
    181  1.4  jmcneill 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, TEGRA_EHCI_TXFILLTUNING_REG,
    182  1.4  jmcneill 	    __SHIFTIN(0x10, TEGRA_EHCI_TXFILLTUNING_TXFIFOTHRES));
    183  1.4  jmcneill }
    184  1.4  jmcneill 
    185  1.4  jmcneill static void
    186  1.4  jmcneill tegra_ehci_utmip_init(struct tegra_ehci_softc *sc)
    187  1.4  jmcneill {
    188  1.4  jmcneill 	bus_space_tag_t bst = sc->sc_bst;
    189  1.4  jmcneill 	bus_space_handle_t bsh = sc->sc_bsh;
    190  1.4  jmcneill 	int retry;
    191  1.4  jmcneill 
    192  1.4  jmcneill 	/* Put UTMIP PHY into reset before programming UTMIP config registers */
    193  1.4  jmcneill 	tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_SUSP_CTRL_REG,
    194  1.4  jmcneill 	    TEGRA_EHCI_SUSP_CTRL_UTMIP_RESET, 0);
    195  1.4  jmcneill 
    196  1.4  jmcneill 	/* Enable UTMIP PHY mode */
    197  1.4  jmcneill 	tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_SUSP_CTRL_REG,
    198  1.4  jmcneill 	    TEGRA_EHCI_SUSP_CTRL_UTMIP_PHY_ENB, 0);
    199  1.4  jmcneill 
    200  1.4  jmcneill 	/* Stop crystal clock */
    201  1.4  jmcneill 	tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_MISC_CFG1_REG,
    202  1.4  jmcneill 	    0, TEGRA_EHCI_UTMIP_MISC_CFG1_PHY_XTAL_CLOCKEN);
    203  1.4  jmcneill 	delay(1);
    204  1.4  jmcneill 
    205  1.4  jmcneill 	/* Clear session status */
    206  1.4  jmcneill 	tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_PHY_VBUS_SENSORS_REG,
    207  1.4  jmcneill 	    0,
    208  1.4  jmcneill 	    TEGRA_EHCI_PHY_VBUS_SENSORS_B_VLD_SW_VALUE |
    209  1.4  jmcneill 	    TEGRA_EHCI_PHY_VBUS_SENSORS_B_VLD_SW_EN);
    210  1.4  jmcneill 
    211  1.4  jmcneill 	/* PLL configuration */
    212  1.4  jmcneill 	tegra_car_utmip_init();
    213  1.4  jmcneill 
    214  1.4  jmcneill 	/* Transceiver configuration */
    215  1.4  jmcneill 	tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG0_REG,
    216  1.4  jmcneill 	    __SHIFTIN(4, TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP) |
    217  1.4  jmcneill 	    __SHIFTIN(3, TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP_MSB) |
    218  1.4  jmcneill 	    __SHIFTIN(8, TEGRA_EHCI_UTMIP_XCVR_CFG0_HSSLEW_MSB),
    219  1.4  jmcneill 	    TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP |
    220  1.4  jmcneill 	    TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP_MSB |
    221  1.4  jmcneill 	    TEGRA_EHCI_UTMIP_XCVR_CFG0_HSSLEW_MSB);
    222  1.4  jmcneill 	tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG1_REG,
    223  1.4  jmcneill 	    __SHIFTIN(7, TEGRA_EHCI_UTMIP_XCVR_CFG1_TERM_RANGE_ADJ),
    224  1.4  jmcneill 	    TEGRA_EHCI_UTMIP_XCVR_CFG1_TERM_RANGE_ADJ);
    225  1.4  jmcneill 
    226  1.4  jmcneill 	if (sc->sc_port == 0) {
    227  1.4  jmcneill 		tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BIAS_CFG0_REG,
    228  1.4  jmcneill 		    TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL_MSB |
    229  1.4  jmcneill 		    __SHIFTIN(2, TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL),
    230  1.4  jmcneill 		    TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL);
    231  1.4  jmcneill 	}
    232  1.4  jmcneill 
    233  1.4  jmcneill 	/* Misc config */
    234  1.4  jmcneill 	tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_MISC_CFG0_REG,
    235  1.4  jmcneill 	    0,
    236  1.4  jmcneill 	    TEGRA_EHCI_UTMIP_MISC_CFG0_SUSPEND_EXIT_ON_EDGE);
    237  1.4  jmcneill 
    238  1.4  jmcneill 	/* BIAS cell power down lag */
    239  1.4  jmcneill 	tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BIAS_CFG1_REG,
    240  1.4  jmcneill 	    __SHIFTIN(6, TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_COUNT),
    241  1.4  jmcneill 	    TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_COUNT);
    242  1.4  jmcneill 
    243  1.4  jmcneill 	/* Debounce config */
    244  1.4  jmcneill 	tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_REG,
    245  1.4  jmcneill 	    __SHIFTIN(0x73f4, TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_A),
    246  1.4  jmcneill 	    TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_A);
    247  1.4  jmcneill 
    248  1.4  jmcneill 	/* Transmit signal preamble config */
    249  1.4  jmcneill 	tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_TX_CFG0_REG,
    250  1.4  jmcneill 	    TEGRA_EHCI_UTMIP_TX_CFG0_FS_PREAMBLE_J, 0);
    251  1.4  jmcneill 
    252  1.4  jmcneill 	/* Power-down battery charger circuit */
    253  1.4  jmcneill 	tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BAT_CHRG_CFG0_REG,
    254  1.4  jmcneill 	    TEGRA_EHCI_UTMIP_BAT_CHRG_CFG0_PD_CHRG, 0);
    255  1.4  jmcneill 
    256  1.4  jmcneill 	/* Select low speed bias method */
    257  1.4  jmcneill 	tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG0_REG,
    258  1.4  jmcneill 	    0, TEGRA_EHCI_UTMIP_XCVR_CFG0_LSBIAS_SEL);
    259  1.4  jmcneill 
    260  1.4  jmcneill 	/* High speed receive config */
    261  1.4  jmcneill 	tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_HSRX_CFG0_REG,
    262  1.4  jmcneill 	    __SHIFTIN(17, TEGRA_EHCI_UTMIP_HSRX_CFG0_IDLE_WAIT) |
    263  1.4  jmcneill 	    __SHIFTIN(16, TEGRA_EHCI_UTMIP_HSRX_CFG0_ELASTIC_LIMIT),
    264  1.4  jmcneill 	    TEGRA_EHCI_UTMIP_HSRX_CFG0_IDLE_WAIT |
    265  1.4  jmcneill 	    TEGRA_EHCI_UTMIP_HSRX_CFG0_ELASTIC_LIMIT);
    266  1.4  jmcneill 	tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_HSRX_CFG1_REG,
    267  1.4  jmcneill 	    __SHIFTIN(9, TEGRA_EHCI_UTMIP_HSRX_CFG1_SYNC_START_DLY),
    268  1.4  jmcneill 	    TEGRA_EHCI_UTMIP_HSRX_CFG1_SYNC_START_DLY);
    269  1.4  jmcneill 
    270  1.4  jmcneill 	/* Start crystal clock */
    271  1.4  jmcneill 	delay(1);
    272  1.4  jmcneill 	tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_MISC_CFG1_REG,
    273  1.4  jmcneill 	    TEGRA_EHCI_UTMIP_MISC_CFG1_PHY_XTAL_CLOCKEN, 0);
    274  1.4  jmcneill 
    275  1.4  jmcneill 	/* Clear port PLL powerdown status */
    276  1.4  jmcneill 	tegra_car_utmip_enable(sc->sc_port);
    277  1.4  jmcneill 
    278  1.4  jmcneill 	/* Bring UTMIP PHY out of reset */
    279  1.4  jmcneill 	tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_SUSP_CTRL_REG,
    280  1.4  jmcneill 	    0, TEGRA_EHCI_SUSP_CTRL_UTMIP_RESET);
    281  1.4  jmcneill 	for (retry = 100000; retry > 0; retry--) {
    282  1.4  jmcneill 		const uint32_t susp = bus_space_read_4(bst, bsh,
    283  1.4  jmcneill 		    TEGRA_EHCI_SUSP_CTRL_REG);
    284  1.4  jmcneill 		if (susp & TEGRA_EHCI_SUSP_CTRL_PHY_CLK_VALID)
    285  1.4  jmcneill 			break;
    286  1.4  jmcneill 		delay(1);
    287  1.4  jmcneill 	}
    288  1.4  jmcneill 	if (retry == 0) {
    289  1.4  jmcneill 		aprint_error_dev(sc->sc.sc_dev, "PHY clock is not valid\n");
    290  1.4  jmcneill 		return;
    291  1.4  jmcneill 	}
    292  1.4  jmcneill 
    293  1.4  jmcneill 	/* Disable ICUSB transceiver */
    294  1.4  jmcneill 	tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_ICUSB_CTRL_REG,
    295  1.4  jmcneill 	    0,
    296  1.4  jmcneill 	    TEGRA_EHCI_ICUSB_CTRL_ENB1);
    297  1.4  jmcneill 
    298  1.4  jmcneill 	/* Power up UTMPI transceiver */
    299  1.4  jmcneill 	tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG0_REG,
    300  1.4  jmcneill 	    0,
    301  1.4  jmcneill 	    TEGRA_EHCI_UTMIP_XCVR_CFG0_PD_POWERDOWN |
    302  1.4  jmcneill 	    TEGRA_EHCI_UTMIP_XCVR_CFG0_PD2_POWERDOWN |
    303  1.4  jmcneill 	    TEGRA_EHCI_UTMIP_XCVR_CFG0_PDZI_POWERDOWN);
    304  1.4  jmcneill 	tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG1_REG,
    305  1.4  jmcneill 	    0,
    306  1.4  jmcneill 	    TEGRA_EHCI_UTMIP_XCVR_CFG1_PDDISC_POWERDOWN |
    307  1.4  jmcneill 	    TEGRA_EHCI_UTMIP_XCVR_CFG1_PDCHRP_POWERDOWN |
    308  1.4  jmcneill 	    TEGRA_EHCI_UTMIP_XCVR_CFG1_PDDR_POWERDOWN);
    309  1.4  jmcneill 
    310  1.4  jmcneill 	if (sc->sc_port == 0) {
    311  1.4  jmcneill 		tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BIAS_CFG0_REG,
    312  1.4  jmcneill 		    0, TEGRA_EHCI_UTMIP_BIAS_CFG0_BIASPD);
    313  1.4  jmcneill 		delay(25);
    314  1.4  jmcneill 		tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BIAS_CFG1_REG,
    315  1.4  jmcneill 		    0, TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_POWERDOWN);
    316  1.4  jmcneill 	}
    317  1.4  jmcneill }
    318  1.5     skrll 
    319  1.5     skrll 
    320  1.5     skrll static int
    321  1.5     skrll tegra_ehci_port_status(struct ehci_softc *sc, uint32_t v, int i)
    322  1.5     skrll {
    323  1.5     skrll 	bus_space_tag_t iot = sc->iot;
    324  1.5     skrll 	bus_space_handle_t ioh = sc->ioh;
    325  1.5     skrll 
    326  1.5     skrll 	i &= ~UPS_HIGH_SPEED;
    327  1.5     skrll 
    328  1.5     skrll 	uint32_t val = bus_space_read_4(iot, ioh,
    329  1.5     skrll 	    TEGRA_EHCI_HOSTPC1_DEVLC_REG);
    330  1.5     skrll 
    331  1.5     skrll 	switch (__SHIFTOUT(val, TEGRA_EHCI_HOSTPC1_DEVLC_PSPD)) {
    332  1.5     skrll 	case TEGRA_EHCI_HOSTPC1_DEVLC_PSPD_FS:
    333  1.5     skrll 		i |= UPS_FULL_SPEED;
    334  1.5     skrll 		break;
    335  1.5     skrll 	case TEGRA_EHCI_HOSTPC1_DEVLC_PSPD_LS:
    336  1.5     skrll 		i |= UPS_LOW_SPEED;
    337  1.5     skrll 		break;
    338  1.5     skrll 	case TEGRA_EHCI_HOSTPC1_DEVLC_PSPD_HS:
    339  1.5     skrll 	default:
    340  1.5     skrll 		i |= UPS_HIGH_SPEED;
    341  1.5     skrll 		break;
    342  1.5     skrll 	}
    343  1.5     skrll 	return i;
    344  1.5     skrll }
    345