tegra_ehci.c revision 1.9 1 1.9 jmcneill /* $NetBSD: tegra_ehci.c,v 1.9 2015/10/21 20:02:12 jmcneill Exp $ */
2 1.1 jmcneill
3 1.1 jmcneill /*-
4 1.1 jmcneill * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca>
5 1.1 jmcneill * All rights reserved.
6 1.1 jmcneill *
7 1.1 jmcneill * Redistribution and use in source and binary forms, with or without
8 1.1 jmcneill * modification, are permitted provided that the following conditions
9 1.1 jmcneill * are met:
10 1.1 jmcneill * 1. Redistributions of source code must retain the above copyright
11 1.1 jmcneill * notice, this list of conditions and the following disclaimer.
12 1.1 jmcneill * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 jmcneill * notice, this list of conditions and the following disclaimer in the
14 1.1 jmcneill * documentation and/or other materials provided with the distribution.
15 1.1 jmcneill *
16 1.1 jmcneill * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 1.1 jmcneill * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 1.1 jmcneill * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 1.1 jmcneill * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 1.1 jmcneill * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 1.1 jmcneill * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 1.1 jmcneill * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 1.1 jmcneill * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 1.1 jmcneill * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 1.1 jmcneill * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 1.1 jmcneill * SUCH DAMAGE.
27 1.1 jmcneill */
28 1.1 jmcneill
29 1.1 jmcneill #include "locators.h"
30 1.1 jmcneill
31 1.1 jmcneill #include <sys/cdefs.h>
32 1.9 jmcneill __KERNEL_RCSID(0, "$NetBSD: tegra_ehci.c,v 1.9 2015/10/21 20:02:12 jmcneill Exp $");
33 1.1 jmcneill
34 1.1 jmcneill #include <sys/param.h>
35 1.1 jmcneill #include <sys/bus.h>
36 1.1 jmcneill #include <sys/device.h>
37 1.1 jmcneill #include <sys/intr.h>
38 1.1 jmcneill #include <sys/systm.h>
39 1.1 jmcneill #include <sys/kernel.h>
40 1.1 jmcneill
41 1.1 jmcneill #include <dev/usb/usb.h>
42 1.1 jmcneill #include <dev/usb/usbdi.h>
43 1.1 jmcneill #include <dev/usb/usbdivar.h>
44 1.1 jmcneill #include <dev/usb/usb_mem.h>
45 1.1 jmcneill #include <dev/usb/ehcireg.h>
46 1.1 jmcneill #include <dev/usb/ehcivar.h>
47 1.1 jmcneill
48 1.1 jmcneill #include <arm/nvidia/tegra_var.h>
49 1.9 jmcneill #include <arm/nvidia/tegra_usbreg.h>
50 1.1 jmcneill
51 1.2 jmcneill #define TEGRA_EHCI_REG_OFFSET 0x100
52 1.2 jmcneill
53 1.1 jmcneill static int tegra_ehci_match(device_t, cfdata_t, void *);
54 1.1 jmcneill static void tegra_ehci_attach(device_t, device_t, void *);
55 1.1 jmcneill
56 1.4 jmcneill static void tegra_ehci_init(struct ehci_softc *);
57 1.4 jmcneill
58 1.1 jmcneill struct tegra_ehci_softc {
59 1.1 jmcneill struct ehci_softc sc;
60 1.4 jmcneill bus_space_tag_t sc_bst;
61 1.4 jmcneill bus_space_handle_t sc_bsh;
62 1.1 jmcneill void *sc_ih;
63 1.4 jmcneill u_int sc_port;
64 1.1 jmcneill };
65 1.1 jmcneill
66 1.5 skrll static int tegra_ehci_port_status(struct ehci_softc *sc, uint32_t v,
67 1.5 skrll int i);
68 1.4 jmcneill
69 1.1 jmcneill CFATTACH_DECL2_NEW(tegra_ehci, sizeof(struct tegra_ehci_softc),
70 1.1 jmcneill tegra_ehci_match, tegra_ehci_attach, NULL,
71 1.1 jmcneill ehci_activate, NULL, ehci_childdet);
72 1.1 jmcneill
73 1.1 jmcneill static int
74 1.1 jmcneill tegra_ehci_match(device_t parent, cfdata_t cf, void *aux)
75 1.1 jmcneill {
76 1.1 jmcneill return 1;
77 1.1 jmcneill }
78 1.1 jmcneill
79 1.1 jmcneill static void
80 1.1 jmcneill tegra_ehci_attach(device_t parent, device_t self, void *aux)
81 1.1 jmcneill {
82 1.1 jmcneill struct tegra_ehci_softc * const sc = device_private(self);
83 1.1 jmcneill struct tegraio_attach_args * const tio = aux;
84 1.1 jmcneill const struct tegra_locators * const loc = &tio->tio_loc;
85 1.1 jmcneill int error;
86 1.1 jmcneill
87 1.4 jmcneill sc->sc_bst = tio->tio_bst;
88 1.4 jmcneill bus_space_subregion(tio->tio_bst, tio->tio_bsh,
89 1.4 jmcneill loc->loc_offset, loc->loc_size, &sc->sc_bsh);
90 1.4 jmcneill sc->sc_port = loc->loc_port;
91 1.4 jmcneill
92 1.1 jmcneill sc->sc.sc_dev = self;
93 1.1 jmcneill sc->sc.sc_bus.hci_private = &sc->sc;
94 1.1 jmcneill sc->sc.sc_bus.dmatag = tio->tio_dmat;
95 1.1 jmcneill sc->sc.sc_bus.usbrev = USBREV_2_0;
96 1.5 skrll sc->sc.sc_ncomp = 0;
97 1.5 skrll sc->sc.sc_flags = EHCIF_ETTF;
98 1.1 jmcneill sc->sc.sc_id_vendor = 0x10de;
99 1.1 jmcneill strlcpy(sc->sc.sc_vendor, "Tegra", sizeof(sc->sc.sc_vendor));
100 1.1 jmcneill sc->sc.sc_size = loc->loc_size;
101 1.1 jmcneill sc->sc.iot = tio->tio_bst;
102 1.1 jmcneill bus_space_subregion(tio->tio_bst, tio->tio_bsh,
103 1.2 jmcneill loc->loc_offset + TEGRA_EHCI_REG_OFFSET,
104 1.2 jmcneill loc->loc_size - TEGRA_EHCI_REG_OFFSET, &sc->sc.ioh);
105 1.4 jmcneill sc->sc.sc_vendor_init = tegra_ehci_init;
106 1.6 skrll sc->sc.sc_vendor_port_status = tegra_ehci_port_status;
107 1.1 jmcneill
108 1.1 jmcneill aprint_naive("\n");
109 1.1 jmcneill aprint_normal(": USB%d\n", loc->loc_port + 1);
110 1.1 jmcneill
111 1.1 jmcneill sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH);
112 1.1 jmcneill
113 1.1 jmcneill sc->sc_ih = intr_establish(loc->loc_intr, IPL_USB, IST_LEVEL,
114 1.1 jmcneill ehci_intr, &sc->sc);
115 1.1 jmcneill if (sc->sc_ih == NULL) {
116 1.1 jmcneill aprint_error_dev(self, "couldn't establish interrupt %d\n",
117 1.1 jmcneill loc->loc_intr);
118 1.1 jmcneill return;
119 1.1 jmcneill }
120 1.1 jmcneill aprint_normal_dev(self, "interrupting on irq %d\n", loc->loc_intr);
121 1.1 jmcneill
122 1.1 jmcneill error = ehci_init(&sc->sc);
123 1.1 jmcneill if (error != USBD_NORMAL_COMPLETION) {
124 1.1 jmcneill aprint_error_dev(self, "init failed, error = %d\n", error);
125 1.1 jmcneill return;
126 1.1 jmcneill }
127 1.1 jmcneill
128 1.1 jmcneill sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint);
129 1.1 jmcneill }
130 1.4 jmcneill
131 1.4 jmcneill static void
132 1.4 jmcneill tegra_ehci_init(struct ehci_softc *esc)
133 1.4 jmcneill {
134 1.4 jmcneill struct tegra_ehci_softc * const sc = device_private(esc->sc_dev);
135 1.4 jmcneill uint32_t usbmode;
136 1.4 jmcneill
137 1.4 jmcneill usbmode = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
138 1.4 jmcneill TEGRA_EHCI_USBMODE_REG);
139 1.4 jmcneill
140 1.4 jmcneill const u_int cm = __SHIFTOUT(usbmode, TEGRA_EHCI_USBMODE_CM);
141 1.4 jmcneill if (cm != TEGRA_EHCI_USBMODE_CM_HOST) {
142 1.4 jmcneill aprint_verbose_dev(esc->sc_dev, "switching to host mode\n");
143 1.4 jmcneill usbmode &= ~TEGRA_EHCI_USBMODE_CM;
144 1.4 jmcneill usbmode |= __SHIFTIN(TEGRA_EHCI_USBMODE_CM_HOST,
145 1.4 jmcneill TEGRA_EHCI_USBMODE_CM);
146 1.4 jmcneill bus_space_write_4(sc->sc_bst, sc->sc_bsh,
147 1.4 jmcneill TEGRA_EHCI_USBMODE_REG, usbmode);
148 1.4 jmcneill }
149 1.4 jmcneill
150 1.4 jmcneill /* Parallel transceiver select */
151 1.4 jmcneill tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh,
152 1.4 jmcneill TEGRA_EHCI_HOSTPC1_DEVLC_REG,
153 1.4 jmcneill __SHIFTIN(TEGRA_EHCI_HOSTPC1_DEVLC_PTS_UTMI,
154 1.4 jmcneill TEGRA_EHCI_HOSTPC1_DEVLC_PTS),
155 1.4 jmcneill TEGRA_EHCI_HOSTPC1_DEVLC_PTS |
156 1.4 jmcneill TEGRA_EHCI_HOSTPC1_DEVLC_STS);
157 1.4 jmcneill
158 1.4 jmcneill bus_space_write_4(sc->sc_bst, sc->sc_bsh, TEGRA_EHCI_TXFILLTUNING_REG,
159 1.4 jmcneill __SHIFTIN(0x10, TEGRA_EHCI_TXFILLTUNING_TXFIFOTHRES));
160 1.4 jmcneill }
161 1.4 jmcneill
162 1.5 skrll static int
163 1.6 skrll tegra_ehci_port_status(struct ehci_softc *ehci_sc, uint32_t v, int i)
164 1.7 skrll {
165 1.6 skrll struct tegra_ehci_softc * const sc = device_private(ehci_sc->sc_dev);
166 1.6 skrll bus_space_tag_t iot = sc->sc_bst;
167 1.6 skrll bus_space_handle_t ioh = sc->sc_bsh;
168 1.7 skrll
169 1.6 skrll i &= ~(UPS_HIGH_SPEED|UPS_LOW_SPEED);
170 1.5 skrll
171 1.5 skrll uint32_t val = bus_space_read_4(iot, ioh,
172 1.5 skrll TEGRA_EHCI_HOSTPC1_DEVLC_REG);
173 1.5 skrll
174 1.5 skrll switch (__SHIFTOUT(val, TEGRA_EHCI_HOSTPC1_DEVLC_PSPD)) {
175 1.5 skrll case TEGRA_EHCI_HOSTPC1_DEVLC_PSPD_FS:
176 1.5 skrll i |= UPS_FULL_SPEED;
177 1.5 skrll break;
178 1.5 skrll case TEGRA_EHCI_HOSTPC1_DEVLC_PSPD_LS:
179 1.5 skrll i |= UPS_LOW_SPEED;
180 1.5 skrll break;
181 1.5 skrll case TEGRA_EHCI_HOSTPC1_DEVLC_PSPD_HS:
182 1.5 skrll default:
183 1.5 skrll i |= UPS_HIGH_SPEED;
184 1.5 skrll break;
185 1.5 skrll }
186 1.5 skrll return i;
187 1.5 skrll }
188