tegra_ehci.c revision 1.11
1 /* $NetBSD: tegra_ehci.c,v 1.11 2015/12/13 17:39:19 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_ehci.c,v 1.11 2015/12/13 17:39:19 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 39 #include <dev/usb/usb.h> 40 #include <dev/usb/usbdi.h> 41 #include <dev/usb/usbdivar.h> 42 #include <dev/usb/usb_mem.h> 43 #include <dev/usb/ehcireg.h> 44 #include <dev/usb/ehcivar.h> 45 46 #include <arm/nvidia/tegra_reg.h> 47 #include <arm/nvidia/tegra_var.h> 48 #include <arm/nvidia/tegra_usbreg.h> 49 50 #include <dev/fdt/fdtvar.h> 51 52 /* XXX */ 53 static int 54 tegra_ehci_addr2port(bus_addr_t addr) 55 { 56 switch (addr) { 57 case TEGRA_AHB_A2_BASE + TEGRA_USB1_OFFSET: 58 return 0; 59 case TEGRA_AHB_A2_BASE + TEGRA_USB2_OFFSET: 60 return 1; 61 case TEGRA_AHB_A2_BASE + TEGRA_USB3_OFFSET: 62 return 2; 63 default: 64 return -1; 65 } 66 } 67 68 #define TEGRA_EHCI_REG_OFFSET 0x100 69 70 static int tegra_ehci_match(device_t, cfdata_t, void *); 71 static void tegra_ehci_attach(device_t, device_t, void *); 72 73 static void tegra_ehci_init(struct ehci_softc *); 74 75 struct tegra_ehci_softc { 76 struct ehci_softc sc; 77 bus_space_tag_t sc_bst; 78 bus_space_handle_t sc_bsh; 79 void *sc_ih; 80 u_int sc_port; 81 }; 82 83 static int tegra_ehci_port_status(struct ehci_softc *sc, uint32_t v, 84 int i); 85 86 CFATTACH_DECL2_NEW(tegra_ehci, sizeof(struct tegra_ehci_softc), 87 tegra_ehci_match, tegra_ehci_attach, NULL, 88 ehci_activate, NULL, ehci_childdet); 89 90 static int 91 tegra_ehci_match(device_t parent, cfdata_t cf, void *aux) 92 { 93 const char * const compatible[] = { "nvidia,tegra124-ehci", NULL }; 94 struct fdt_attach_args * const faa = aux; 95 96 return of_match_compatible(faa->faa_phandle, compatible); 97 } 98 99 static void 100 tegra_ehci_attach(device_t parent, device_t self, void *aux) 101 { 102 struct tegra_ehci_softc * const sc = device_private(self); 103 struct fdt_attach_args * const faa = aux; 104 char intrstr[128]; 105 bus_addr_t addr; 106 bus_size_t size; 107 int error; 108 109 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 110 aprint_error(": couldn't get registers\n"); 111 return; 112 } 113 114 sc->sc_bst = faa->faa_bst; 115 sc->sc_port = tegra_ehci_addr2port(addr); 116 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 117 if (error) { 118 aprint_error(": couldn't map USB%d\n", sc->sc_port + 1); 119 return; 120 } 121 122 sc->sc.sc_dev = self; 123 sc->sc.sc_bus.hci_private = &sc->sc; 124 sc->sc.sc_bus.dmatag = faa->faa_dmat; 125 sc->sc.sc_bus.usbrev = USBREV_2_0; 126 sc->sc.sc_ncomp = 0; 127 sc->sc.sc_flags = EHCIF_ETTF; 128 sc->sc.sc_id_vendor = 0x10de; 129 strlcpy(sc->sc.sc_vendor, "Tegra", sizeof(sc->sc.sc_vendor)); 130 sc->sc.sc_size = size - TEGRA_EHCI_REG_OFFSET; 131 sc->sc.iot = sc->sc_bst; 132 bus_space_subregion(sc->sc_bst, sc->sc_bsh, TEGRA_EHCI_REG_OFFSET, 133 sc->sc.sc_size, &sc->sc.ioh); 134 sc->sc.sc_vendor_init = tegra_ehci_init; 135 sc->sc.sc_vendor_port_status = tegra_ehci_port_status; 136 137 aprint_naive("\n"); 138 aprint_normal(": USB%d\n", sc->sc_port + 1); 139 140 sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH); 141 142 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) { 143 aprint_error_dev(self, "failed to decode interrupt\n"); 144 return; 145 } 146 147 sc->sc_ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_USB, 0, 148 ehci_intr, &sc->sc); 149 if (sc->sc_ih == NULL) { 150 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 151 intrstr); 152 return; 153 } 154 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 155 156 error = ehci_init(&sc->sc); 157 if (error != USBD_NORMAL_COMPLETION) { 158 aprint_error_dev(self, "init failed, error = %d\n", error); 159 return; 160 } 161 162 sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint); 163 } 164 165 static void 166 tegra_ehci_init(struct ehci_softc *esc) 167 { 168 struct tegra_ehci_softc * const sc = device_private(esc->sc_dev); 169 uint32_t usbmode; 170 171 usbmode = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 172 TEGRA_EHCI_USBMODE_REG); 173 174 const u_int cm = __SHIFTOUT(usbmode, TEGRA_EHCI_USBMODE_CM); 175 if (cm != TEGRA_EHCI_USBMODE_CM_HOST) { 176 aprint_verbose_dev(esc->sc_dev, "switching to host mode\n"); 177 usbmode &= ~TEGRA_EHCI_USBMODE_CM; 178 usbmode |= __SHIFTIN(TEGRA_EHCI_USBMODE_CM_HOST, 179 TEGRA_EHCI_USBMODE_CM); 180 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 181 TEGRA_EHCI_USBMODE_REG, usbmode); 182 } 183 184 /* Parallel transceiver select */ 185 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, 186 TEGRA_EHCI_HOSTPC1_DEVLC_REG, 187 __SHIFTIN(TEGRA_EHCI_HOSTPC1_DEVLC_PTS_UTMI, 188 TEGRA_EHCI_HOSTPC1_DEVLC_PTS), 189 TEGRA_EHCI_HOSTPC1_DEVLC_PTS | 190 TEGRA_EHCI_HOSTPC1_DEVLC_STS); 191 192 bus_space_write_4(sc->sc_bst, sc->sc_bsh, TEGRA_EHCI_TXFILLTUNING_REG, 193 __SHIFTIN(0x10, TEGRA_EHCI_TXFILLTUNING_TXFIFOTHRES)); 194 } 195 196 static int 197 tegra_ehci_port_status(struct ehci_softc *ehci_sc, uint32_t v, int i) 198 { 199 struct tegra_ehci_softc * const sc = device_private(ehci_sc->sc_dev); 200 bus_space_tag_t iot = sc->sc_bst; 201 bus_space_handle_t ioh = sc->sc_bsh; 202 203 i &= ~(UPS_HIGH_SPEED|UPS_LOW_SPEED); 204 205 uint32_t val = bus_space_read_4(iot, ioh, 206 TEGRA_EHCI_HOSTPC1_DEVLC_REG); 207 208 switch (__SHIFTOUT(val, TEGRA_EHCI_HOSTPC1_DEVLC_PSPD)) { 209 case TEGRA_EHCI_HOSTPC1_DEVLC_PSPD_FS: 210 i |= UPS_FULL_SPEED; 211 break; 212 case TEGRA_EHCI_HOSTPC1_DEVLC_PSPD_LS: 213 i |= UPS_LOW_SPEED; 214 break; 215 case TEGRA_EHCI_HOSTPC1_DEVLC_PSPD_HS: 216 default: 217 i |= UPS_HIGH_SPEED; 218 break; 219 } 220 return i; 221 } 222
Indexes created Wed Sep 24 05:09:52 GMT 2025