tegra_ehci.c revision 1.15.10.1
1 /* $NetBSD: tegra_ehci.c,v 1.15.10.1 2018/04/16 01:59:53 pgoyette Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_ehci.c,v 1.15.10.1 2018/04/16 01:59:53 pgoyette Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 39 #include <dev/usb/usb.h> 40 #include <dev/usb/usbdi.h> 41 #include <dev/usb/usbdivar.h> 42 #include <dev/usb/usb_mem.h> 43 #include <dev/usb/ehcireg.h> 44 #include <dev/usb/ehcivar.h> 45 46 #include <arm/nvidia/tegra_reg.h> 47 #include <arm/nvidia/tegra_var.h> 48 #include <arm/nvidia/tegra_usbreg.h> 49 50 #include <dev/fdt/fdtvar.h> 51 52 #define TEGRA_EHCI_REG_OFFSET 0x100 53 54 static int tegra_ehci_match(device_t, cfdata_t, void *); 55 static void tegra_ehci_attach(device_t, device_t, void *); 56 57 static void tegra_ehci_init(struct ehci_softc *); 58 59 struct tegra_ehci_softc { 60 struct ehci_softc sc; 61 bus_space_tag_t sc_bst; 62 bus_space_handle_t sc_bsh; 63 void *sc_ih; 64 }; 65 66 static int tegra_ehci_port_status(struct ehci_softc *sc, uint32_t v, 67 int i); 68 69 CFATTACH_DECL2_NEW(tegra_ehci, sizeof(struct tegra_ehci_softc), 70 tegra_ehci_match, tegra_ehci_attach, NULL, 71 ehci_activate, NULL, ehci_childdet); 72 73 static int 74 tegra_ehci_match(device_t parent, cfdata_t cf, void *aux) 75 { 76 const char * const compatible[] = { 77 "nvidia,tegra210-ehci", 78 "nvidia,tegra124-ehci", 79 "nvidia,tegra30-ehci", 80 NULL 81 }; 82 struct fdt_attach_args * const faa = aux; 83 84 return of_match_compatible(faa->faa_phandle, compatible); 85 } 86 87 static void 88 tegra_ehci_attach(device_t parent, device_t self, void *aux) 89 { 90 struct tegra_ehci_softc * const sc = device_private(self); 91 struct fdt_attach_args * const faa = aux; 92 char intrstr[128]; 93 bus_addr_t addr; 94 bus_size_t size; 95 int error; 96 97 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 98 aprint_error(": couldn't get registers\n"); 99 return; 100 } 101 102 sc->sc_bst = faa->faa_bst; 103 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 104 if (error) { 105 aprint_error(": couldn't map USB\n"); 106 return; 107 } 108 109 sc->sc.sc_dev = self; 110 sc->sc.sc_bus.ub_hcpriv = &sc->sc; 111 sc->sc.sc_bus.ub_dmatag = faa->faa_dmat; 112 sc->sc.sc_bus.ub_revision = USBREV_2_0; 113 sc->sc.sc_ncomp = 0; 114 sc->sc.sc_flags = EHCIF_ETTF; 115 sc->sc.sc_size = size - TEGRA_EHCI_REG_OFFSET; 116 sc->sc.iot = sc->sc_bst; 117 bus_space_subregion(sc->sc_bst, sc->sc_bsh, TEGRA_EHCI_REG_OFFSET, 118 sc->sc.sc_size, &sc->sc.ioh); 119 sc->sc.sc_vendor_init = tegra_ehci_init; 120 sc->sc.sc_vendor_port_status = tegra_ehci_port_status; 121 122 aprint_naive("\n"); 123 aprint_normal(": USB\n"); 124 125 sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH); 126 127 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) { 128 aprint_error_dev(self, "failed to decode interrupt\n"); 129 return; 130 } 131 132 sc->sc_ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_USB, 133 FDT_INTR_MPSAFE, ehci_intr, &sc->sc); 134 if (sc->sc_ih == NULL) { 135 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 136 intrstr); 137 return; 138 } 139 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 140 141 error = ehci_init(&sc->sc); 142 if (error) { 143 aprint_error_dev(self, "init failed, error = %d\n", error); 144 return; 145 } 146 147 sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint); 148 } 149 150 static void 151 tegra_ehci_init(struct ehci_softc *esc) 152 { 153 struct tegra_ehci_softc * const sc = device_private(esc->sc_dev); 154 uint32_t usbmode; 155 156 usbmode = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 157 TEGRA_EHCI_USBMODE_REG); 158 159 const u_int cm = __SHIFTOUT(usbmode, TEGRA_EHCI_USBMODE_CM); 160 if (cm != TEGRA_EHCI_USBMODE_CM_HOST) { 161 aprint_verbose_dev(esc->sc_dev, "switching to host mode\n"); 162 usbmode &= ~TEGRA_EHCI_USBMODE_CM; 163 usbmode |= __SHIFTIN(TEGRA_EHCI_USBMODE_CM_HOST, 164 TEGRA_EHCI_USBMODE_CM); 165 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 166 TEGRA_EHCI_USBMODE_REG, usbmode); 167 } 168 169 /* Parallel transceiver select */ 170 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, 171 TEGRA_EHCI_HOSTPC1_DEVLC_REG, 172 __SHIFTIN(TEGRA_EHCI_HOSTPC1_DEVLC_PTS_UTMI, 173 TEGRA_EHCI_HOSTPC1_DEVLC_PTS), 174 TEGRA_EHCI_HOSTPC1_DEVLC_PTS | 175 TEGRA_EHCI_HOSTPC1_DEVLC_STS); 176 177 bus_space_write_4(sc->sc_bst, sc->sc_bsh, TEGRA_EHCI_TXFILLTUNING_REG, 178 __SHIFTIN(0x10, TEGRA_EHCI_TXFILLTUNING_TXFIFOTHRES)); 179 } 180 181 static int 182 tegra_ehci_port_status(struct ehci_softc *ehci_sc, uint32_t v, int i) 183 { 184 struct tegra_ehci_softc * const sc = device_private(ehci_sc->sc_dev); 185 bus_space_tag_t iot = sc->sc_bst; 186 bus_space_handle_t ioh = sc->sc_bsh; 187 188 i &= ~(UPS_HIGH_SPEED|UPS_LOW_SPEED); 189 190 uint32_t val = bus_space_read_4(iot, ioh, 191 TEGRA_EHCI_HOSTPC1_DEVLC_REG); 192 193 switch (__SHIFTOUT(val, TEGRA_EHCI_HOSTPC1_DEVLC_PSPD)) { 194 case TEGRA_EHCI_HOSTPC1_DEVLC_PSPD_FS: 195 i |= UPS_FULL_SPEED; 196 break; 197 case TEGRA_EHCI_HOSTPC1_DEVLC_PSPD_LS: 198 i |= UPS_LOW_SPEED; 199 break; 200 case TEGRA_EHCI_HOSTPC1_DEVLC_PSPD_HS: 201 default: 202 i |= UPS_HIGH_SPEED; 203 break; 204 } 205 return i; 206 } 207
Indexes created Wed Oct 15 16:09:53 GMT 2025