tegra_ehci.c revision 1.7
1 /* $NetBSD: tegra_ehci.c,v 1.7 2015/05/22 06:27:17 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "locators.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: tegra_ehci.c,v 1.7 2015/05/22 06:27:17 skrll Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 41 #include <dev/usb/usb.h> 42 #include <dev/usb/usbdi.h> 43 #include <dev/usb/usbdivar.h> 44 #include <dev/usb/usb_mem.h> 45 #include <dev/usb/ehcireg.h> 46 #include <dev/usb/ehcivar.h> 47 48 #include <arm/nvidia/tegra_var.h> 49 #include <arm/nvidia/tegra_ehcireg.h> 50 51 #define TEGRA_EHCI_REG_OFFSET 0x100 52 53 static int tegra_ehci_match(device_t, cfdata_t, void *); 54 static void tegra_ehci_attach(device_t, device_t, void *); 55 56 static void tegra_ehci_init(struct ehci_softc *); 57 58 struct tegra_ehci_softc { 59 struct ehci_softc sc; 60 bus_space_tag_t sc_bst; 61 bus_space_handle_t sc_bsh; 62 void *sc_ih; 63 u_int sc_port; 64 65 struct tegra_gpio_pin *sc_pin_vbus; 66 }; 67 68 static void tegra_ehci_utmip_init(struct tegra_ehci_softc *); 69 static int tegra_ehci_port_status(struct ehci_softc *sc, uint32_t v, 70 int i); 71 72 CFATTACH_DECL2_NEW(tegra_ehci, sizeof(struct tegra_ehci_softc), 73 tegra_ehci_match, tegra_ehci_attach, NULL, 74 ehci_activate, NULL, ehci_childdet); 75 76 static int 77 tegra_ehci_match(device_t parent, cfdata_t cf, void *aux) 78 { 79 return 1; 80 } 81 82 static void 83 tegra_ehci_attach(device_t parent, device_t self, void *aux) 84 { 85 struct tegra_ehci_softc * const sc = device_private(self); 86 struct tegraio_attach_args * const tio = aux; 87 const struct tegra_locators * const loc = &tio->tio_loc; 88 prop_dictionary_t prop = device_properties(self); 89 const char *pin; 90 int error; 91 92 sc->sc_bst = tio->tio_bst; 93 bus_space_subregion(tio->tio_bst, tio->tio_bsh, 94 loc->loc_offset, loc->loc_size, &sc->sc_bsh); 95 sc->sc_port = loc->loc_port; 96 97 sc->sc.sc_dev = self; 98 sc->sc.sc_bus.hci_private = &sc->sc; 99 sc->sc.sc_bus.dmatag = tio->tio_dmat; 100 sc->sc.sc_bus.usbrev = USBREV_2_0; 101 sc->sc.sc_ncomp = 0; 102 sc->sc.sc_flags = EHCIF_ETTF; 103 sc->sc.sc_id_vendor = 0x10de; 104 strlcpy(sc->sc.sc_vendor, "Tegra", sizeof(sc->sc.sc_vendor)); 105 sc->sc.sc_size = loc->loc_size; 106 sc->sc.iot = tio->tio_bst; 107 bus_space_subregion(tio->tio_bst, tio->tio_bsh, 108 loc->loc_offset + TEGRA_EHCI_REG_OFFSET, 109 loc->loc_size - TEGRA_EHCI_REG_OFFSET, &sc->sc.ioh); 110 sc->sc.sc_vendor_init = tegra_ehci_init; 111 sc->sc.sc_vendor_port_status = tegra_ehci_port_status; 112 113 aprint_naive("\n"); 114 aprint_normal(": USB%d\n", loc->loc_port + 1); 115 116 tegra_car_periph_usb_enable(sc->sc_port); 117 delay(2); 118 119 tegra_ehci_utmip_init(sc); 120 121 if (prop_dictionary_get_cstring_nocopy(prop, "vbus-gpio", &pin)) { 122 const uint32_t v = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 123 TEGRA_EHCI_PHY_VBUS_SENSORS_REG); 124 if ((v & TEGRA_EHCI_PHY_VBUS_SENSORS_A_VBUS_VLD_STS) == 0) { 125 sc->sc_pin_vbus = tegra_gpio_acquire(pin, 126 GPIO_PIN_OUTPUT | GPIO_PIN_OPENDRAIN); 127 if (sc->sc_pin_vbus) 128 tegra_gpio_write(sc->sc_pin_vbus, 1); 129 } else { 130 aprint_normal_dev(self, "VBUS input active\n"); 131 } 132 } 133 134 sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH); 135 136 sc->sc_ih = intr_establish(loc->loc_intr, IPL_USB, IST_LEVEL, 137 ehci_intr, &sc->sc); 138 if (sc->sc_ih == NULL) { 139 aprint_error_dev(self, "couldn't establish interrupt %d\n", 140 loc->loc_intr); 141 return; 142 } 143 aprint_normal_dev(self, "interrupting on irq %d\n", loc->loc_intr); 144 145 error = ehci_init(&sc->sc); 146 if (error != USBD_NORMAL_COMPLETION) { 147 aprint_error_dev(self, "init failed, error = %d\n", error); 148 return; 149 } 150 151 sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint); 152 } 153 154 static void 155 tegra_ehci_init(struct ehci_softc *esc) 156 { 157 struct tegra_ehci_softc * const sc = device_private(esc->sc_dev); 158 uint32_t usbmode; 159 160 usbmode = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 161 TEGRA_EHCI_USBMODE_REG); 162 163 const u_int cm = __SHIFTOUT(usbmode, TEGRA_EHCI_USBMODE_CM); 164 if (cm != TEGRA_EHCI_USBMODE_CM_HOST) { 165 aprint_verbose_dev(esc->sc_dev, "switching to host mode\n"); 166 usbmode &= ~TEGRA_EHCI_USBMODE_CM; 167 usbmode |= __SHIFTIN(TEGRA_EHCI_USBMODE_CM_HOST, 168 TEGRA_EHCI_USBMODE_CM); 169 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 170 TEGRA_EHCI_USBMODE_REG, usbmode); 171 } 172 173 /* Parallel transceiver select */ 174 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, 175 TEGRA_EHCI_HOSTPC1_DEVLC_REG, 176 __SHIFTIN(TEGRA_EHCI_HOSTPC1_DEVLC_PTS_UTMI, 177 TEGRA_EHCI_HOSTPC1_DEVLC_PTS), 178 TEGRA_EHCI_HOSTPC1_DEVLC_PTS | 179 TEGRA_EHCI_HOSTPC1_DEVLC_STS); 180 181 bus_space_write_4(sc->sc_bst, sc->sc_bsh, TEGRA_EHCI_TXFILLTUNING_REG, 182 __SHIFTIN(0x10, TEGRA_EHCI_TXFILLTUNING_TXFIFOTHRES)); 183 } 184 185 static void 186 tegra_ehci_utmip_init(struct tegra_ehci_softc *sc) 187 { 188 bus_space_tag_t bst = sc->sc_bst; 189 bus_space_handle_t bsh = sc->sc_bsh; 190 int retry; 191 192 /* Put UTMIP PHY into reset before programming UTMIP config registers */ 193 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_SUSP_CTRL_REG, 194 TEGRA_EHCI_SUSP_CTRL_UTMIP_RESET, 0); 195 196 /* Enable UTMIP PHY mode */ 197 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_SUSP_CTRL_REG, 198 TEGRA_EHCI_SUSP_CTRL_UTMIP_PHY_ENB, 0); 199 200 /* Stop crystal clock */ 201 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_MISC_CFG1_REG, 202 0, TEGRA_EHCI_UTMIP_MISC_CFG1_PHY_XTAL_CLOCKEN); 203 delay(1); 204 205 /* Clear session status */ 206 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_PHY_VBUS_SENSORS_REG, 207 0, 208 TEGRA_EHCI_PHY_VBUS_SENSORS_B_VLD_SW_VALUE | 209 TEGRA_EHCI_PHY_VBUS_SENSORS_B_VLD_SW_EN); 210 211 /* PLL configuration */ 212 tegra_car_utmip_init(); 213 214 /* Transceiver configuration */ 215 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG0_REG, 216 __SHIFTIN(4, TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP) | 217 __SHIFTIN(3, TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP_MSB) | 218 __SHIFTIN(8, TEGRA_EHCI_UTMIP_XCVR_CFG0_HSSLEW_MSB), 219 TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP | 220 TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP_MSB | 221 TEGRA_EHCI_UTMIP_XCVR_CFG0_HSSLEW_MSB); 222 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG1_REG, 223 __SHIFTIN(7, TEGRA_EHCI_UTMIP_XCVR_CFG1_TERM_RANGE_ADJ), 224 TEGRA_EHCI_UTMIP_XCVR_CFG1_TERM_RANGE_ADJ); 225 226 if (sc->sc_port == 0) { 227 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BIAS_CFG0_REG, 228 TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL_MSB | 229 __SHIFTIN(2, TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL), 230 TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL); 231 } 232 233 /* Misc config */ 234 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_MISC_CFG0_REG, 235 0, 236 TEGRA_EHCI_UTMIP_MISC_CFG0_SUSPEND_EXIT_ON_EDGE); 237 238 /* BIAS cell power down lag */ 239 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BIAS_CFG1_REG, 240 __SHIFTIN(6, TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_COUNT), 241 TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_COUNT); 242 243 /* Debounce config */ 244 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_REG, 245 __SHIFTIN(0x73f4, TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_A), 246 TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_A); 247 248 /* Transmit signal preamble config */ 249 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_TX_CFG0_REG, 250 TEGRA_EHCI_UTMIP_TX_CFG0_FS_PREAMBLE_J, 0); 251 252 /* Power-down battery charger circuit */ 253 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BAT_CHRG_CFG0_REG, 254 TEGRA_EHCI_UTMIP_BAT_CHRG_CFG0_PD_CHRG, 0); 255 256 /* Select low speed bias method */ 257 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG0_REG, 258 0, TEGRA_EHCI_UTMIP_XCVR_CFG0_LSBIAS_SEL); 259 260 /* High speed receive config */ 261 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_HSRX_CFG0_REG, 262 __SHIFTIN(17, TEGRA_EHCI_UTMIP_HSRX_CFG0_IDLE_WAIT) | 263 __SHIFTIN(16, TEGRA_EHCI_UTMIP_HSRX_CFG0_ELASTIC_LIMIT), 264 TEGRA_EHCI_UTMIP_HSRX_CFG0_IDLE_WAIT | 265 TEGRA_EHCI_UTMIP_HSRX_CFG0_ELASTIC_LIMIT); 266 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_HSRX_CFG1_REG, 267 __SHIFTIN(9, TEGRA_EHCI_UTMIP_HSRX_CFG1_SYNC_START_DLY), 268 TEGRA_EHCI_UTMIP_HSRX_CFG1_SYNC_START_DLY); 269 270 /* Start crystal clock */ 271 delay(1); 272 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_MISC_CFG1_REG, 273 TEGRA_EHCI_UTMIP_MISC_CFG1_PHY_XTAL_CLOCKEN, 0); 274 275 /* Clear port PLL powerdown status */ 276 tegra_car_utmip_enable(sc->sc_port); 277 278 /* Bring UTMIP PHY out of reset */ 279 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_SUSP_CTRL_REG, 280 0, TEGRA_EHCI_SUSP_CTRL_UTMIP_RESET); 281 for (retry = 100000; retry > 0; retry--) { 282 const uint32_t susp = bus_space_read_4(bst, bsh, 283 TEGRA_EHCI_SUSP_CTRL_REG); 284 if (susp & TEGRA_EHCI_SUSP_CTRL_PHY_CLK_VALID) 285 break; 286 delay(1); 287 } 288 if (retry == 0) { 289 aprint_error_dev(sc->sc.sc_dev, "PHY clock is not valid\n"); 290 return; 291 } 292 293 /* Disable ICUSB transceiver */ 294 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_ICUSB_CTRL_REG, 295 0, 296 TEGRA_EHCI_ICUSB_CTRL_ENB1); 297 298 /* Power up UTMPI transceiver */ 299 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG0_REG, 300 0, 301 TEGRA_EHCI_UTMIP_XCVR_CFG0_PD_POWERDOWN | 302 TEGRA_EHCI_UTMIP_XCVR_CFG0_PD2_POWERDOWN | 303 TEGRA_EHCI_UTMIP_XCVR_CFG0_PDZI_POWERDOWN); 304 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG1_REG, 305 0, 306 TEGRA_EHCI_UTMIP_XCVR_CFG1_PDDISC_POWERDOWN | 307 TEGRA_EHCI_UTMIP_XCVR_CFG1_PDCHRP_POWERDOWN | 308 TEGRA_EHCI_UTMIP_XCVR_CFG1_PDDR_POWERDOWN); 309 310 if (sc->sc_port == 0) { 311 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BIAS_CFG0_REG, 312 0, TEGRA_EHCI_UTMIP_BIAS_CFG0_BIASPD); 313 delay(25); 314 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BIAS_CFG1_REG, 315 0, TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_POWERDOWN); 316 } 317 } 318 319 static int 320 tegra_ehci_port_status(struct ehci_softc *ehci_sc, uint32_t v, int i) 321 { 322 struct tegra_ehci_softc * const sc = device_private(ehci_sc->sc_dev); 323 bus_space_tag_t iot = sc->sc_bst; 324 bus_space_handle_t ioh = sc->sc_bsh; 325 326 i &= ~(UPS_HIGH_SPEED|UPS_LOW_SPEED); 327 328 uint32_t val = bus_space_read_4(iot, ioh, 329 TEGRA_EHCI_HOSTPC1_DEVLC_REG); 330 331 switch (__SHIFTOUT(val, TEGRA_EHCI_HOSTPC1_DEVLC_PSPD)) { 332 case TEGRA_EHCI_HOSTPC1_DEVLC_PSPD_FS: 333 i |= UPS_FULL_SPEED; 334 break; 335 case TEGRA_EHCI_HOSTPC1_DEVLC_PSPD_LS: 336 i |= UPS_LOW_SPEED; 337 break; 338 case TEGRA_EHCI_HOSTPC1_DEVLC_PSPD_HS: 339 default: 340 i |= UPS_HIGH_SPEED; 341 break; 342 } 343 return i; 344 } 345
Indexes created Tue Sep 23 07:09:52 GMT 2025