tegra_ehci.c revision 1.8
1 /* $NetBSD: tegra_ehci.c,v 1.8 2015/10/21 10:43:09 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "locators.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: tegra_ehci.c,v 1.8 2015/10/21 10:43:09 jmcneill Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 41 #include <dev/usb/usb.h> 42 #include <dev/usb/usbdi.h> 43 #include <dev/usb/usbdivar.h> 44 #include <dev/usb/usb_mem.h> 45 #include <dev/usb/ehcireg.h> 46 #include <dev/usb/ehcivar.h> 47 48 #include <arm/nvidia/tegra_var.h> 49 #include <arm/nvidia/tegra_ehcireg.h> 50 51 #define TEGRA_EHCI_REG_OFFSET 0x100 52 53 static int tegra_ehci_match(device_t, cfdata_t, void *); 54 static void tegra_ehci_attach(device_t, device_t, void *); 55 56 static void tegra_ehci_init(struct ehci_softc *); 57 58 struct tegra_ehci_softc { 59 struct ehci_softc sc; 60 bus_space_tag_t sc_bst; 61 bus_space_handle_t sc_bsh; 62 void *sc_ih; 63 u_int sc_port; 64 65 struct tegra_gpio_pin *sc_pin_vbus; 66 uint8_t sc_hssync_start_delay; 67 uint8_t sc_idle_wait_delay; 68 uint8_t sc_elastic_limit; 69 uint8_t sc_term_range_adj; 70 uint8_t sc_xcvr_setup; 71 uint8_t sc_xcvr_lsfslew; 72 uint8_t sc_xcvr_lsrslew; 73 uint8_t sc_hssquelch_level; 74 uint8_t sc_hsdiscon_level; 75 uint8_t sc_xcvr_hsslew; 76 }; 77 78 static int tegra_ehci_parse_properties(struct tegra_ehci_softc *); 79 static void tegra_ehci_utmip_init(struct tegra_ehci_softc *); 80 static int tegra_ehci_port_status(struct ehci_softc *sc, uint32_t v, 81 int i); 82 83 CFATTACH_DECL2_NEW(tegra_ehci, sizeof(struct tegra_ehci_softc), 84 tegra_ehci_match, tegra_ehci_attach, NULL, 85 ehci_activate, NULL, ehci_childdet); 86 87 static int 88 tegra_ehci_match(device_t parent, cfdata_t cf, void *aux) 89 { 90 return 1; 91 } 92 93 static void 94 tegra_ehci_attach(device_t parent, device_t self, void *aux) 95 { 96 struct tegra_ehci_softc * const sc = device_private(self); 97 struct tegraio_attach_args * const tio = aux; 98 const struct tegra_locators * const loc = &tio->tio_loc; 99 prop_dictionary_t prop = device_properties(self); 100 const char *pin; 101 int error; 102 103 sc->sc_bst = tio->tio_bst; 104 bus_space_subregion(tio->tio_bst, tio->tio_bsh, 105 loc->loc_offset, loc->loc_size, &sc->sc_bsh); 106 sc->sc_port = loc->loc_port; 107 108 sc->sc.sc_dev = self; 109 sc->sc.sc_bus.hci_private = &sc->sc; 110 sc->sc.sc_bus.dmatag = tio->tio_dmat; 111 sc->sc.sc_bus.usbrev = USBREV_2_0; 112 sc->sc.sc_ncomp = 0; 113 sc->sc.sc_flags = EHCIF_ETTF; 114 sc->sc.sc_id_vendor = 0x10de; 115 strlcpy(sc->sc.sc_vendor, "Tegra", sizeof(sc->sc.sc_vendor)); 116 sc->sc.sc_size = loc->loc_size; 117 sc->sc.iot = tio->tio_bst; 118 bus_space_subregion(tio->tio_bst, tio->tio_bsh, 119 loc->loc_offset + TEGRA_EHCI_REG_OFFSET, 120 loc->loc_size - TEGRA_EHCI_REG_OFFSET, &sc->sc.ioh); 121 sc->sc.sc_vendor_init = tegra_ehci_init; 122 sc->sc.sc_vendor_port_status = tegra_ehci_port_status; 123 124 aprint_naive("\n"); 125 aprint_normal(": USB%d\n", loc->loc_port + 1); 126 127 if (tegra_ehci_parse_properties(sc) != 0) 128 return; 129 130 tegra_car_periph_usb_enable(sc->sc_port); 131 delay(2); 132 133 tegra_ehci_utmip_init(sc); 134 135 if (prop_dictionary_get_cstring_nocopy(prop, "vbus-gpio", &pin)) { 136 const uint32_t v = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 137 TEGRA_EHCI_PHY_VBUS_SENSORS_REG); 138 if ((v & TEGRA_EHCI_PHY_VBUS_SENSORS_A_VBUS_VLD_STS) == 0) { 139 sc->sc_pin_vbus = tegra_gpio_acquire(pin, 140 GPIO_PIN_OUTPUT | GPIO_PIN_OPENDRAIN); 141 if (sc->sc_pin_vbus) 142 tegra_gpio_write(sc->sc_pin_vbus, 1); 143 } else { 144 aprint_normal_dev(self, "VBUS input active\n"); 145 } 146 } 147 148 sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH); 149 150 sc->sc_ih = intr_establish(loc->loc_intr, IPL_USB, IST_LEVEL, 151 ehci_intr, &sc->sc); 152 if (sc->sc_ih == NULL) { 153 aprint_error_dev(self, "couldn't establish interrupt %d\n", 154 loc->loc_intr); 155 return; 156 } 157 aprint_normal_dev(self, "interrupting on irq %d\n", loc->loc_intr); 158 159 error = ehci_init(&sc->sc); 160 if (error != USBD_NORMAL_COMPLETION) { 161 aprint_error_dev(self, "init failed, error = %d\n", error); 162 return; 163 } 164 165 sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint); 166 } 167 168 static int 169 tegra_ehci_parse_properties(struct tegra_ehci_softc *sc) 170 { 171 #define PROPGET(k, v) \ 172 if (prop_dictionary_get_uint8(prop, (k), (v)) == false) { \ 173 aprint_error_dev(sc->sc.sc_dev, \ 174 "missing property '%s'\n", (k)); \ 175 return EIO; \ 176 } 177 178 prop_dictionary_t prop = device_properties(sc->sc.sc_dev); 179 180 PROPGET("nvidia,hssync-start-delay", &sc->sc_hssync_start_delay); 181 PROPGET("nvidia,idle-wait-delay", &sc->sc_idle_wait_delay); 182 PROPGET("nvidia,elastic-limit", &sc->sc_elastic_limit); 183 PROPGET("nvidia,term-range-adj", &sc->sc_term_range_adj); 184 PROPGET("nvidia,xcvr-setup", &sc->sc_xcvr_setup); 185 PROPGET("nvidia,xcvr-lsfslew", &sc->sc_xcvr_lsfslew); 186 PROPGET("nvidia,xcvr-lsrslew", &sc->sc_xcvr_lsrslew); 187 PROPGET("nvidia,hssquelch-level", &sc->sc_hssquelch_level); 188 PROPGET("nvidia,hsdiscon-level", &sc->sc_hsdiscon_level); 189 PROPGET("nvidia,xcvr-hsslew", &sc->sc_xcvr_hsslew); 190 191 return 0; 192 #undef PROPGET 193 } 194 195 static void 196 tegra_ehci_init(struct ehci_softc *esc) 197 { 198 struct tegra_ehci_softc * const sc = device_private(esc->sc_dev); 199 uint32_t usbmode; 200 201 usbmode = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 202 TEGRA_EHCI_USBMODE_REG); 203 204 const u_int cm = __SHIFTOUT(usbmode, TEGRA_EHCI_USBMODE_CM); 205 if (cm != TEGRA_EHCI_USBMODE_CM_HOST) { 206 aprint_verbose_dev(esc->sc_dev, "switching to host mode\n"); 207 usbmode &= ~TEGRA_EHCI_USBMODE_CM; 208 usbmode |= __SHIFTIN(TEGRA_EHCI_USBMODE_CM_HOST, 209 TEGRA_EHCI_USBMODE_CM); 210 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 211 TEGRA_EHCI_USBMODE_REG, usbmode); 212 } 213 214 /* Parallel transceiver select */ 215 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, 216 TEGRA_EHCI_HOSTPC1_DEVLC_REG, 217 __SHIFTIN(TEGRA_EHCI_HOSTPC1_DEVLC_PTS_UTMI, 218 TEGRA_EHCI_HOSTPC1_DEVLC_PTS), 219 TEGRA_EHCI_HOSTPC1_DEVLC_PTS | 220 TEGRA_EHCI_HOSTPC1_DEVLC_STS); 221 222 bus_space_write_4(sc->sc_bst, sc->sc_bsh, TEGRA_EHCI_TXFILLTUNING_REG, 223 __SHIFTIN(0x10, TEGRA_EHCI_TXFILLTUNING_TXFIFOTHRES)); 224 } 225 226 static void 227 tegra_ehci_utmip_init(struct tegra_ehci_softc *sc) 228 { 229 bus_space_tag_t bst = sc->sc_bst; 230 bus_space_handle_t bsh = sc->sc_bsh; 231 int retry; 232 233 /* Put UTMIP PHY into reset before programming UTMIP config registers */ 234 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_SUSP_CTRL_REG, 235 TEGRA_EHCI_SUSP_CTRL_UTMIP_RESET, 0); 236 237 /* Enable UTMIP PHY mode */ 238 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_SUSP_CTRL_REG, 239 TEGRA_EHCI_SUSP_CTRL_UTMIP_PHY_ENB, 0); 240 241 /* Stop crystal clock */ 242 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_MISC_CFG1_REG, 243 0, TEGRA_EHCI_UTMIP_MISC_CFG1_PHY_XTAL_CLOCKEN); 244 delay(1); 245 246 /* Clear session status */ 247 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_PHY_VBUS_SENSORS_REG, 248 0, 249 TEGRA_EHCI_PHY_VBUS_SENSORS_B_VLD_SW_VALUE | 250 TEGRA_EHCI_PHY_VBUS_SENSORS_B_VLD_SW_EN); 251 252 /* PLL configuration */ 253 tegra_car_utmip_init(); 254 255 /* Transceiver configuration */ 256 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG0_REG, 257 __SHIFTIN(4, TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP) | 258 __SHIFTIN(3, TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP_MSB) | 259 __SHIFTIN(sc->sc_xcvr_hsslew, 260 TEGRA_EHCI_UTMIP_XCVR_CFG0_HSSLEW_MSB), 261 TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP | 262 TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP_MSB | 263 TEGRA_EHCI_UTMIP_XCVR_CFG0_HSSLEW_MSB); 264 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG1_REG, 265 __SHIFTIN(sc->sc_term_range_adj, 266 TEGRA_EHCI_UTMIP_XCVR_CFG1_TERM_RANGE_ADJ), 267 TEGRA_EHCI_UTMIP_XCVR_CFG1_TERM_RANGE_ADJ); 268 269 if (sc->sc_port == 0) { 270 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BIAS_CFG0_REG, 271 TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL_MSB | 272 __SHIFTIN(sc->sc_hsdiscon_level, 273 TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL), 274 TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL); 275 } 276 277 /* Misc config */ 278 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_MISC_CFG0_REG, 279 0, 280 TEGRA_EHCI_UTMIP_MISC_CFG0_SUSPEND_EXIT_ON_EDGE); 281 282 /* BIAS cell power down lag */ 283 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BIAS_CFG1_REG, 284 __SHIFTIN(5, TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_COUNT), 285 TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_COUNT); 286 287 /* Debounce config */ 288 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_REG, 289 __SHIFTIN(0x7530, TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_A), 290 TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_A); 291 292 /* Transmit signal preamble config */ 293 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_TX_CFG0_REG, 294 TEGRA_EHCI_UTMIP_TX_CFG0_FS_PREAMBLE_J, 0); 295 296 /* Power-down battery charger circuit */ 297 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BAT_CHRG_CFG0_REG, 298 TEGRA_EHCI_UTMIP_BAT_CHRG_CFG0_PD_CHRG, 0); 299 300 /* Select low speed bias method */ 301 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG0_REG, 302 0, TEGRA_EHCI_UTMIP_XCVR_CFG0_LSBIAS_SEL); 303 304 /* High speed receive config */ 305 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_HSRX_CFG0_REG, 306 __SHIFTIN(sc->sc_idle_wait_delay, 307 TEGRA_EHCI_UTMIP_HSRX_CFG0_IDLE_WAIT) | 308 __SHIFTIN(sc->sc_elastic_limit, 309 TEGRA_EHCI_UTMIP_HSRX_CFG0_ELASTIC_LIMIT), 310 TEGRA_EHCI_UTMIP_HSRX_CFG0_IDLE_WAIT | 311 TEGRA_EHCI_UTMIP_HSRX_CFG0_ELASTIC_LIMIT); 312 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_HSRX_CFG1_REG, 313 __SHIFTIN(sc->sc_hssync_start_delay, 314 TEGRA_EHCI_UTMIP_HSRX_CFG1_SYNC_START_DLY), 315 TEGRA_EHCI_UTMIP_HSRX_CFG1_SYNC_START_DLY); 316 317 /* Start crystal clock */ 318 delay(1); 319 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_MISC_CFG1_REG, 320 TEGRA_EHCI_UTMIP_MISC_CFG1_PHY_XTAL_CLOCKEN, 0); 321 322 /* Clear port PLL powerdown status */ 323 tegra_car_utmip_enable(sc->sc_port); 324 325 /* Bring UTMIP PHY out of reset */ 326 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_SUSP_CTRL_REG, 327 0, TEGRA_EHCI_SUSP_CTRL_UTMIP_RESET); 328 for (retry = 100000; retry > 0; retry--) { 329 const uint32_t susp = bus_space_read_4(bst, bsh, 330 TEGRA_EHCI_SUSP_CTRL_REG); 331 if (susp & TEGRA_EHCI_SUSP_CTRL_PHY_CLK_VALID) 332 break; 333 delay(1); 334 } 335 if (retry == 0) { 336 aprint_error_dev(sc->sc.sc_dev, "PHY clock is not valid\n"); 337 return; 338 } 339 340 /* Disable ICUSB transceiver */ 341 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_ICUSB_CTRL_REG, 342 0, 343 TEGRA_EHCI_ICUSB_CTRL_ENB1); 344 345 /* Power up UTMPI transceiver */ 346 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG0_REG, 347 0, 348 TEGRA_EHCI_UTMIP_XCVR_CFG0_PD_POWERDOWN | 349 TEGRA_EHCI_UTMIP_XCVR_CFG0_PD2_POWERDOWN | 350 TEGRA_EHCI_UTMIP_XCVR_CFG0_PDZI_POWERDOWN); 351 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG1_REG, 352 0, 353 TEGRA_EHCI_UTMIP_XCVR_CFG1_PDDISC_POWERDOWN | 354 TEGRA_EHCI_UTMIP_XCVR_CFG1_PDCHRP_POWERDOWN | 355 TEGRA_EHCI_UTMIP_XCVR_CFG1_PDDR_POWERDOWN); 356 357 if (sc->sc_port == 0) { 358 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BIAS_CFG0_REG, 359 0, TEGRA_EHCI_UTMIP_BIAS_CFG0_BIASPD); 360 delay(25); 361 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BIAS_CFG1_REG, 362 0, TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_POWERDOWN); 363 } 364 } 365 366 static int 367 tegra_ehci_port_status(struct ehci_softc *ehci_sc, uint32_t v, int i) 368 { 369 struct tegra_ehci_softc * const sc = device_private(ehci_sc->sc_dev); 370 bus_space_tag_t iot = sc->sc_bst; 371 bus_space_handle_t ioh = sc->sc_bsh; 372 373 i &= ~(UPS_HIGH_SPEED|UPS_LOW_SPEED); 374 375 uint32_t val = bus_space_read_4(iot, ioh, 376 TEGRA_EHCI_HOSTPC1_DEVLC_REG); 377 378 switch (__SHIFTOUT(val, TEGRA_EHCI_HOSTPC1_DEVLC_PSPD)) { 379 case TEGRA_EHCI_HOSTPC1_DEVLC_PSPD_FS: 380 i |= UPS_FULL_SPEED; 381 break; 382 case TEGRA_EHCI_HOSTPC1_DEVLC_PSPD_LS: 383 i |= UPS_LOW_SPEED; 384 break; 385 case TEGRA_EHCI_HOSTPC1_DEVLC_PSPD_HS: 386 default: 387 i |= UPS_HIGH_SPEED; 388 break; 389 } 390 return i; 391 } 392
Indexes created Fri Oct 17 17:09:57 GMT 2025