tegra_gpio.c revision 1.3.2.2
1 1.3.2.2 skrll /* $NetBSD: tegra_gpio.c,v 1.3.2.2 2015/06/06 14:39:56 skrll Exp $ */ 2 1.3.2.2 skrll 3 1.3.2.2 skrll /*- 4 1.3.2.2 skrll * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 1.3.2.2 skrll * All rights reserved. 6 1.3.2.2 skrll * 7 1.3.2.2 skrll * Redistribution and use in source and binary forms, with or without 8 1.3.2.2 skrll * modification, are permitted provided that the following conditions 9 1.3.2.2 skrll * are met: 10 1.3.2.2 skrll * 1. Redistributions of source code must retain the above copyright 11 1.3.2.2 skrll * notice, this list of conditions and the following disclaimer. 12 1.3.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 13 1.3.2.2 skrll * notice, this list of conditions and the following disclaimer in the 14 1.3.2.2 skrll * documentation and/or other materials provided with the distribution. 15 1.3.2.2 skrll * 16 1.3.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 1.3.2.2 skrll * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 1.3.2.2 skrll * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 1.3.2.2 skrll * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 1.3.2.2 skrll * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 1.3.2.2 skrll * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 1.3.2.2 skrll * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 1.3.2.2 skrll * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 1.3.2.2 skrll * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.3.2.2 skrll * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.3.2.2 skrll * SUCH DAMAGE. 27 1.3.2.2 skrll */ 28 1.3.2.2 skrll 29 1.3.2.2 skrll #include "locators.h" 30 1.3.2.2 skrll 31 1.3.2.2 skrll #include <sys/cdefs.h> 32 1.3.2.2 skrll __KERNEL_RCSID(0, "$NetBSD: tegra_gpio.c,v 1.3.2.2 2015/06/06 14:39:56 skrll Exp $"); 33 1.3.2.2 skrll 34 1.3.2.2 skrll #include <sys/param.h> 35 1.3.2.2 skrll #include <sys/bus.h> 36 1.3.2.2 skrll #include <sys/device.h> 37 1.3.2.2 skrll #include <sys/intr.h> 38 1.3.2.2 skrll #include <sys/systm.h> 39 1.3.2.2 skrll #include <sys/kernel.h> 40 1.3.2.2 skrll #include <sys/kmem.h> 41 1.3.2.2 skrll #include <sys/gpio.h> 42 1.3.2.2 skrll 43 1.3.2.2 skrll #include <dev/gpio/gpiovar.h> 44 1.3.2.2 skrll 45 1.3.2.2 skrll #include <arm/nvidia/tegra_reg.h> 46 1.3.2.2 skrll #include <arm/nvidia/tegra_gpioreg.h> 47 1.3.2.2 skrll #include <arm/nvidia/tegra_var.h> 48 1.3.2.2 skrll 49 1.3.2.2 skrll const struct tegra_gpio_pinbank { 50 1.3.2.2 skrll const char *name; 51 1.3.2.2 skrll bus_size_t base; 52 1.3.2.2 skrll } tegra_gpio_pinbanks [] = { 53 1.3.2.2 skrll { "A", 0x000 }, 54 1.3.2.2 skrll { "B", 0x004 }, 55 1.3.2.2 skrll { "C", 0x008 }, 56 1.3.2.2 skrll { "D", 0x00c }, 57 1.3.2.2 skrll { "E", 0x100 }, 58 1.3.2.2 skrll { "F", 0x104 }, 59 1.3.2.2 skrll { "G", 0x108 }, 60 1.3.2.2 skrll { "H", 0x10c }, 61 1.3.2.2 skrll { "I", 0x200 }, 62 1.3.2.2 skrll { "J", 0x204 }, 63 1.3.2.2 skrll { "K", 0x208 }, 64 1.3.2.2 skrll { "L", 0x20c }, 65 1.3.2.2 skrll { "M", 0x300 }, 66 1.3.2.2 skrll { "N", 0x304 }, 67 1.3.2.2 skrll { "O", 0x308 }, 68 1.3.2.2 skrll { "P", 0x30c }, 69 1.3.2.2 skrll { "Q", 0x400 }, 70 1.3.2.2 skrll { "R", 0x404 }, 71 1.3.2.2 skrll { "S", 0x408 }, 72 1.3.2.2 skrll { "T", 0x40c }, 73 1.3.2.2 skrll { "U", 0x500 }, 74 1.3.2.2 skrll { "V", 0x504 }, 75 1.3.2.2 skrll { "W", 0x508 }, 76 1.3.2.2 skrll { "X", 0x50c }, 77 1.3.2.2 skrll { "Y", 0x600 }, 78 1.3.2.2 skrll { "Z", 0x604 }, 79 1.3.2.2 skrll { "AA", 0x608 }, 80 1.3.2.2 skrll { "BB", 0x60c }, 81 1.3.2.2 skrll { "CC", 0x700 }, 82 1.3.2.2 skrll { "DD", 0x704 }, 83 1.3.2.2 skrll { "EE", 0x708 } 84 1.3.2.2 skrll }; 85 1.3.2.2 skrll 86 1.3.2.2 skrll static int tegra_gpio_match(device_t, cfdata_t, void *); 87 1.3.2.2 skrll static void tegra_gpio_attach(device_t, device_t, void *); 88 1.3.2.2 skrll 89 1.3.2.2 skrll struct tegra_gpio_softc; 90 1.3.2.2 skrll 91 1.3.2.2 skrll struct tegra_gpio_bank { 92 1.3.2.2 skrll struct tegra_gpio_softc *bank_sc; 93 1.3.2.2 skrll const struct tegra_gpio_pinbank *bank_pb; 94 1.3.2.2 skrll device_t bank_dev; 95 1.3.2.2 skrll struct gpio_chipset_tag bank_gc; 96 1.3.2.2 skrll gpio_pin_t bank_pins[8]; 97 1.3.2.2 skrll }; 98 1.3.2.2 skrll 99 1.3.2.2 skrll struct tegra_gpio_softc { 100 1.3.2.2 skrll device_t sc_dev; 101 1.3.2.2 skrll bus_space_tag_t sc_bst; 102 1.3.2.2 skrll bus_space_handle_t sc_bsh; 103 1.3.2.2 skrll 104 1.3.2.2 skrll struct tegra_gpio_bank *sc_banks; 105 1.3.2.2 skrll }; 106 1.3.2.2 skrll 107 1.3.2.2 skrll struct tegra_gpio_pin { 108 1.3.2.2 skrll struct tegra_gpio_softc *pin_sc; 109 1.3.2.2 skrll struct tegra_gpio_bank pin_bank; 110 1.3.2.2 skrll int pin_no; 111 1.3.2.2 skrll u_int pin_flags; 112 1.3.2.2 skrll }; 113 1.3.2.2 skrll 114 1.3.2.2 skrll static void tegra_gpio_attach_bank(struct tegra_gpio_softc *, u_int); 115 1.3.2.2 skrll 116 1.3.2.2 skrll static int tegra_gpio_pin_read(void *, int); 117 1.3.2.2 skrll static void tegra_gpio_pin_write(void *, int, int); 118 1.3.2.2 skrll static void tegra_gpio_pin_ctl(void *, int, int); 119 1.3.2.2 skrll 120 1.3.2.2 skrll static int tegra_gpio_cfprint(void *, const char *); 121 1.3.2.2 skrll 122 1.3.2.2 skrll CFATTACH_DECL_NEW(tegra_gpio, sizeof(struct tegra_gpio_softc), 123 1.3.2.2 skrll tegra_gpio_match, tegra_gpio_attach, NULL, NULL); 124 1.3.2.2 skrll 125 1.3.2.2 skrll #define GPIO_WRITE(bank, reg, val) \ 126 1.3.2.2 skrll bus_space_write_4((bank)->bank_sc->sc_bst, \ 127 1.3.2.2 skrll (bank)->bank_sc->sc_bsh, \ 128 1.3.2.2 skrll (bank)->bank_pb->base + (reg), (val)) 129 1.3.2.2 skrll #define GPIO_READ(bank, reg) \ 130 1.3.2.2 skrll bus_space_read_4((bank)->bank_sc->sc_bst, \ 131 1.3.2.2 skrll (bank)->bank_sc->sc_bsh, \ 132 1.3.2.2 skrll (bank)->bank_pb->base + (reg)) 133 1.3.2.2 skrll 134 1.3.2.2 skrll static int 135 1.3.2.2 skrll tegra_gpio_match(device_t parent, cfdata_t cf, void *aux) 136 1.3.2.2 skrll { 137 1.3.2.2 skrll return 1; 138 1.3.2.2 skrll } 139 1.3.2.2 skrll 140 1.3.2.2 skrll static void 141 1.3.2.2 skrll tegra_gpio_attach(device_t parent, device_t self, void *aux) 142 1.3.2.2 skrll { 143 1.3.2.2 skrll struct tegra_gpio_softc * const sc = device_private(self); 144 1.3.2.2 skrll struct tegraio_attach_args * const tio = aux; 145 1.3.2.2 skrll const struct tegra_locators * const loc = &tio->tio_loc; 146 1.3.2.2 skrll u_int n; 147 1.3.2.2 skrll 148 1.3.2.2 skrll sc->sc_dev = self; 149 1.3.2.2 skrll sc->sc_bst = tio->tio_bst; 150 1.3.2.2 skrll bus_space_subregion(tio->tio_bst, tio->tio_bsh, 151 1.3.2.2 skrll loc->loc_offset, loc->loc_size, &sc->sc_bsh); 152 1.3.2.2 skrll 153 1.3.2.2 skrll aprint_naive("\n"); 154 1.3.2.2 skrll aprint_normal(": GPIO\n"); 155 1.3.2.2 skrll 156 1.3.2.2 skrll const u_int nbank = __arraycount(tegra_gpio_pinbanks); 157 1.3.2.2 skrll sc->sc_banks = kmem_zalloc(sizeof(*sc->sc_banks) * nbank, KM_SLEEP); 158 1.3.2.2 skrll for (n = 0; n < nbank; n++) { 159 1.3.2.2 skrll tegra_gpio_attach_bank(sc, n); 160 1.3.2.2 skrll } 161 1.3.2.2 skrll } 162 1.3.2.2 skrll 163 1.3.2.2 skrll static void 164 1.3.2.2 skrll tegra_gpio_attach_bank(struct tegra_gpio_softc *sc, u_int bankno) 165 1.3.2.2 skrll { 166 1.3.2.2 skrll struct tegra_gpio_bank *bank = &sc->sc_banks[bankno]; 167 1.3.2.2 skrll struct gpiobus_attach_args gba; 168 1.3.2.2 skrll u_int pin; 169 1.3.2.2 skrll 170 1.3.2.2 skrll bank->bank_sc = sc; 171 1.3.2.2 skrll bank->bank_pb = &tegra_gpio_pinbanks[bankno]; 172 1.3.2.2 skrll bank->bank_gc.gp_cookie = bank; 173 1.3.2.2 skrll bank->bank_gc.gp_pin_read = tegra_gpio_pin_read; 174 1.3.2.2 skrll bank->bank_gc.gp_pin_write = tegra_gpio_pin_write; 175 1.3.2.2 skrll bank->bank_gc.gp_pin_ctl = tegra_gpio_pin_ctl; 176 1.3.2.2 skrll 177 1.3.2.2 skrll const uint32_t cnf = GPIO_READ(bank, GPIO_CNF_REG); 178 1.3.2.2 skrll 179 1.3.2.2 skrll for (pin = 0; pin < __arraycount(bank->bank_pins); pin++) { 180 1.3.2.2 skrll bank->bank_pins[pin].pin_num = pin; 181 1.3.2.2 skrll /* skip pins in SFIO mode */ 182 1.3.2.2 skrll if ((cnf & __BIT(pin)) == 0) 183 1.3.2.2 skrll continue; 184 1.3.2.2 skrll bank->bank_pins[pin].pin_caps = 185 1.3.2.2 skrll GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | 186 1.3.2.2 skrll GPIO_PIN_TRISTATE; 187 1.3.2.2 skrll bank->bank_pins[pin].pin_state = 188 1.3.2.2 skrll tegra_gpio_pin_read(bank, pin); 189 1.3.2.2 skrll } 190 1.3.2.2 skrll 191 1.3.2.2 skrll memset(&gba, 0, sizeof(gba)); 192 1.3.2.2 skrll gba.gba_gc = &bank->bank_gc; 193 1.3.2.2 skrll gba.gba_pins = bank->bank_pins; 194 1.3.2.2 skrll gba.gba_npins = __arraycount(bank->bank_pins); 195 1.3.2.2 skrll 196 1.3.2.2 skrll bank->bank_dev = config_found_ia(sc->sc_dev, "gpiobus", &gba, 197 1.3.2.2 skrll tegra_gpio_cfprint); 198 1.3.2.2 skrll } 199 1.3.2.2 skrll 200 1.3.2.2 skrll static int 201 1.3.2.2 skrll tegra_gpio_cfprint(void *priv, const char *pnp) 202 1.3.2.2 skrll { 203 1.3.2.2 skrll struct gpiobus_attach_args *gba = priv; 204 1.3.2.2 skrll struct tegra_gpio_bank *bank = gba->gba_gc->gp_cookie; 205 1.3.2.2 skrll const char *bankname = bank->bank_pb->name; 206 1.3.2.2 skrll 207 1.3.2.2 skrll if (pnp) 208 1.3.2.2 skrll aprint_normal("gpiobus at %s", pnp); 209 1.3.2.2 skrll 210 1.3.2.2 skrll aprint_normal(" (%s)", bankname); 211 1.3.2.2 skrll 212 1.3.2.2 skrll return UNCONF; 213 1.3.2.2 skrll } 214 1.3.2.2 skrll 215 1.3.2.2 skrll static int 216 1.3.2.2 skrll tegra_gpio_pin_read(void *priv, int pin) 217 1.3.2.2 skrll { 218 1.3.2.2 skrll struct tegra_gpio_bank *bank = priv; 219 1.3.2.2 skrll 220 1.3.2.2 skrll const uint32_t v = GPIO_READ(bank, GPIO_IN_REG); 221 1.3.2.2 skrll 222 1.3.2.2 skrll return (v >> pin) & 1; 223 1.3.2.2 skrll } 224 1.3.2.2 skrll 225 1.3.2.2 skrll static void 226 1.3.2.2 skrll tegra_gpio_pin_write(void *priv, int pin, int val) 227 1.3.2.2 skrll { 228 1.3.2.2 skrll struct tegra_gpio_bank *bank = priv; 229 1.3.2.2 skrll uint32_t v; 230 1.3.2.2 skrll 231 1.3.2.2 skrll v = (1 << (pin + 8)); 232 1.3.2.2 skrll v |= (val << pin); 233 1.3.2.2 skrll GPIO_WRITE(bank, GPIO_MSK_OUT_REG, v); 234 1.3.2.2 skrll } 235 1.3.2.2 skrll 236 1.3.2.2 skrll static void 237 1.3.2.2 skrll tegra_gpio_pin_ctl(void *priv, int pin, int flags) 238 1.3.2.2 skrll { 239 1.3.2.2 skrll struct tegra_gpio_bank *bank = priv; 240 1.3.2.2 skrll uint32_t v; 241 1.3.2.2 skrll 242 1.3.2.2 skrll if (flags & GPIO_PIN_INPUT) { 243 1.3.2.2 skrll v = (1 << (pin + 8)); 244 1.3.2.2 skrll GPIO_WRITE(bank, GPIO_MSK_OE_REG, v); 245 1.3.2.2 skrll } else if (flags & GPIO_PIN_OUTPUT) { 246 1.3.2.2 skrll v = (1 << (pin + 8)); 247 1.3.2.2 skrll v |= (1 << pin); 248 1.3.2.2 skrll GPIO_WRITE(bank, GPIO_MSK_OE_REG, v); 249 1.3.2.2 skrll } 250 1.3.2.2 skrll } 251 1.3.2.2 skrll 252 1.3.2.2 skrll static const struct tegra_gpio_pinbank * 253 1.3.2.2 skrll tegra_gpio_pin_lookup(const char *pinname, int *ppin) 254 1.3.2.2 skrll { 255 1.3.2.2 skrll char bankname[3]; 256 1.3.2.2 skrll u_int n; 257 1.3.2.2 skrll int pin; 258 1.3.2.2 skrll 259 1.3.2.2 skrll KASSERT(strlen(pinname) == 2 || strlen(pinname) == 3); 260 1.3.2.2 skrll 261 1.3.2.2 skrll memset(bankname, 0, sizeof(bankname)); 262 1.3.2.2 skrll bankname[0] = pinname[0]; 263 1.3.2.2 skrll if (strlen(pinname) == 2) { 264 1.3.2.2 skrll pin = pinname[1] - '0'; 265 1.3.2.2 skrll } else { 266 1.3.2.2 skrll bankname[1] = pinname[1]; 267 1.3.2.2 skrll pin = pinname[2] - '0'; 268 1.3.2.2 skrll } 269 1.3.2.2 skrll 270 1.3.2.2 skrll for (n = 0; n < __arraycount(tegra_gpio_pinbanks); n++) { 271 1.3.2.2 skrll const struct tegra_gpio_pinbank *pb = 272 1.3.2.2 skrll &tegra_gpio_pinbanks[n]; 273 1.3.2.2 skrll if (strcmp(pb->name, bankname) == 0) { 274 1.3.2.2 skrll *ppin = pin; 275 1.3.2.2 skrll return pb; 276 1.3.2.2 skrll } 277 1.3.2.2 skrll } 278 1.3.2.2 skrll 279 1.3.2.2 skrll return NULL; 280 1.3.2.2 skrll } 281 1.3.2.2 skrll 282 1.3.2.2 skrll struct tegra_gpio_pin * 283 1.3.2.2 skrll tegra_gpio_acquire(const char *pinname, u_int flags) 284 1.3.2.2 skrll { 285 1.3.2.2 skrll struct tegra_gpio_bank bank; 286 1.3.2.2 skrll struct tegra_gpio_pin *gpin; 287 1.3.2.2 skrll int pin; 288 1.3.2.2 skrll device_t dev; 289 1.3.2.2 skrll 290 1.3.2.2 skrll dev = device_find_by_driver_unit("tegragpio", 0); 291 1.3.2.2 skrll if (dev == NULL) 292 1.3.2.2 skrll return NULL; 293 1.3.2.2 skrll 294 1.3.2.2 skrll bank.bank_sc = device_private(dev); 295 1.3.2.2 skrll bank.bank_pb = tegra_gpio_pin_lookup(pinname, &pin); 296 1.3.2.2 skrll if (bank.bank_pb == NULL) 297 1.3.2.2 skrll return NULL; 298 1.3.2.2 skrll 299 1.3.2.2 skrll const uint32_t cnf = GPIO_READ(&bank, GPIO_CNF_REG); 300 1.3.2.2 skrll if ((cnf & __BIT(pin)) == 0) 301 1.3.2.2 skrll GPIO_WRITE(&bank, GPIO_CNF_REG, cnf | __BIT(pin)); 302 1.3.2.2 skrll 303 1.3.2.2 skrll gpin = kmem_alloc(sizeof(*gpin), KM_SLEEP); 304 1.3.2.2 skrll gpin->pin_bank = bank; 305 1.3.2.2 skrll gpin->pin_no = pin; 306 1.3.2.2 skrll gpin->pin_flags = flags; 307 1.3.2.2 skrll 308 1.3.2.2 skrll tegra_gpio_pin_ctl(&gpin->pin_bank, gpin->pin_no, gpin->pin_flags); 309 1.3.2.2 skrll 310 1.3.2.2 skrll return gpin; 311 1.3.2.2 skrll } 312 1.3.2.2 skrll 313 1.3.2.2 skrll void 314 1.3.2.2 skrll tegra_gpio_release(struct tegra_gpio_pin *gpin) 315 1.3.2.2 skrll { 316 1.3.2.2 skrll tegra_gpio_pin_ctl(&gpin->pin_bank, gpin->pin_no, GPIO_PIN_INPUT); 317 1.3.2.2 skrll kmem_free(gpin, sizeof(*gpin)); 318 1.3.2.2 skrll } 319 1.3.2.2 skrll 320 1.3.2.2 skrll int 321 1.3.2.2 skrll tegra_gpio_read(struct tegra_gpio_pin *gpin) 322 1.3.2.2 skrll { 323 1.3.2.2 skrll if (gpin->pin_flags & GPIO_PIN_INPUT) { 324 1.3.2.2 skrll return tegra_gpio_pin_read(&gpin->pin_bank, gpin->pin_no); 325 1.3.2.2 skrll } else { 326 1.3.2.2 skrll const uint32_t v = GPIO_READ(&gpin->pin_bank, GPIO_OUT_REG); 327 1.3.2.2 skrll return (v >> gpin->pin_no) & 1; 328 1.3.2.2 skrll } 329 1.3.2.2 skrll } 330 1.3.2.2 skrll 331 1.3.2.2 skrll void 332 1.3.2.2 skrll tegra_gpio_write(struct tegra_gpio_pin *gpin, int val) 333 1.3.2.2 skrll { 334 1.3.2.2 skrll KASSERT((gpin->pin_flags & GPIO_PIN_OUTPUT) != 0); 335 1.3.2.2 skrll tegra_gpio_pin_write(&gpin->pin_bank, gpin->pin_no, val); 336 1.3.2.2 skrll } 337
Indexes created Thu Oct 02 07:10:07 GMT 2025