tegra_gpio.c revision 1.3.2.5
1 1.3.2.5 skrll /* $NetBSD: tegra_gpio.c,v 1.3.2.5 2017/08/28 17:51:31 skrll Exp $ */ 2 1.3.2.2 skrll 3 1.3.2.2 skrll /*- 4 1.3.2.2 skrll * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 1.3.2.2 skrll * All rights reserved. 6 1.3.2.2 skrll * 7 1.3.2.2 skrll * Redistribution and use in source and binary forms, with or without 8 1.3.2.2 skrll * modification, are permitted provided that the following conditions 9 1.3.2.2 skrll * are met: 10 1.3.2.2 skrll * 1. Redistributions of source code must retain the above copyright 11 1.3.2.2 skrll * notice, this list of conditions and the following disclaimer. 12 1.3.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 13 1.3.2.2 skrll * notice, this list of conditions and the following disclaimer in the 14 1.3.2.2 skrll * documentation and/or other materials provided with the distribution. 15 1.3.2.2 skrll * 16 1.3.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 1.3.2.2 skrll * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 1.3.2.2 skrll * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 1.3.2.2 skrll * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 1.3.2.2 skrll * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 1.3.2.2 skrll * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 1.3.2.2 skrll * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 1.3.2.2 skrll * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 1.3.2.2 skrll * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.3.2.2 skrll * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.3.2.2 skrll * SUCH DAMAGE. 27 1.3.2.2 skrll */ 28 1.3.2.2 skrll 29 1.3.2.2 skrll #include <sys/cdefs.h> 30 1.3.2.5 skrll __KERNEL_RCSID(0, "$NetBSD: tegra_gpio.c,v 1.3.2.5 2017/08/28 17:51:31 skrll Exp $"); 31 1.3.2.2 skrll 32 1.3.2.2 skrll #include <sys/param.h> 33 1.3.2.2 skrll #include <sys/bus.h> 34 1.3.2.2 skrll #include <sys/device.h> 35 1.3.2.2 skrll #include <sys/intr.h> 36 1.3.2.2 skrll #include <sys/systm.h> 37 1.3.2.2 skrll #include <sys/kernel.h> 38 1.3.2.2 skrll #include <sys/kmem.h> 39 1.3.2.2 skrll #include <sys/gpio.h> 40 1.3.2.2 skrll 41 1.3.2.2 skrll #include <dev/gpio/gpiovar.h> 42 1.3.2.2 skrll 43 1.3.2.2 skrll #include <arm/nvidia/tegra_reg.h> 44 1.3.2.2 skrll #include <arm/nvidia/tegra_gpioreg.h> 45 1.3.2.2 skrll #include <arm/nvidia/tegra_var.h> 46 1.3.2.2 skrll 47 1.3.2.3 skrll #include <dev/fdt/fdtvar.h> 48 1.3.2.3 skrll 49 1.3.2.2 skrll const struct tegra_gpio_pinbank { 50 1.3.2.2 skrll const char *name; 51 1.3.2.2 skrll bus_size_t base; 52 1.3.2.2 skrll } tegra_gpio_pinbanks [] = { 53 1.3.2.2 skrll { "A", 0x000 }, 54 1.3.2.2 skrll { "B", 0x004 }, 55 1.3.2.2 skrll { "C", 0x008 }, 56 1.3.2.2 skrll { "D", 0x00c }, 57 1.3.2.2 skrll { "E", 0x100 }, 58 1.3.2.2 skrll { "F", 0x104 }, 59 1.3.2.2 skrll { "G", 0x108 }, 60 1.3.2.2 skrll { "H", 0x10c }, 61 1.3.2.2 skrll { "I", 0x200 }, 62 1.3.2.2 skrll { "J", 0x204 }, 63 1.3.2.2 skrll { "K", 0x208 }, 64 1.3.2.2 skrll { "L", 0x20c }, 65 1.3.2.2 skrll { "M", 0x300 }, 66 1.3.2.2 skrll { "N", 0x304 }, 67 1.3.2.2 skrll { "O", 0x308 }, 68 1.3.2.2 skrll { "P", 0x30c }, 69 1.3.2.2 skrll { "Q", 0x400 }, 70 1.3.2.2 skrll { "R", 0x404 }, 71 1.3.2.2 skrll { "S", 0x408 }, 72 1.3.2.2 skrll { "T", 0x40c }, 73 1.3.2.2 skrll { "U", 0x500 }, 74 1.3.2.2 skrll { "V", 0x504 }, 75 1.3.2.2 skrll { "W", 0x508 }, 76 1.3.2.2 skrll { "X", 0x50c }, 77 1.3.2.2 skrll { "Y", 0x600 }, 78 1.3.2.2 skrll { "Z", 0x604 }, 79 1.3.2.2 skrll { "AA", 0x608 }, 80 1.3.2.2 skrll { "BB", 0x60c }, 81 1.3.2.2 skrll { "CC", 0x700 }, 82 1.3.2.2 skrll { "DD", 0x704 }, 83 1.3.2.2 skrll { "EE", 0x708 } 84 1.3.2.2 skrll }; 85 1.3.2.2 skrll 86 1.3.2.2 skrll static int tegra_gpio_match(device_t, cfdata_t, void *); 87 1.3.2.2 skrll static void tegra_gpio_attach(device_t, device_t, void *); 88 1.3.2.2 skrll 89 1.3.2.3 skrll static void * tegra_gpio_fdt_acquire(device_t, const void *, 90 1.3.2.3 skrll size_t, int); 91 1.3.2.3 skrll static void tegra_gpio_fdt_release(device_t, void *); 92 1.3.2.3 skrll static int tegra_gpio_fdt_read(device_t, void *, bool); 93 1.3.2.3 skrll static void tegra_gpio_fdt_write(device_t, void *, int, bool); 94 1.3.2.3 skrll 95 1.3.2.3 skrll struct fdtbus_gpio_controller_func tegra_gpio_funcs = { 96 1.3.2.3 skrll .acquire = tegra_gpio_fdt_acquire, 97 1.3.2.3 skrll .release = tegra_gpio_fdt_release, 98 1.3.2.3 skrll .read = tegra_gpio_fdt_read, 99 1.3.2.3 skrll .write = tegra_gpio_fdt_write 100 1.3.2.3 skrll }; 101 1.3.2.3 skrll 102 1.3.2.2 skrll struct tegra_gpio_softc; 103 1.3.2.2 skrll 104 1.3.2.2 skrll struct tegra_gpio_bank { 105 1.3.2.2 skrll struct tegra_gpio_softc *bank_sc; 106 1.3.2.2 skrll const struct tegra_gpio_pinbank *bank_pb; 107 1.3.2.2 skrll device_t bank_dev; 108 1.3.2.2 skrll struct gpio_chipset_tag bank_gc; 109 1.3.2.2 skrll gpio_pin_t bank_pins[8]; 110 1.3.2.2 skrll }; 111 1.3.2.2 skrll 112 1.3.2.2 skrll struct tegra_gpio_softc { 113 1.3.2.2 skrll device_t sc_dev; 114 1.3.2.2 skrll bus_space_tag_t sc_bst; 115 1.3.2.2 skrll bus_space_handle_t sc_bsh; 116 1.3.2.2 skrll 117 1.3.2.2 skrll struct tegra_gpio_bank *sc_banks; 118 1.3.2.2 skrll }; 119 1.3.2.2 skrll 120 1.3.2.2 skrll struct tegra_gpio_pin { 121 1.3.2.2 skrll struct tegra_gpio_softc *pin_sc; 122 1.3.2.2 skrll struct tegra_gpio_bank pin_bank; 123 1.3.2.2 skrll int pin_no; 124 1.3.2.2 skrll u_int pin_flags; 125 1.3.2.3 skrll bool pin_actlo; 126 1.3.2.2 skrll }; 127 1.3.2.2 skrll 128 1.3.2.2 skrll static void tegra_gpio_attach_bank(struct tegra_gpio_softc *, u_int); 129 1.3.2.2 skrll 130 1.3.2.2 skrll static int tegra_gpio_pin_read(void *, int); 131 1.3.2.2 skrll static void tegra_gpio_pin_write(void *, int, int); 132 1.3.2.2 skrll static void tegra_gpio_pin_ctl(void *, int, int); 133 1.3.2.2 skrll 134 1.3.2.2 skrll static int tegra_gpio_cfprint(void *, const char *); 135 1.3.2.2 skrll 136 1.3.2.2 skrll CFATTACH_DECL_NEW(tegra_gpio, sizeof(struct tegra_gpio_softc), 137 1.3.2.2 skrll tegra_gpio_match, tegra_gpio_attach, NULL, NULL); 138 1.3.2.2 skrll 139 1.3.2.2 skrll #define GPIO_WRITE(bank, reg, val) \ 140 1.3.2.2 skrll bus_space_write_4((bank)->bank_sc->sc_bst, \ 141 1.3.2.2 skrll (bank)->bank_sc->sc_bsh, \ 142 1.3.2.2 skrll (bank)->bank_pb->base + (reg), (val)) 143 1.3.2.2 skrll #define GPIO_READ(bank, reg) \ 144 1.3.2.2 skrll bus_space_read_4((bank)->bank_sc->sc_bst, \ 145 1.3.2.2 skrll (bank)->bank_sc->sc_bsh, \ 146 1.3.2.2 skrll (bank)->bank_pb->base + (reg)) 147 1.3.2.2 skrll 148 1.3.2.2 skrll static int 149 1.3.2.2 skrll tegra_gpio_match(device_t parent, cfdata_t cf, void *aux) 150 1.3.2.2 skrll { 151 1.3.2.5 skrll const char * const compatible[] = { 152 1.3.2.5 skrll "nvidia,tegra210-gpio", 153 1.3.2.5 skrll "nvidia,tegra124-gpio", 154 1.3.2.5 skrll "nvidia,tegra30-gpio", 155 1.3.2.5 skrll NULL 156 1.3.2.5 skrll }; 157 1.3.2.3 skrll struct fdt_attach_args * const faa = aux; 158 1.3.2.3 skrll 159 1.3.2.3 skrll return of_match_compatible(faa->faa_phandle, compatible); 160 1.3.2.2 skrll } 161 1.3.2.2 skrll 162 1.3.2.2 skrll static void 163 1.3.2.2 skrll tegra_gpio_attach(device_t parent, device_t self, void *aux) 164 1.3.2.2 skrll { 165 1.3.2.2 skrll struct tegra_gpio_softc * const sc = device_private(self); 166 1.3.2.3 skrll struct fdt_attach_args * const faa = aux; 167 1.3.2.3 skrll bus_addr_t addr; 168 1.3.2.3 skrll bus_size_t size; 169 1.3.2.3 skrll int error; 170 1.3.2.2 skrll u_int n; 171 1.3.2.2 skrll 172 1.3.2.3 skrll if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 173 1.3.2.3 skrll aprint_error(": couldn't get registers\n"); 174 1.3.2.3 skrll return; 175 1.3.2.3 skrll } 176 1.3.2.3 skrll 177 1.3.2.2 skrll sc->sc_dev = self; 178 1.3.2.3 skrll sc->sc_bst = faa->faa_bst; 179 1.3.2.3 skrll error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 180 1.3.2.3 skrll if (error) { 181 1.3.2.3 skrll aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 182 1.3.2.3 skrll return; 183 1.3.2.3 skrll } 184 1.3.2.2 skrll 185 1.3.2.2 skrll aprint_naive("\n"); 186 1.3.2.2 skrll aprint_normal(": GPIO\n"); 187 1.3.2.2 skrll 188 1.3.2.2 skrll const u_int nbank = __arraycount(tegra_gpio_pinbanks); 189 1.3.2.2 skrll sc->sc_banks = kmem_zalloc(sizeof(*sc->sc_banks) * nbank, KM_SLEEP); 190 1.3.2.2 skrll for (n = 0; n < nbank; n++) { 191 1.3.2.2 skrll tegra_gpio_attach_bank(sc, n); 192 1.3.2.2 skrll } 193 1.3.2.3 skrll 194 1.3.2.3 skrll fdtbus_register_gpio_controller(self, faa->faa_phandle, 195 1.3.2.3 skrll &tegra_gpio_funcs); 196 1.3.2.2 skrll } 197 1.3.2.2 skrll 198 1.3.2.2 skrll static void 199 1.3.2.2 skrll tegra_gpio_attach_bank(struct tegra_gpio_softc *sc, u_int bankno) 200 1.3.2.2 skrll { 201 1.3.2.2 skrll struct tegra_gpio_bank *bank = &sc->sc_banks[bankno]; 202 1.3.2.2 skrll struct gpiobus_attach_args gba; 203 1.3.2.2 skrll u_int pin; 204 1.3.2.2 skrll 205 1.3.2.2 skrll bank->bank_sc = sc; 206 1.3.2.2 skrll bank->bank_pb = &tegra_gpio_pinbanks[bankno]; 207 1.3.2.2 skrll bank->bank_gc.gp_cookie = bank; 208 1.3.2.2 skrll bank->bank_gc.gp_pin_read = tegra_gpio_pin_read; 209 1.3.2.2 skrll bank->bank_gc.gp_pin_write = tegra_gpio_pin_write; 210 1.3.2.2 skrll bank->bank_gc.gp_pin_ctl = tegra_gpio_pin_ctl; 211 1.3.2.2 skrll 212 1.3.2.2 skrll const uint32_t cnf = GPIO_READ(bank, GPIO_CNF_REG); 213 1.3.2.2 skrll 214 1.3.2.2 skrll for (pin = 0; pin < __arraycount(bank->bank_pins); pin++) { 215 1.3.2.2 skrll bank->bank_pins[pin].pin_num = pin; 216 1.3.2.2 skrll /* skip pins in SFIO mode */ 217 1.3.2.2 skrll if ((cnf & __BIT(pin)) == 0) 218 1.3.2.2 skrll continue; 219 1.3.2.2 skrll bank->bank_pins[pin].pin_caps = 220 1.3.2.2 skrll GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | 221 1.3.2.2 skrll GPIO_PIN_TRISTATE; 222 1.3.2.2 skrll bank->bank_pins[pin].pin_state = 223 1.3.2.2 skrll tegra_gpio_pin_read(bank, pin); 224 1.3.2.2 skrll } 225 1.3.2.2 skrll 226 1.3.2.2 skrll memset(&gba, 0, sizeof(gba)); 227 1.3.2.2 skrll gba.gba_gc = &bank->bank_gc; 228 1.3.2.2 skrll gba.gba_pins = bank->bank_pins; 229 1.3.2.2 skrll gba.gba_npins = __arraycount(bank->bank_pins); 230 1.3.2.2 skrll 231 1.3.2.2 skrll bank->bank_dev = config_found_ia(sc->sc_dev, "gpiobus", &gba, 232 1.3.2.2 skrll tegra_gpio_cfprint); 233 1.3.2.2 skrll } 234 1.3.2.2 skrll 235 1.3.2.2 skrll static int 236 1.3.2.2 skrll tegra_gpio_cfprint(void *priv, const char *pnp) 237 1.3.2.2 skrll { 238 1.3.2.2 skrll struct gpiobus_attach_args *gba = priv; 239 1.3.2.2 skrll struct tegra_gpio_bank *bank = gba->gba_gc->gp_cookie; 240 1.3.2.2 skrll const char *bankname = bank->bank_pb->name; 241 1.3.2.2 skrll 242 1.3.2.2 skrll if (pnp) 243 1.3.2.2 skrll aprint_normal("gpiobus at %s", pnp); 244 1.3.2.2 skrll 245 1.3.2.2 skrll aprint_normal(" (%s)", bankname); 246 1.3.2.2 skrll 247 1.3.2.2 skrll return UNCONF; 248 1.3.2.2 skrll } 249 1.3.2.2 skrll 250 1.3.2.2 skrll static int 251 1.3.2.2 skrll tegra_gpio_pin_read(void *priv, int pin) 252 1.3.2.2 skrll { 253 1.3.2.2 skrll struct tegra_gpio_bank *bank = priv; 254 1.3.2.2 skrll 255 1.3.2.2 skrll const uint32_t v = GPIO_READ(bank, GPIO_IN_REG); 256 1.3.2.2 skrll 257 1.3.2.2 skrll return (v >> pin) & 1; 258 1.3.2.2 skrll } 259 1.3.2.2 skrll 260 1.3.2.2 skrll static void 261 1.3.2.2 skrll tegra_gpio_pin_write(void *priv, int pin, int val) 262 1.3.2.2 skrll { 263 1.3.2.2 skrll struct tegra_gpio_bank *bank = priv; 264 1.3.2.2 skrll uint32_t v; 265 1.3.2.2 skrll 266 1.3.2.2 skrll v = (1 << (pin + 8)); 267 1.3.2.2 skrll v |= (val << pin); 268 1.3.2.2 skrll GPIO_WRITE(bank, GPIO_MSK_OUT_REG, v); 269 1.3.2.2 skrll } 270 1.3.2.2 skrll 271 1.3.2.2 skrll static void 272 1.3.2.2 skrll tegra_gpio_pin_ctl(void *priv, int pin, int flags) 273 1.3.2.2 skrll { 274 1.3.2.2 skrll struct tegra_gpio_bank *bank = priv; 275 1.3.2.2 skrll uint32_t v; 276 1.3.2.2 skrll 277 1.3.2.2 skrll if (flags & GPIO_PIN_INPUT) { 278 1.3.2.2 skrll v = (1 << (pin + 8)); 279 1.3.2.2 skrll GPIO_WRITE(bank, GPIO_MSK_OE_REG, v); 280 1.3.2.2 skrll } else if (flags & GPIO_PIN_OUTPUT) { 281 1.3.2.2 skrll v = (1 << (pin + 8)); 282 1.3.2.2 skrll v |= (1 << pin); 283 1.3.2.2 skrll GPIO_WRITE(bank, GPIO_MSK_OE_REG, v); 284 1.3.2.2 skrll } 285 1.3.2.2 skrll } 286 1.3.2.2 skrll 287 1.3.2.3 skrll static void * 288 1.3.2.3 skrll tegra_gpio_fdt_acquire(device_t dev, const void *data, size_t len, int flags) 289 1.3.2.3 skrll { 290 1.3.2.3 skrll struct tegra_gpio_bank gbank; 291 1.3.2.3 skrll struct tegra_gpio_pin *gpin; 292 1.3.2.3 skrll const u_int *gpio = data; 293 1.3.2.3 skrll 294 1.3.2.3 skrll if (len != 12) 295 1.3.2.3 skrll return NULL; 296 1.3.2.3 skrll 297 1.3.2.3 skrll const u_int bank = be32toh(gpio[1]) >> 3; 298 1.3.2.3 skrll const u_int pin = be32toh(gpio[1]) & 7; 299 1.3.2.3 skrll const bool actlo = be32toh(gpio[2]) & 1; 300 1.3.2.3 skrll 301 1.3.2.3 skrll if (bank >= __arraycount(tegra_gpio_pinbanks) || pin > 8) 302 1.3.2.3 skrll return NULL; 303 1.3.2.3 skrll 304 1.3.2.3 skrll gbank.bank_sc = device_private(dev); 305 1.3.2.3 skrll gbank.bank_pb = &tegra_gpio_pinbanks[bank]; 306 1.3.2.3 skrll 307 1.3.2.3 skrll const uint32_t cnf = GPIO_READ(&gbank, GPIO_CNF_REG); 308 1.3.2.3 skrll if ((cnf & __BIT(pin)) == 0) 309 1.3.2.3 skrll GPIO_WRITE(&gbank, GPIO_CNF_REG, cnf | __BIT(pin)); 310 1.3.2.3 skrll 311 1.3.2.4 skrll gpin = kmem_zalloc(sizeof(*gpin), KM_SLEEP); 312 1.3.2.3 skrll gpin->pin_bank = gbank; 313 1.3.2.3 skrll gpin->pin_no = pin; 314 1.3.2.3 skrll gpin->pin_flags = flags; 315 1.3.2.3 skrll gpin->pin_actlo = actlo; 316 1.3.2.3 skrll 317 1.3.2.3 skrll tegra_gpio_pin_ctl(&gpin->pin_bank, gpin->pin_no, gpin->pin_flags); 318 1.3.2.3 skrll 319 1.3.2.3 skrll return gpin; 320 1.3.2.3 skrll } 321 1.3.2.3 skrll 322 1.3.2.3 skrll static void 323 1.3.2.3 skrll tegra_gpio_fdt_release(device_t dev, void *priv) 324 1.3.2.3 skrll { 325 1.3.2.3 skrll struct tegra_gpio_pin *gpin = priv; 326 1.3.2.3 skrll 327 1.3.2.3 skrll tegra_gpio_release(gpin); 328 1.3.2.3 skrll } 329 1.3.2.3 skrll 330 1.3.2.3 skrll static int 331 1.3.2.3 skrll tegra_gpio_fdt_read(device_t dev, void *priv, bool raw) 332 1.3.2.3 skrll { 333 1.3.2.3 skrll struct tegra_gpio_pin *gpin = priv; 334 1.3.2.3 skrll int val; 335 1.3.2.3 skrll 336 1.3.2.3 skrll val = tegra_gpio_read(gpin); 337 1.3.2.3 skrll 338 1.3.2.3 skrll if (!raw && gpin->pin_actlo) 339 1.3.2.3 skrll val = !val; 340 1.3.2.3 skrll 341 1.3.2.3 skrll return val; 342 1.3.2.3 skrll } 343 1.3.2.3 skrll 344 1.3.2.3 skrll static void 345 1.3.2.3 skrll tegra_gpio_fdt_write(device_t dev, void *priv, int val, bool raw) 346 1.3.2.3 skrll { 347 1.3.2.3 skrll struct tegra_gpio_pin *gpin = priv; 348 1.3.2.3 skrll 349 1.3.2.3 skrll if (!raw && gpin->pin_actlo) 350 1.3.2.3 skrll val = !val; 351 1.3.2.3 skrll 352 1.3.2.3 skrll tegra_gpio_write(gpin, val); 353 1.3.2.3 skrll } 354 1.3.2.3 skrll 355 1.3.2.2 skrll static const struct tegra_gpio_pinbank * 356 1.3.2.2 skrll tegra_gpio_pin_lookup(const char *pinname, int *ppin) 357 1.3.2.2 skrll { 358 1.3.2.2 skrll char bankname[3]; 359 1.3.2.2 skrll u_int n; 360 1.3.2.2 skrll int pin; 361 1.3.2.2 skrll 362 1.3.2.2 skrll KASSERT(strlen(pinname) == 2 || strlen(pinname) == 3); 363 1.3.2.2 skrll 364 1.3.2.2 skrll memset(bankname, 0, sizeof(bankname)); 365 1.3.2.2 skrll bankname[0] = pinname[0]; 366 1.3.2.2 skrll if (strlen(pinname) == 2) { 367 1.3.2.2 skrll pin = pinname[1] - '0'; 368 1.3.2.2 skrll } else { 369 1.3.2.2 skrll bankname[1] = pinname[1]; 370 1.3.2.2 skrll pin = pinname[2] - '0'; 371 1.3.2.2 skrll } 372 1.3.2.2 skrll 373 1.3.2.2 skrll for (n = 0; n < __arraycount(tegra_gpio_pinbanks); n++) { 374 1.3.2.2 skrll const struct tegra_gpio_pinbank *pb = 375 1.3.2.2 skrll &tegra_gpio_pinbanks[n]; 376 1.3.2.2 skrll if (strcmp(pb->name, bankname) == 0) { 377 1.3.2.2 skrll *ppin = pin; 378 1.3.2.2 skrll return pb; 379 1.3.2.2 skrll } 380 1.3.2.2 skrll } 381 1.3.2.2 skrll 382 1.3.2.2 skrll return NULL; 383 1.3.2.2 skrll } 384 1.3.2.2 skrll 385 1.3.2.2 skrll struct tegra_gpio_pin * 386 1.3.2.2 skrll tegra_gpio_acquire(const char *pinname, u_int flags) 387 1.3.2.2 skrll { 388 1.3.2.2 skrll struct tegra_gpio_bank bank; 389 1.3.2.2 skrll struct tegra_gpio_pin *gpin; 390 1.3.2.2 skrll int pin; 391 1.3.2.2 skrll device_t dev; 392 1.3.2.2 skrll 393 1.3.2.2 skrll dev = device_find_by_driver_unit("tegragpio", 0); 394 1.3.2.2 skrll if (dev == NULL) 395 1.3.2.2 skrll return NULL; 396 1.3.2.2 skrll 397 1.3.2.2 skrll bank.bank_sc = device_private(dev); 398 1.3.2.2 skrll bank.bank_pb = tegra_gpio_pin_lookup(pinname, &pin); 399 1.3.2.2 skrll if (bank.bank_pb == NULL) 400 1.3.2.2 skrll return NULL; 401 1.3.2.2 skrll 402 1.3.2.2 skrll const uint32_t cnf = GPIO_READ(&bank, GPIO_CNF_REG); 403 1.3.2.2 skrll if ((cnf & __BIT(pin)) == 0) 404 1.3.2.2 skrll GPIO_WRITE(&bank, GPIO_CNF_REG, cnf | __BIT(pin)); 405 1.3.2.2 skrll 406 1.3.2.2 skrll gpin = kmem_alloc(sizeof(*gpin), KM_SLEEP); 407 1.3.2.2 skrll gpin->pin_bank = bank; 408 1.3.2.2 skrll gpin->pin_no = pin; 409 1.3.2.2 skrll gpin->pin_flags = flags; 410 1.3.2.2 skrll 411 1.3.2.2 skrll tegra_gpio_pin_ctl(&gpin->pin_bank, gpin->pin_no, gpin->pin_flags); 412 1.3.2.2 skrll 413 1.3.2.2 skrll return gpin; 414 1.3.2.2 skrll } 415 1.3.2.2 skrll 416 1.3.2.2 skrll void 417 1.3.2.2 skrll tegra_gpio_release(struct tegra_gpio_pin *gpin) 418 1.3.2.2 skrll { 419 1.3.2.2 skrll tegra_gpio_pin_ctl(&gpin->pin_bank, gpin->pin_no, GPIO_PIN_INPUT); 420 1.3.2.2 skrll kmem_free(gpin, sizeof(*gpin)); 421 1.3.2.2 skrll } 422 1.3.2.2 skrll 423 1.3.2.2 skrll int 424 1.3.2.2 skrll tegra_gpio_read(struct tegra_gpio_pin *gpin) 425 1.3.2.2 skrll { 426 1.3.2.3 skrll int ret; 427 1.3.2.3 skrll 428 1.3.2.2 skrll if (gpin->pin_flags & GPIO_PIN_INPUT) { 429 1.3.2.3 skrll ret = tegra_gpio_pin_read(&gpin->pin_bank, gpin->pin_no); 430 1.3.2.2 skrll } else { 431 1.3.2.2 skrll const uint32_t v = GPIO_READ(&gpin->pin_bank, GPIO_OUT_REG); 432 1.3.2.3 skrll ret = (v >> gpin->pin_no) & 1; 433 1.3.2.2 skrll } 434 1.3.2.3 skrll 435 1.3.2.3 skrll return ret; 436 1.3.2.2 skrll } 437 1.3.2.2 skrll 438 1.3.2.2 skrll void 439 1.3.2.2 skrll tegra_gpio_write(struct tegra_gpio_pin *gpin, int val) 440 1.3.2.2 skrll { 441 1.3.2.2 skrll KASSERT((gpin->pin_flags & GPIO_PIN_OUTPUT) != 0); 442 1.3.2.3 skrll 443 1.3.2.2 skrll tegra_gpio_pin_write(&gpin->pin_bank, gpin->pin_no, val); 444 1.3.2.2 skrll } 445
Indexes created Thu Oct 02 10:09:58 GMT 2025