Home | History | Annotate | Line # | Download | only in nvidia
tegra_gpio.c revision 1.1 
      1 /* $NetBSD: tegra_gpio.c,v 1.1 2015/05/02 12:08:32 jmcneill Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #include "locators.h"
     30 
     31 #include <sys/cdefs.h>
     32 __KERNEL_RCSID(0, "$NetBSD: tegra_gpio.c,v 1.1 2015/05/02 12:08:32 jmcneill Exp $");
     33 
     34 #include <sys/param.h>
     35 #include <sys/bus.h>
     36 #include <sys/device.h>
     37 #include <sys/intr.h>
     38 #include <sys/systm.h>
     39 #include <sys/kernel.h>
     40 #include <sys/kmem.h>
     41 #include <sys/gpio.h>
     42 
     43 #include <dev/gpio/gpiovar.h>
     44 
     45 #include <arm/nvidia/tegra_reg.h>
     46 #include <arm/nvidia/tegra_gpioreg.h>
     47 #include <arm/nvidia/tegra_var.h>
     48 
     49 const struct tegra_gpio_pinbank {
     50 	const char *name;
     51 	bus_size_t base;
     52 } tegra_gpio_pinbanks [] = {
     53 	{ "A", 0x000 },
     54 	{ "B", 0x004 },
     55 	{ "C", 0x008 },
     56 	{ "D", 0x00c },
     57 	{ "E", 0x100 },
     58 	{ "F", 0x104 },
     59 	{ "G", 0x108 },
     60 	{ "H", 0x10c },
     61 	{ "I", 0x200 },
     62 	{ "J", 0x204 },
     63 	{ "K", 0x208 },
     64 	{ "L", 0x20c },
     65 	{ "M", 0x300 },
     66 	{ "N", 0x304 },
     67 	{ "O", 0x308 },
     68 	{ "P", 0x30c },
     69 	{ "Q", 0x400 },
     70 	{ "R", 0x404 },
     71 	{ "S", 0x408 },
     72 	{ "T", 0x40c },
     73 	{ "U", 0x500 },
     74 	{ "V", 0x504 },
     75 	{ "W", 0x508 },
     76 	{ "X", 0x50c },
     77 	{ "Y", 0x600 },
     78 	{ "Z", 0x604 },
     79 	{ "AA", 0x608 },
     80 	{ "BB", 0x60c },
     81 	{ "CC", 0x700 },
     82 	{ "DD", 0x704 },
     83 	{ "EE", 0x708 }
     84 };
     85 
     86 static int	tegra_gpio_match(device_t, cfdata_t, void *);
     87 static void	tegra_gpio_attach(device_t, device_t, void *);
     88 
     89 struct tegra_gpio_softc;
     90 
     91 struct tegra_gpio_bank {
     92 	struct tegra_gpio_softc *bank_sc;
     93 	const struct tegra_gpio_pinbank *bank_pb;
     94 	device_t		bank_dev;
     95 	struct gpio_chipset_tag	bank_gc;
     96 	gpio_pin_t		bank_pins[8];
     97 };
     98 
     99 struct tegra_gpio_softc {
    100 	device_t		sc_dev;
    101 	bus_space_tag_t		sc_bst;
    102 	bus_space_handle_t	sc_bsh;
    103 
    104 	struct tegra_gpio_bank *sc_banks;
    105 };
    106 
    107 struct tegra_gpio_pin {
    108 	struct tegra_gpio_softc *pin_sc;
    109 	struct tegra_gpio_bank	pin_bank;
    110 	int			pin_no;
    111 	u_int			pin_flags;
    112 };
    113 
    114 static void	tegra_gpio_attach_bank(struct tegra_gpio_softc *, u_int);
    115 
    116 static int	tegra_gpio_pin_read(void *, int);
    117 static void	tegra_gpio_pin_write(void *, int, int);
    118 static void	tegra_gpio_pin_ctl(void *, int, int);
    119 
    120 static int	tegra_gpio_cfprint(void *, const char *);
    121 
    122 CFATTACH_DECL_NEW(tegra_gpio, sizeof(struct tegra_gpio_softc),
    123 	tegra_gpio_match, tegra_gpio_attach, NULL, NULL);
    124 
    125 #define GPIO_WRITE(bank, reg, val) \
    126 	bus_space_write_4((bank)->bank_sc->sc_bst, \
    127 	    (bank)->bank_sc->sc_bsh, \
    128 	    (bank)->bank_pb->base + (reg), (val))
    129 #define GPIO_READ(bank, reg) \
    130 	bus_space_read_4((bank)->bank_sc->sc_bst, \
    131 	    (bank)->bank_sc->sc_bsh, \
    132 	    (bank)->bank_pb->base + (reg))
    133 
    134 static int
    135 tegra_gpio_match(device_t parent, cfdata_t cf, void *aux)
    136 {
    137 	return 1;
    138 }
    139 
    140 static void
    141 tegra_gpio_attach(device_t parent, device_t self, void *aux)
    142 {
    143 	struct tegra_gpio_softc * const sc = device_private(self);
    144 	struct tegraio_attach_args * const tio = aux;
    145 	const struct tegra_locators * const loc = &tio->tio_loc;
    146 	u_int n;
    147 
    148 	sc->sc_dev = self;
    149 	sc->sc_bst = tio->tio_bst;
    150 	bus_space_subregion(tio->tio_bst, tio->tio_bsh,
    151 	    loc->loc_offset, loc->loc_size, &sc->sc_bsh);
    152 
    153 	aprint_naive("\n");
    154 	aprint_normal(": GPIO\n");
    155 
    156 	const u_int nbank = __arraycount(tegra_gpio_pinbanks);
    157 	sc->sc_banks = kmem_zalloc(sizeof(*sc->sc_banks) * nbank, KM_SLEEP);
    158 	for (n = 0; n < nbank; n++) {
    159 		tegra_gpio_attach_bank(sc, n);
    160 	}
    161 }
    162 
    163 static void
    164 tegra_gpio_attach_bank(struct tegra_gpio_softc *sc, u_int bankno)
    165 {
    166 	struct tegra_gpio_bank *bank = &sc->sc_banks[bankno];
    167 	struct gpiobus_attach_args gba;
    168 	u_int pin;
    169 
    170 	bank->bank_sc = sc;
    171 	bank->bank_pb = &tegra_gpio_pinbanks[bankno];
    172 	bank->bank_gc.gp_cookie = bank;
    173 	bank->bank_gc.gp_pin_read = tegra_gpio_pin_read;
    174 	bank->bank_gc.gp_pin_write = tegra_gpio_pin_write;
    175 	bank->bank_gc.gp_pin_ctl = tegra_gpio_pin_ctl;
    176 
    177 	const uint32_t cnf = GPIO_READ(bank, GPIO_CNF_REG);
    178 
    179 	for (pin = 0; pin < __arraycount(bank->bank_pins); pin++) {
    180 		bank->bank_pins[pin].pin_num = pin;
    181 		/* skip pins in SFIO mode */
    182 		if ((cnf & __BIT(pin)) == 0)
    183 			continue;
    184 		bank->bank_pins[pin].pin_caps =
    185 		    GPIO_PIN_INPUT | GPIO_PIN_OUTPUT |
    186 		    GPIO_PIN_TRISTATE;
    187 		bank->bank_pins[pin].pin_state =
    188 		    tegra_gpio_pin_read(bank, pin);
    189 	}
    190 
    191 	memset(&gba, 0, sizeof(gba));
    192 	gba.gba_gc = &bank->bank_gc;
    193 	gba.gba_pins = bank->bank_pins;
    194 	gba.gba_npins = __arraycount(bank->bank_pins);
    195 
    196 	bank->bank_dev = config_found_ia(sc->sc_dev, "gpiobus", &gba,
    197 	    tegra_gpio_cfprint);
    198 }
    199 
    200 static int
    201 tegra_gpio_cfprint(void *priv, const char *pnp)
    202 {
    203 	struct gpiobus_attach_args *gba = priv;
    204 	struct tegra_gpio_bank *bank = gba->gba_gc->gp_cookie;
    205 	const char *bankname = bank->bank_pb->name;
    206 
    207 	if (pnp)
    208 		aprint_normal("gpiobus at %s", pnp);
    209 
    210 	aprint_normal(" (%s)", bankname);
    211 
    212 	return UNCONF;
    213 }
    214 
    215 static int
    216 tegra_gpio_pin_read(void *priv, int pin)
    217 {
    218 	struct tegra_gpio_bank *bank = priv;
    219 
    220 	const uint32_t v = GPIO_READ(bank, GPIO_IN_REG);
    221 
    222 	return (v >> pin) & 1;
    223 }
    224 
    225 static void
    226 tegra_gpio_pin_write(void *priv, int pin, int val)
    227 {
    228 	struct tegra_gpio_bank *bank = priv;
    229 	uint32_t v;
    230 
    231 	v = (1 << (pin + 8));
    232 	v |= (val << pin);
    233 	GPIO_WRITE(bank, GPIO_MSK_OUT_REG, v);
    234 }
    235 
    236 static void
    237 tegra_gpio_pin_ctl(void *priv, int pin, int flags)
    238 {
    239 	struct tegra_gpio_bank *bank = priv;
    240 	uint32_t v;
    241 
    242 	if (flags & GPIO_PIN_INPUT) {
    243 		v = (1 << (pin + 8));
    244 		GPIO_WRITE(bank, GPIO_MSK_OE_REG, v);
    245 	} else if (flags & GPIO_PIN_OUTPUT) {
    246 		v = (1 << (pin + 8));
    247 		v |= (1 << pin);
    248 		GPIO_WRITE(bank, GPIO_MSK_OE_REG, v);
    249 	}
    250 }
    251 
    252 static const struct tegra_gpio_pinbank *
    253 tegra_gpio_pinbank_lookup(const char *bankname)
    254 {
    255 	u_int n;
    256 
    257 	for (n = 0; n < __arraycount(tegra_gpio_pinbanks); n++) {
    258 		const struct tegra_gpio_pinbank *pb =
    259 		    &tegra_gpio_pinbanks[n];
    260 		if (strcmp(pb->name, bankname) == 0)
    261 			return pb;
    262 	}
    263 
    264 	return NULL;
    265 }
    266 
    267 struct tegra_gpio_pin *
    268 tegra_gpio_acquire(const char *bankname, int pin, u_int flags)
    269 {
    270 	struct tegra_gpio_bank bank;
    271 	struct tegra_gpio_pin *gpin;
    272 	device_t dev;
    273 
    274 	dev = device_find_by_driver_unit("tegragpio", 0);
    275 	if (dev == NULL)
    276 		return NULL;
    277 
    278 	bank.bank_sc = device_private(dev);
    279 	bank.bank_pb = tegra_gpio_pinbank_lookup(bankname);
    280 	if (bank.bank_pb == NULL)
    281 		return NULL;
    282 
    283 	const uint32_t cnf = GPIO_READ(&bank, GPIO_CNF_REG);
    284 	if ((cnf & __BIT(pin)) == 0)
    285 		return NULL;
    286 
    287 	gpin = kmem_alloc(sizeof(*gpin), KM_SLEEP);
    288 	gpin->pin_bank = bank;
    289 	gpin->pin_no = pin;
    290 	gpin->pin_flags = flags;
    291 
    292 	tegra_gpio_pin_ctl(&gpin->pin_bank, gpin->pin_no, gpin->pin_flags);
    293 
    294 	return gpin;
    295 }
    296 
    297 void
    298 tegra_gpio_release(struct tegra_gpio_pin *gpin)
    299 {
    300 	tegra_gpio_pin_ctl(&gpin->pin_bank, gpin->pin_no, GPIO_PIN_INPUT);
    301 	kmem_free(gpin, sizeof(*gpin));
    302 }
    303 
    304 int
    305 tegra_gpio_read(struct tegra_gpio_pin *gpin)
    306 {
    307 	if (gpin->pin_flags & GPIO_PIN_INPUT) {
    308 		return tegra_gpio_pin_read(&gpin->pin_bank, gpin->pin_no);
    309 	} else {
    310 		const uint32_t v = GPIO_READ(&gpin->pin_bank, GPIO_OUT_REG);
    311 		return (v >> gpin->pin_no) & 1;
    312 	}
    313 }
    314 
    315 void
    316 tegra_gpio_write(struct tegra_gpio_pin *gpin, int val)
    317 {
    318 	KASSERT((gpin->pin_flags & GPIO_PIN_OUTPUT) != 0);
    319 	tegra_gpio_pin_write(&gpin->pin_bank, gpin->pin_no, val);
    320 }
    321