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tegra_gpio.c revision 1.8.8.2 
      1 /* $NetBSD: tegra_gpio.c,v 1.8.8.2 2017/12/03 11:35:54 jdolecek Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #include <sys/cdefs.h>
     30 __KERNEL_RCSID(0, "$NetBSD: tegra_gpio.c,v 1.8.8.2 2017/12/03 11:35:54 jdolecek Exp $");
     31 
     32 #include <sys/param.h>
     33 #include <sys/bus.h>
     34 #include <sys/device.h>
     35 #include <sys/intr.h>
     36 #include <sys/systm.h>
     37 #include <sys/kernel.h>
     38 #include <sys/kmem.h>
     39 #include <sys/gpio.h>
     40 
     41 #include <dev/gpio/gpiovar.h>
     42 
     43 #include <arm/nvidia/tegra_reg.h>
     44 #include <arm/nvidia/tegra_gpioreg.h>
     45 #include <arm/nvidia/tegra_var.h>
     46 
     47 #include <dev/fdt/fdtvar.h>
     48 
     49 const struct tegra_gpio_pinbank {
     50 	const char *name;
     51 	bus_size_t base;
     52 } tegra_gpio_pinbanks [] = {
     53 	{ "A", 0x000 },
     54 	{ "B", 0x004 },
     55 	{ "C", 0x008 },
     56 	{ "D", 0x00c },
     57 	{ "E", 0x100 },
     58 	{ "F", 0x104 },
     59 	{ "G", 0x108 },
     60 	{ "H", 0x10c },
     61 	{ "I", 0x200 },
     62 	{ "J", 0x204 },
     63 	{ "K", 0x208 },
     64 	{ "L", 0x20c },
     65 	{ "M", 0x300 },
     66 	{ "N", 0x304 },
     67 	{ "O", 0x308 },
     68 	{ "P", 0x30c },
     69 	{ "Q", 0x400 },
     70 	{ "R", 0x404 },
     71 	{ "S", 0x408 },
     72 	{ "T", 0x40c },
     73 	{ "U", 0x500 },
     74 	{ "V", 0x504 },
     75 	{ "W", 0x508 },
     76 	{ "X", 0x50c },
     77 	{ "Y", 0x600 },
     78 	{ "Z", 0x604 },
     79 	{ "AA", 0x608 },
     80 	{ "BB", 0x60c },
     81 	{ "CC", 0x700 },
     82 	{ "DD", 0x704 },
     83 	{ "EE", 0x708 }
     84 };
     85 
     86 static int	tegra_gpio_match(device_t, cfdata_t, void *);
     87 static void	tegra_gpio_attach(device_t, device_t, void *);
     88 
     89 static void *	tegra_gpio_fdt_acquire(device_t, const void *,
     90 		    size_t, int);
     91 static void	tegra_gpio_fdt_release(device_t, void *);
     92 static int	tegra_gpio_fdt_read(device_t, void *, bool);
     93 static void	tegra_gpio_fdt_write(device_t, void *, int, bool);
     94 
     95 struct fdtbus_gpio_controller_func tegra_gpio_funcs = {
     96 	.acquire = tegra_gpio_fdt_acquire,
     97 	.release = tegra_gpio_fdt_release,
     98 	.read = tegra_gpio_fdt_read,
     99 	.write = tegra_gpio_fdt_write
    100 };
    101 
    102 struct tegra_gpio_softc;
    103 
    104 struct tegra_gpio_bank {
    105 	struct tegra_gpio_softc *bank_sc;
    106 	const struct tegra_gpio_pinbank *bank_pb;
    107 	device_t		bank_dev;
    108 	struct gpio_chipset_tag	bank_gc;
    109 	gpio_pin_t		bank_pins[8];
    110 };
    111 
    112 struct tegra_gpio_softc {
    113 	device_t		sc_dev;
    114 	bus_space_tag_t		sc_bst;
    115 	bus_space_handle_t	sc_bsh;
    116 
    117 	struct tegra_gpio_bank *sc_banks;
    118 };
    119 
    120 struct tegra_gpio_pin {
    121 	struct tegra_gpio_softc *pin_sc;
    122 	struct tegra_gpio_bank	pin_bank;
    123 	int			pin_no;
    124 	u_int			pin_flags;
    125 	bool			pin_actlo;
    126 };
    127 
    128 static void	tegra_gpio_attach_bank(struct tegra_gpio_softc *, u_int);
    129 
    130 static int	tegra_gpio_pin_read(void *, int);
    131 static void	tegra_gpio_pin_write(void *, int, int);
    132 static void	tegra_gpio_pin_ctl(void *, int, int);
    133 
    134 static int	tegra_gpio_cfprint(void *, const char *);
    135 
    136 CFATTACH_DECL_NEW(tegra_gpio, sizeof(struct tegra_gpio_softc),
    137 	tegra_gpio_match, tegra_gpio_attach, NULL, NULL);
    138 
    139 #define GPIO_WRITE(bank, reg, val) \
    140 	bus_space_write_4((bank)->bank_sc->sc_bst, \
    141 	    (bank)->bank_sc->sc_bsh, \
    142 	    (bank)->bank_pb->base + (reg), (val))
    143 #define GPIO_READ(bank, reg) \
    144 	bus_space_read_4((bank)->bank_sc->sc_bst, \
    145 	    (bank)->bank_sc->sc_bsh, \
    146 	    (bank)->bank_pb->base + (reg))
    147 
    148 static int
    149 tegra_gpio_match(device_t parent, cfdata_t cf, void *aux)
    150 {
    151 	const char * const compatible[] = {
    152 		"nvidia,tegra210-gpio",
    153 		"nvidia,tegra124-gpio",
    154 		"nvidia,tegra30-gpio",
    155 		NULL
    156 	};
    157 	struct fdt_attach_args * const faa = aux;
    158 
    159 	return of_match_compatible(faa->faa_phandle, compatible);
    160 }
    161 
    162 static void
    163 tegra_gpio_attach(device_t parent, device_t self, void *aux)
    164 {
    165 	struct tegra_gpio_softc * const sc = device_private(self);
    166 	struct fdt_attach_args * const faa = aux;
    167 	bus_addr_t addr;
    168 	bus_size_t size;
    169 	int error;
    170 	u_int n;
    171 
    172 	if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) {
    173 		aprint_error(": couldn't get registers\n");
    174 		return;
    175 	}
    176 
    177 	sc->sc_dev = self;
    178 	sc->sc_bst = faa->faa_bst;
    179 	error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
    180 	if (error) {
    181 		aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error);
    182 		return;
    183 	}
    184 
    185 	aprint_naive("\n");
    186 	aprint_normal(": GPIO\n");
    187 
    188 	const u_int nbank = __arraycount(tegra_gpio_pinbanks);
    189 	sc->sc_banks = kmem_zalloc(sizeof(*sc->sc_banks) * nbank, KM_SLEEP);
    190 	for (n = 0; n < nbank; n++) {
    191 		tegra_gpio_attach_bank(sc, n);
    192 	}
    193 
    194 	fdtbus_register_gpio_controller(self, faa->faa_phandle,
    195 	    &tegra_gpio_funcs);
    196 }
    197 
    198 static void
    199 tegra_gpio_attach_bank(struct tegra_gpio_softc *sc, u_int bankno)
    200 {
    201 	struct tegra_gpio_bank *bank = &sc->sc_banks[bankno];
    202 	struct gpiobus_attach_args gba;
    203 	u_int pin;
    204 
    205 	bank->bank_sc = sc;
    206 	bank->bank_pb = &tegra_gpio_pinbanks[bankno];
    207 	bank->bank_gc.gp_cookie = bank;
    208 	bank->bank_gc.gp_pin_read = tegra_gpio_pin_read;
    209 	bank->bank_gc.gp_pin_write = tegra_gpio_pin_write;
    210 	bank->bank_gc.gp_pin_ctl = tegra_gpio_pin_ctl;
    211 
    212 	const uint32_t cnf = GPIO_READ(bank, GPIO_CNF_REG);
    213 
    214 	for (pin = 0; pin < __arraycount(bank->bank_pins); pin++) {
    215 		bank->bank_pins[pin].pin_num = pin;
    216 		/* skip pins in SFIO mode */
    217 		if ((cnf & __BIT(pin)) == 0)
    218 			continue;
    219 		bank->bank_pins[pin].pin_caps =
    220 		    GPIO_PIN_INPUT | GPIO_PIN_OUTPUT |
    221 		    GPIO_PIN_TRISTATE;
    222 		bank->bank_pins[pin].pin_state =
    223 		    tegra_gpio_pin_read(bank, pin);
    224 	}
    225 
    226 	memset(&gba, 0, sizeof(gba));
    227 	gba.gba_gc = &bank->bank_gc;
    228 	gba.gba_pins = bank->bank_pins;
    229 	gba.gba_npins = __arraycount(bank->bank_pins);
    230 
    231 	bank->bank_dev = config_found_ia(sc->sc_dev, "gpiobus", &gba,
    232 	    tegra_gpio_cfprint);
    233 }
    234 
    235 static int
    236 tegra_gpio_cfprint(void *priv, const char *pnp)
    237 {
    238 	struct gpiobus_attach_args *gba = priv;
    239 	struct tegra_gpio_bank *bank = gba->gba_gc->gp_cookie;
    240 	const char *bankname = bank->bank_pb->name;
    241 
    242 	if (pnp)
    243 		aprint_normal("gpiobus at %s", pnp);
    244 
    245 	aprint_normal(" (%s)", bankname);
    246 
    247 	return UNCONF;
    248 }
    249 
    250 static int
    251 tegra_gpio_pin_read(void *priv, int pin)
    252 {
    253 	struct tegra_gpio_bank *bank = priv;
    254 
    255 	const uint32_t v = GPIO_READ(bank, GPIO_IN_REG);
    256 
    257 	return (v >> pin) & 1;
    258 }
    259 
    260 static void
    261 tegra_gpio_pin_write(void *priv, int pin, int val)
    262 {
    263 	struct tegra_gpio_bank *bank = priv;
    264 	uint32_t v;
    265 
    266 	v = (1 << (pin + 8));
    267 	v |= (val << pin);
    268 	GPIO_WRITE(bank, GPIO_MSK_OUT_REG, v);
    269 }
    270 
    271 static void
    272 tegra_gpio_pin_ctl(void *priv, int pin, int flags)
    273 {
    274 	struct tegra_gpio_bank *bank = priv;
    275 	uint32_t v;
    276 
    277 	if (flags & GPIO_PIN_INPUT) {
    278 		v = (1 << (pin + 8));
    279 		GPIO_WRITE(bank, GPIO_MSK_OE_REG, v);
    280 	} else if (flags & GPIO_PIN_OUTPUT) {
    281 		v = (1 << (pin + 8));
    282 		v |= (1 << pin);
    283 		GPIO_WRITE(bank, GPIO_MSK_OE_REG, v);
    284 	}
    285 }
    286 
    287 static void *
    288 tegra_gpio_fdt_acquire(device_t dev, const void *data, size_t len, int flags)
    289 {
    290 	struct tegra_gpio_bank gbank;
    291 	struct tegra_gpio_pin *gpin;
    292 	const u_int *gpio = data;
    293 
    294 	if (len != 12)
    295 		return NULL;
    296 
    297 	const u_int bank = be32toh(gpio[1]) >> 3;
    298 	const u_int pin = be32toh(gpio[1]) & 7;
    299 	const bool actlo = be32toh(gpio[2]) & 1;
    300 
    301 	if (bank >= __arraycount(tegra_gpio_pinbanks) || pin > 8)
    302 		return NULL;
    303 
    304 	gbank.bank_sc = device_private(dev);
    305 	gbank.bank_pb = &tegra_gpio_pinbanks[bank];
    306 
    307 	const uint32_t cnf = GPIO_READ(&gbank, GPIO_CNF_REG);
    308 	if ((cnf & __BIT(pin)) == 0)
    309 		GPIO_WRITE(&gbank, GPIO_CNF_REG, cnf | __BIT(pin));
    310 
    311 	gpin = kmem_zalloc(sizeof(*gpin), KM_SLEEP);
    312 	gpin->pin_bank = gbank;
    313 	gpin->pin_no = pin;
    314 	gpin->pin_flags = flags;
    315 	gpin->pin_actlo = actlo;
    316 
    317 	tegra_gpio_pin_ctl(&gpin->pin_bank, gpin->pin_no, gpin->pin_flags);
    318 
    319 	return gpin;
    320 }
    321 
    322 static void
    323 tegra_gpio_fdt_release(device_t dev, void *priv)
    324 {
    325 	struct tegra_gpio_pin *gpin = priv;
    326 
    327 	tegra_gpio_release(gpin);
    328 }
    329 
    330 static int
    331 tegra_gpio_fdt_read(device_t dev, void *priv, bool raw)
    332 {
    333 	struct tegra_gpio_pin *gpin = priv;
    334 	int val;
    335 
    336 	val = tegra_gpio_read(gpin);
    337 
    338 	if (!raw && gpin->pin_actlo)
    339 		val = !val;
    340 
    341 	return val;
    342 }
    343 
    344 static void
    345 tegra_gpio_fdt_write(device_t dev, void *priv, int val, bool raw)
    346 {
    347 	struct tegra_gpio_pin *gpin = priv;
    348 
    349 	if (!raw && gpin->pin_actlo)
    350 		val = !val;
    351 
    352 	tegra_gpio_write(gpin, val);
    353 }
    354 
    355 static const struct tegra_gpio_pinbank *
    356 tegra_gpio_pin_lookup(const char *pinname, int *ppin)
    357 {
    358 	char bankname[3];
    359 	u_int n;
    360 	int pin;
    361 
    362 	KASSERT(strlen(pinname) == 2 || strlen(pinname) == 3);
    363 
    364 	memset(bankname, 0, sizeof(bankname));
    365 	bankname[0] = pinname[0];
    366 	if (strlen(pinname) == 2) {
    367 		pin = pinname[1] - '0';
    368 	} else {
    369 		bankname[1] = pinname[1];
    370 		pin = pinname[2] - '0';
    371 	}
    372 
    373 	for (n = 0; n < __arraycount(tegra_gpio_pinbanks); n++) {
    374 		const struct tegra_gpio_pinbank *pb =
    375 		    &tegra_gpio_pinbanks[n];
    376 		if (strcmp(pb->name, bankname) == 0) {
    377 			*ppin = pin;
    378 			return pb;
    379 		}
    380 	}
    381 
    382 	return NULL;
    383 }
    384 
    385 struct tegra_gpio_pin *
    386 tegra_gpio_acquire(const char *pinname, u_int flags)
    387 {
    388 	struct tegra_gpio_bank bank;
    389 	struct tegra_gpio_pin *gpin;
    390 	int pin;
    391 	device_t dev;
    392 
    393 	dev = device_find_by_driver_unit("tegragpio", 0);
    394 	if (dev == NULL)
    395 		return NULL;
    396 
    397 	bank.bank_sc = device_private(dev);
    398 	bank.bank_pb = tegra_gpio_pin_lookup(pinname, &pin);
    399 	if (bank.bank_pb == NULL)
    400 		return NULL;
    401 
    402 	const uint32_t cnf = GPIO_READ(&bank, GPIO_CNF_REG);
    403 	if ((cnf & __BIT(pin)) == 0)
    404 		GPIO_WRITE(&bank, GPIO_CNF_REG, cnf | __BIT(pin));
    405 
    406 	gpin = kmem_alloc(sizeof(*gpin), KM_SLEEP);
    407 	gpin->pin_bank = bank;
    408 	gpin->pin_no = pin;
    409 	gpin->pin_flags = flags;
    410 
    411 	tegra_gpio_pin_ctl(&gpin->pin_bank, gpin->pin_no, gpin->pin_flags);
    412 
    413 	return gpin;
    414 }
    415 
    416 void
    417 tegra_gpio_release(struct tegra_gpio_pin *gpin)
    418 {
    419 	tegra_gpio_pin_ctl(&gpin->pin_bank, gpin->pin_no, GPIO_PIN_INPUT);
    420 	kmem_free(gpin, sizeof(*gpin));
    421 }
    422 
    423 int
    424 tegra_gpio_read(struct tegra_gpio_pin *gpin)
    425 {
    426 	int ret;
    427 
    428 	if (gpin->pin_flags & GPIO_PIN_INPUT) {
    429 		ret = tegra_gpio_pin_read(&gpin->pin_bank, gpin->pin_no);
    430 	} else {
    431 		const uint32_t v = GPIO_READ(&gpin->pin_bank, GPIO_OUT_REG);
    432 		ret = (v >> gpin->pin_no) & 1;
    433 	}
    434 
    435 	return ret;
    436 }
    437 
    438 void
    439 tegra_gpio_write(struct tegra_gpio_pin *gpin, int val)
    440 {
    441 	KASSERT((gpin->pin_flags & GPIO_PIN_OUTPUT) != 0);
    442 
    443 	tegra_gpio_pin_write(&gpin->pin_bank, gpin->pin_no, val);
    444 }
    445