1 1.1 jmcneill /* $NetBSD: tegra_gpioreg.h,v 1.1 2015/05/02 12:08:32 jmcneill Exp $ */ 2 1.1 jmcneill 3 1.1 jmcneill /*- 4 1.1 jmcneill * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 1.1 jmcneill * All rights reserved. 6 1.1 jmcneill * 7 1.1 jmcneill * Redistribution and use in source and binary forms, with or without 8 1.1 jmcneill * modification, are permitted provided that the following conditions 9 1.1 jmcneill * are met: 10 1.1 jmcneill * 1. Redistributions of source code must retain the above copyright 11 1.1 jmcneill * notice, this list of conditions and the following disclaimer. 12 1.1 jmcneill * 2. Redistributions in binary form must reproduce the above copyright 13 1.1 jmcneill * notice, this list of conditions and the following disclaimer in the 14 1.1 jmcneill * documentation and/or other materials provided with the distribution. 15 1.1 jmcneill * 16 1.1 jmcneill * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 1.1 jmcneill * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 1.1 jmcneill * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 1.1 jmcneill * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 1.1 jmcneill * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 1.1 jmcneill * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 1.1 jmcneill * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 1.1 jmcneill * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 1.1 jmcneill * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.1 jmcneill * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.1 jmcneill * SUCH DAMAGE. 27 1.1 jmcneill */ 28 1.1 jmcneill 29 1.1 jmcneill #ifndef _ARM_TEGRA_GPIOREG_H 30 1.1 jmcneill #define _ARM_TEGRA_GPIOREG_H 31 1.1 jmcneill 32 1.1 jmcneill #define GPIO_BANK_OFFSET(n) (4 * (n)) 33 1.1 jmcneill 34 1.1 jmcneill #define GPIO_CNF_REG 0x000 35 1.1 jmcneill #define GPIO_OE_REG 0x010 36 1.1 jmcneill #define GPIO_OUT_REG 0x020 37 1.1 jmcneill #define GPIO_IN_REG 0x030 38 1.1 jmcneill #define GPIO_INT_STA_REG 0x040 39 1.1 jmcneill #define GPIO_INT_ENB_REG 0x050 40 1.1 jmcneill #define GPIO_INT_LVL_REG 0x060 41 1.1 jmcneill #define GPIO_INT_CLR_REG 0x070 42 1.1 jmcneill 43 1.1 jmcneill #define GPIO_MSK_CNF_REG 0x080 44 1.1 jmcneill #define GPIO_MSK_OE_REG 0x090 45 1.1 jmcneill #define GPIO_MSK_OUT_REG 0x0a0 46 1.1 jmcneill #define GPIO_MSK_INT_STA_REG 0x0c0 47 1.1 jmcneill #define GPIO_MSK_INT_ENB_REG 0x0d0 48 1.1 jmcneill #define GPIO_MSK_INT_CLR_REG 0x0e0 49 1.1 jmcneill 50 1.1 jmcneill #define GPIO_CNF_LOCK __BITS(15,8) 51 1.1 jmcneill #define GPIO_CNF_MODE __BITS(7,0) 52 1.1 jmcneill 53 1.1 jmcneill #endif /* _ARM_TEGRA_GPIOREG_H */ 54
Indexes created Sat Sep 27 22:09:54 GMT 2025