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tegra_gpioreg.h revision 1.1 
      1 /* $NetBSD: tegra_gpioreg.h,v 1.1 2015/05/02 12:08:32 jmcneill Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #ifndef _ARM_TEGRA_GPIOREG_H
     30 #define _ARM_TEGRA_GPIOREG_H
     31 
     32 #define GPIO_BANK_OFFSET(n)	(4 * (n))
     33 
     34 #define GPIO_CNF_REG		0x000
     35 #define GPIO_OE_REG		0x010
     36 #define GPIO_OUT_REG		0x020
     37 #define GPIO_IN_REG		0x030
     38 #define GPIO_INT_STA_REG	0x040
     39 #define GPIO_INT_ENB_REG	0x050
     40 #define GPIO_INT_LVL_REG	0x060
     41 #define GPIO_INT_CLR_REG	0x070
     42 
     43 #define GPIO_MSK_CNF_REG	0x080
     44 #define GPIO_MSK_OE_REG		0x090
     45 #define GPIO_MSK_OUT_REG	0x0a0
     46 #define GPIO_MSK_INT_STA_REG	0x0c0
     47 #define GPIO_MSK_INT_ENB_REG	0x0d0
     48 #define GPIO_MSK_INT_CLR_REG	0x0e0
     49 
     50 #define GPIO_CNF_LOCK		__BITS(15,8)
     51 #define GPIO_CNF_MODE		__BITS(7,0)
     52 
     53 #endif /* _ARM_TEGRA_GPIOREG_H */
     54