tegra_hdaudio.c revision 1.7.2.1
1 /* $NetBSD: tegra_hdaudio.c,v 1.7.2.1 2017/04/26 02:53:01 pgoyette Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_hdaudio.c,v 1.7.2.1 2017/04/26 02:53:01 pgoyette Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 39 #include <dev/hdaudio/hdaudioreg.h> 40 #include <dev/hdaudio/hdaudiovar.h> 41 42 #include <arm/nvidia/tegra_var.h> 43 #include <arm/nvidia/tegra_pmcreg.h> 44 #include <arm/nvidia/tegra_hdaudioreg.h> 45 46 #include <dev/fdt/fdtvar.h> 47 48 #define TEGRA_HDAUDIO_OFFSET 0x8000 49 50 #define TEGRA_HDA_IFPS_BAR0_REG 0x0080 51 #define TEGRA_HDA_IFPS_CONFIG_REG 0x0180 52 #define TEGRA_HDA_IFPS_INTR_REG 0x0188 53 #define TEGRA_HDA_CFG_CMD_REG 0x1004 54 #define TEGRA_HDA_CFG_BAR0_REG 0x1010 55 56 static int tegra_hdaudio_match(device_t, cfdata_t, void *); 57 static void tegra_hdaudio_attach(device_t, device_t, void *); 58 static int tegra_hdaudio_detach(device_t, int); 59 static int tegra_hdaudio_rescan(device_t, const char *, const int *); 60 static void tegra_hdaudio_childdet(device_t, device_t); 61 62 static int tegra_hdaudio_intr(void *); 63 64 struct tegra_hdaudio_softc { 65 struct hdaudio_softc sc; 66 bus_space_tag_t sc_bst; 67 bus_space_handle_t sc_bsh; 68 void *sc_ih; 69 int sc_phandle; 70 struct clk *sc_clk_hda; 71 struct clk *sc_clk_hda2hdmi; 72 struct clk *sc_clk_hda2codec_2x; 73 struct fdtbus_reset *sc_rst_hda; 74 struct fdtbus_reset *sc_rst_hda2hdmi; 75 struct fdtbus_reset *sc_rst_hda2codec_2x; 76 }; 77 78 static int tegra_hdaudio_init_clocks(struct tegra_hdaudio_softc *); 79 static void tegra_hdaudio_init(struct tegra_hdaudio_softc *); 80 81 CFATTACH_DECL2_NEW(tegra_hdaudio, sizeof(struct tegra_hdaudio_softc), 82 tegra_hdaudio_match, tegra_hdaudio_attach, tegra_hdaudio_detach, NULL, 83 tegra_hdaudio_rescan, tegra_hdaudio_childdet); 84 85 static int 86 tegra_hdaudio_match(device_t parent, cfdata_t cf, void *aux) 87 { 88 const char * const compatible[] = { "nvidia,tegra124-hda", NULL }; 89 struct fdt_attach_args * const faa = aux; 90 91 return of_match_compatible(faa->faa_phandle, compatible); 92 } 93 94 static void 95 tegra_hdaudio_attach(device_t parent, device_t self, void *aux) 96 { 97 struct tegra_hdaudio_softc * const sc = device_private(self); 98 struct fdt_attach_args * const faa = aux; 99 const int phandle = faa->faa_phandle; 100 char intrstr[128]; 101 bus_addr_t addr; 102 bus_size_t size; 103 int error; 104 105 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 106 aprint_error(": couldn't get registers\n"); 107 return; 108 } 109 sc->sc_clk_hda = fdtbus_clock_get(phandle, "hda"); 110 if (sc->sc_clk_hda == NULL) { 111 aprint_error(": couldn't get clock hda\n"); 112 return; 113 } 114 sc->sc_clk_hda2hdmi = fdtbus_clock_get(phandle, "hda2hdmi"); 115 if (sc->sc_clk_hda2hdmi == NULL) { 116 aprint_error(": couldn't get clock hda2hdmi\n"); 117 return; 118 } 119 sc->sc_clk_hda2codec_2x = fdtbus_clock_get(phandle, "hda2codec_2x"); 120 if (sc->sc_clk_hda2codec_2x == NULL) { 121 aprint_error(": couldn't get clock hda2codec_2x\n"); 122 return; 123 } 124 sc->sc_rst_hda = fdtbus_reset_get(phandle, "hda"); 125 if (sc->sc_rst_hda == NULL) { 126 aprint_error(": couldn't get reset hda\n"); 127 return; 128 } 129 sc->sc_rst_hda2hdmi = fdtbus_reset_get(phandle, "hda2hdmi"); 130 if (sc->sc_rst_hda2hdmi == NULL) { 131 aprint_error(": couldn't get reset hda2hdmi\n"); 132 return; 133 } 134 sc->sc_rst_hda2codec_2x = fdtbus_reset_get(phandle, "hda2codec_2x"); 135 if (sc->sc_rst_hda2codec_2x == NULL) { 136 aprint_error(": couldn't get reset hda2codec_2x\n"); 137 return; 138 } 139 140 sc->sc_phandle = phandle; 141 sc->sc_bst = faa->faa_bst; 142 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 143 if (error) { 144 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 145 return; 146 } 147 148 sc->sc.sc_dev = self; 149 sc->sc.sc_memt = faa->faa_bst; 150 bus_space_subregion(sc->sc.sc_memt, sc->sc_bsh, TEGRA_HDAUDIO_OFFSET, 151 size - TEGRA_HDAUDIO_OFFSET, &sc->sc.sc_memh); 152 sc->sc.sc_memvalid = true; 153 sc->sc.sc_dmat = faa->faa_dmat; 154 155 aprint_naive("\n"); 156 aprint_normal(": HDA\n"); 157 158 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 159 aprint_error_dev(self, "failed to decode interrupt\n"); 160 return; 161 } 162 163 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_AUDIO, 0, 164 tegra_hdaudio_intr, sc); 165 if (sc->sc_ih == NULL) { 166 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 167 intrstr); 168 return; 169 } 170 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 171 172 tegra_pmc_power(PMC_PARTID_DISB, true); 173 174 if (tegra_hdaudio_init_clocks(sc) != 0) 175 return; 176 177 tegra_hdaudio_init(sc); 178 179 hdaudio_attach(self, &sc->sc); 180 } 181 182 static int 183 tegra_hdaudio_init_clocks(struct tegra_hdaudio_softc *sc) 184 { 185 device_t self = sc->sc.sc_dev; 186 int error; 187 188 /* Assert resets */ 189 fdtbus_reset_assert(sc->sc_rst_hda); 190 fdtbus_reset_assert(sc->sc_rst_hda2hdmi); 191 fdtbus_reset_assert(sc->sc_rst_hda2codec_2x); 192 193 /* Set hda to 48MHz and enable it */ 194 error = clk_set_rate(sc->sc_clk_hda, 48000000); 195 if (error) { 196 aprint_error_dev(self, "couldn't set hda frequency: %d\n", 197 error); 198 return error; 199 } 200 error = clk_enable(sc->sc_clk_hda); 201 if (error) { 202 aprint_error_dev(self, "couldn't enable clock hda: %d\n", 203 error); 204 return error; 205 } 206 207 /* Enable hda2hdmi clock */ 208 error = clk_enable(sc->sc_clk_hda2hdmi); 209 if (error) { 210 aprint_error_dev(self, "couldn't enable clock hda2hdmi: %d\n", 211 error); 212 return error; 213 } 214 215 /* Set hda2codec_2x to 48MHz and enable it */ 216 error = clk_set_rate(sc->sc_clk_hda2codec_2x, 48000000); 217 if (error) { 218 aprint_error_dev(self, 219 "couldn't set clock hda2codec_2x frequency: %d\n", error); 220 return error; 221 } 222 error = clk_enable(sc->sc_clk_hda2codec_2x); 223 if (error) { 224 aprint_error_dev(self, 225 "couldn't enable clock hda2codec_2x: %d\n", error); 226 return error; 227 } 228 229 /* De-assert resets */ 230 fdtbus_reset_deassert(sc->sc_rst_hda); 231 fdtbus_reset_deassert(sc->sc_rst_hda2hdmi); 232 fdtbus_reset_deassert(sc->sc_rst_hda2codec_2x); 233 234 return 0; 235 } 236 237 static void 238 tegra_hdaudio_init(struct tegra_hdaudio_softc *sc) 239 { 240 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, TEGRA_HDA_IFPS_CONFIG_REG, 241 TEGRA_HDA_IFPS_CONFIG_FPCI_EN, 0); 242 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, TEGRA_HDA_CFG_CMD_REG, 243 TEGRA_HDA_CFG_CMD_ENABLE_SERR | 244 TEGRA_HDA_CFG_CMD_BUS_MASTER | 245 TEGRA_HDA_CFG_CMD_MEM_SPACE | 246 TEGRA_HDA_CFG_CMD_IO_SPACE, 247 TEGRA_HDA_CFG_CMD_DISABLE_INTR); 248 bus_space_write_4(sc->sc_bst, sc->sc_bsh, TEGRA_HDA_CFG_BAR0_REG, 249 0xffffffff); 250 bus_space_write_4(sc->sc_bst, sc->sc_bsh, TEGRA_HDA_CFG_BAR0_REG, 251 0x00004000); 252 bus_space_write_4(sc->sc_bst, sc->sc_bsh, TEGRA_HDA_IFPS_BAR0_REG, 253 TEGRA_HDA_CFG_BAR0_START); 254 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, TEGRA_HDA_IFPS_INTR_REG, 255 TEGRA_HDA_IFPS_INTR_EN, 0); 256 } 257 258 static int 259 tegra_hdaudio_detach(device_t self, int flags) 260 { 261 struct tegra_hdaudio_softc * const sc = device_private(self); 262 263 hdaudio_detach(&sc->sc, flags); 264 265 if (sc->sc_ih) { 266 fdtbus_intr_disestablish(sc->sc_phandle, sc->sc_ih); 267 sc->sc_ih = NULL; 268 } 269 270 sc->sc.sc_memvalid = false; 271 272 return 0; 273 } 274 275 static int 276 tegra_hdaudio_rescan(device_t self, const char *ifattr, const int *locs) 277 { 278 struct tegra_hdaudio_softc * const sc = device_private(self); 279 280 return hdaudio_rescan(&sc->sc, ifattr, locs); 281 } 282 283 static void 284 tegra_hdaudio_childdet(device_t self, device_t child) 285 { 286 struct tegra_hdaudio_softc * const sc = device_private(self); 287 288 hdaudio_childdet(&sc->sc, child); 289 } 290 291 static int 292 tegra_hdaudio_intr(void *priv) 293 { 294 struct tegra_hdaudio_softc * const sc = priv; 295 296 return hdaudio_intr(&sc->sc); 297 } 298
Indexes created Fri Oct 31 11:10:07 GMT 2025