tegra_i2c.c revision 1.5.2.2
1 1.5.2.2 skrll /* $NetBSD: tegra_i2c.c,v 1.5.2.2 2015/06/06 14:39:56 skrll Exp $ */ 2 1.5.2.2 skrll 3 1.5.2.2 skrll /*- 4 1.5.2.2 skrll * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 1.5.2.2 skrll * All rights reserved. 6 1.5.2.2 skrll * 7 1.5.2.2 skrll * Redistribution and use in source and binary forms, with or without 8 1.5.2.2 skrll * modification, are permitted provided that the following conditions 9 1.5.2.2 skrll * are met: 10 1.5.2.2 skrll * 1. Redistributions of source code must retain the above copyright 11 1.5.2.2 skrll * notice, this list of conditions and the following disclaimer. 12 1.5.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 13 1.5.2.2 skrll * notice, this list of conditions and the following disclaimer in the 14 1.5.2.2 skrll * documentation and/or other materials provided with the distribution. 15 1.5.2.2 skrll * 16 1.5.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 1.5.2.2 skrll * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 1.5.2.2 skrll * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 1.5.2.2 skrll * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 1.5.2.2 skrll * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 1.5.2.2 skrll * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 1.5.2.2 skrll * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 1.5.2.2 skrll * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 1.5.2.2 skrll * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.5.2.2 skrll * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.5.2.2 skrll * SUCH DAMAGE. 27 1.5.2.2 skrll */ 28 1.5.2.2 skrll 29 1.5.2.2 skrll #include "locators.h" 30 1.5.2.2 skrll 31 1.5.2.2 skrll #include <sys/cdefs.h> 32 1.5.2.2 skrll __KERNEL_RCSID(0, "$NetBSD: tegra_i2c.c,v 1.5.2.2 2015/06/06 14:39:56 skrll Exp $"); 33 1.5.2.2 skrll 34 1.5.2.2 skrll #include <sys/param.h> 35 1.5.2.2 skrll #include <sys/bus.h> 36 1.5.2.2 skrll #include <sys/device.h> 37 1.5.2.2 skrll #include <sys/intr.h> 38 1.5.2.2 skrll #include <sys/systm.h> 39 1.5.2.2 skrll #include <sys/kernel.h> 40 1.5.2.2 skrll 41 1.5.2.2 skrll #include <dev/i2c/i2cvar.h> 42 1.5.2.2 skrll 43 1.5.2.2 skrll #include <arm/nvidia/tegra_reg.h> 44 1.5.2.2 skrll #include <arm/nvidia/tegra_i2creg.h> 45 1.5.2.2 skrll #include <arm/nvidia/tegra_var.h> 46 1.5.2.2 skrll 47 1.5.2.2 skrll static int tegra_i2c_match(device_t, cfdata_t, void *); 48 1.5.2.2 skrll static void tegra_i2c_attach(device_t, device_t, void *); 49 1.5.2.2 skrll 50 1.5.2.2 skrll struct tegra_i2c_softc { 51 1.5.2.2 skrll device_t sc_dev; 52 1.5.2.2 skrll bus_space_tag_t sc_bst; 53 1.5.2.2 skrll bus_space_handle_t sc_bsh; 54 1.5.2.2 skrll void * sc_ih; 55 1.5.2.2 skrll u_int sc_port; 56 1.5.2.2 skrll 57 1.5.2.2 skrll struct i2c_controller sc_ic; 58 1.5.2.2 skrll kmutex_t sc_lock; 59 1.5.2.2 skrll kcondvar_t sc_cv; 60 1.5.2.2 skrll device_t sc_i2cdev; 61 1.5.2.2 skrll }; 62 1.5.2.2 skrll 63 1.5.2.2 skrll static void tegra_i2c_init(struct tegra_i2c_softc *); 64 1.5.2.2 skrll static int tegra_i2c_intr(void *); 65 1.5.2.2 skrll 66 1.5.2.2 skrll static int tegra_i2c_acquire_bus(void *, int); 67 1.5.2.2 skrll static void tegra_i2c_release_bus(void *, int); 68 1.5.2.2 skrll static int tegra_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 69 1.5.2.2 skrll size_t, void *, size_t, int); 70 1.5.2.2 skrll 71 1.5.2.2 skrll static int tegra_i2c_wait(struct tegra_i2c_softc *, int); 72 1.5.2.2 skrll static int tegra_i2c_write(struct tegra_i2c_softc *, i2c_addr_t, 73 1.5.2.2 skrll const uint8_t *, size_t, int); 74 1.5.2.2 skrll static int tegra_i2c_read(struct tegra_i2c_softc *, i2c_addr_t, uint8_t *, 75 1.5.2.2 skrll size_t, int); 76 1.5.2.2 skrll 77 1.5.2.2 skrll CFATTACH_DECL_NEW(tegra_i2c, sizeof(struct tegra_i2c_softc), 78 1.5.2.2 skrll tegra_i2c_match, tegra_i2c_attach, NULL, NULL); 79 1.5.2.2 skrll 80 1.5.2.2 skrll #define I2C_WRITE(sc, reg, val) \ 81 1.5.2.2 skrll bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 82 1.5.2.2 skrll #define I2C_READ(sc, reg) \ 83 1.5.2.2 skrll bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 84 1.5.2.2 skrll #define I2C_SET_CLEAR(sc, reg, setval, clrval) \ 85 1.5.2.2 skrll tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (setval), (clrval)) 86 1.5.2.2 skrll 87 1.5.2.2 skrll static int 88 1.5.2.2 skrll tegra_i2c_match(device_t parent, cfdata_t cf, void *aux) 89 1.5.2.2 skrll { 90 1.5.2.2 skrll struct tegraio_attach_args * const tio = aux; 91 1.5.2.2 skrll const struct tegra_locators * const loc = &tio->tio_loc; 92 1.5.2.2 skrll 93 1.5.2.2 skrll if (loc->loc_port == TEGRAIOCF_PORT_DEFAULT) 94 1.5.2.2 skrll return 0; 95 1.5.2.2 skrll 96 1.5.2.2 skrll return 1; 97 1.5.2.2 skrll } 98 1.5.2.2 skrll 99 1.5.2.2 skrll static void 100 1.5.2.2 skrll tegra_i2c_attach(device_t parent, device_t self, void *aux) 101 1.5.2.2 skrll { 102 1.5.2.2 skrll struct tegra_i2c_softc * const sc = device_private(self); 103 1.5.2.2 skrll struct tegraio_attach_args * const tio = aux; 104 1.5.2.2 skrll const struct tegra_locators * const loc = &tio->tio_loc; 105 1.5.2.2 skrll struct i2cbus_attach_args iba; 106 1.5.2.2 skrll 107 1.5.2.2 skrll sc->sc_dev = self; 108 1.5.2.2 skrll sc->sc_bst = tio->tio_bst; 109 1.5.2.2 skrll bus_space_subregion(tio->tio_bst, tio->tio_bsh, 110 1.5.2.2 skrll loc->loc_offset, loc->loc_size, &sc->sc_bsh); 111 1.5.2.2 skrll sc->sc_port = loc->loc_port; 112 1.5.2.2 skrll mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 113 1.5.2.2 skrll cv_init(&sc->sc_cv, device_xname(self)); 114 1.5.2.2 skrll 115 1.5.2.2 skrll aprint_naive("\n"); 116 1.5.2.2 skrll aprint_normal(": I2C%d\n", loc->loc_port + 1); 117 1.5.2.2 skrll 118 1.5.2.2 skrll sc->sc_ih = intr_establish(loc->loc_intr, IPL_VM, IST_LEVEL|IST_MPSAFE, 119 1.5.2.2 skrll tegra_i2c_intr, sc); 120 1.5.2.2 skrll if (sc->sc_ih == NULL) { 121 1.5.2.2 skrll aprint_error_dev(self, "couldn't establish interrupt %d\n", 122 1.5.2.2 skrll loc->loc_intr); 123 1.5.2.2 skrll return; 124 1.5.2.2 skrll } 125 1.5.2.2 skrll aprint_normal_dev(self, "interrupting on irq %d\n", loc->loc_intr); 126 1.5.2.2 skrll 127 1.5.2.2 skrll /* Recommended setting for standard mode */ 128 1.5.2.2 skrll tegra_car_periph_i2c_enable(loc->loc_port, 20400000); 129 1.5.2.2 skrll 130 1.5.2.2 skrll tegra_i2c_init(sc); 131 1.5.2.2 skrll 132 1.5.2.2 skrll sc->sc_ic.ic_cookie = sc; 133 1.5.2.2 skrll sc->sc_ic.ic_acquire_bus = tegra_i2c_acquire_bus; 134 1.5.2.2 skrll sc->sc_ic.ic_release_bus = tegra_i2c_release_bus; 135 1.5.2.2 skrll sc->sc_ic.ic_exec = tegra_i2c_exec; 136 1.5.2.2 skrll 137 1.5.2.2 skrll iba.iba_tag = &sc->sc_ic; 138 1.5.2.2 skrll sc->sc_i2cdev = config_found_ia(self, "i2cbus", &iba, iicbus_print); 139 1.5.2.2 skrll } 140 1.5.2.2 skrll 141 1.5.2.2 skrll static void 142 1.5.2.2 skrll tegra_i2c_init(struct tegra_i2c_softc *sc) 143 1.5.2.2 skrll { 144 1.5.2.2 skrll int retry = 10000; 145 1.5.2.2 skrll 146 1.5.2.2 skrll I2C_WRITE(sc, I2C_CLK_DIVISOR_REG, 147 1.5.2.2 skrll __SHIFTIN(0x19, I2C_CLK_DIVISOR_STD_FAST_MODE) | 148 1.5.2.2 skrll __SHIFTIN(0x1, I2C_CLK_DIVISOR_HSMODE)); 149 1.5.2.2 skrll 150 1.5.2.2 skrll I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 0); 151 1.5.2.2 skrll I2C_WRITE(sc, I2C_CNFG_REG, 152 1.5.2.2 skrll I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN); 153 1.5.2.2 skrll I2C_SET_CLEAR(sc, I2C_SL_CNFG_REG, I2C_SL_CNFG_NEWSL, 0); 154 1.5.2.2 skrll I2C_WRITE(sc, I2C_FIFO_CONTROL_REG, 155 1.5.2.2 skrll __SHIFTIN(7, I2C_FIFO_CONTROL_TX_FIFO_TRIG) | 156 1.5.2.2 skrll __SHIFTIN(0, I2C_FIFO_CONTROL_RX_FIFO_TRIG)); 157 1.5.2.2 skrll 158 1.5.2.2 skrll I2C_WRITE(sc, I2C_BUS_CONFIG_LOAD_REG, 159 1.5.2.2 skrll I2C_BUS_CONFIG_LOAD_MSTR_CONFIG_LOAD); 160 1.5.2.2 skrll while (--retry > 0) { 161 1.5.2.2 skrll if (I2C_READ(sc, I2C_BUS_CONFIG_LOAD_REG) == 0) 162 1.5.2.2 skrll break; 163 1.5.2.2 skrll delay(10); 164 1.5.2.2 skrll } 165 1.5.2.2 skrll if (retry == 0) { 166 1.5.2.2 skrll device_printf(sc->sc_dev, "config load timeout\n"); 167 1.5.2.2 skrll } 168 1.5.2.2 skrll } 169 1.5.2.2 skrll 170 1.5.2.2 skrll static int 171 1.5.2.2 skrll tegra_i2c_intr(void *priv) 172 1.5.2.2 skrll { 173 1.5.2.2 skrll struct tegra_i2c_softc * const sc = priv; 174 1.5.2.2 skrll 175 1.5.2.2 skrll const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 176 1.5.2.2 skrll if (istatus == 0) 177 1.5.2.2 skrll return 0; 178 1.5.2.2 skrll I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 179 1.5.2.2 skrll 180 1.5.2.2 skrll mutex_enter(&sc->sc_lock); 181 1.5.2.2 skrll cv_broadcast(&sc->sc_cv); 182 1.5.2.2 skrll mutex_exit(&sc->sc_lock); 183 1.5.2.2 skrll 184 1.5.2.2 skrll return 1; 185 1.5.2.2 skrll } 186 1.5.2.2 skrll 187 1.5.2.2 skrll static int 188 1.5.2.2 skrll tegra_i2c_acquire_bus(void *priv, int flags) 189 1.5.2.2 skrll { 190 1.5.2.2 skrll struct tegra_i2c_softc * const sc = priv; 191 1.5.2.2 skrll 192 1.5.2.2 skrll mutex_enter(&sc->sc_lock); 193 1.5.2.2 skrll 194 1.5.2.2 skrll return 0; 195 1.5.2.2 skrll } 196 1.5.2.2 skrll 197 1.5.2.2 skrll static void 198 1.5.2.2 skrll tegra_i2c_release_bus(void *priv, int flags) 199 1.5.2.2 skrll { 200 1.5.2.2 skrll struct tegra_i2c_softc * const sc = priv; 201 1.5.2.2 skrll 202 1.5.2.2 skrll mutex_exit(&sc->sc_lock); 203 1.5.2.2 skrll } 204 1.5.2.2 skrll 205 1.5.2.2 skrll static int 206 1.5.2.2 skrll tegra_i2c_exec(void *priv, i2c_op_t op, i2c_addr_t addr, const void *cmdbuf, 207 1.5.2.2 skrll size_t cmdlen, void *buf, size_t buflen, int flags) 208 1.5.2.2 skrll { 209 1.5.2.2 skrll struct tegra_i2c_softc * const sc = priv; 210 1.5.2.2 skrll int retry, error; 211 1.5.2.2 skrll 212 1.5.2.2 skrll #if notyet 213 1.5.2.2 skrll if (cold) 214 1.5.2.2 skrll #endif 215 1.5.2.2 skrll flags |= I2C_F_POLL; 216 1.5.2.2 skrll 217 1.5.2.2 skrll KASSERT(mutex_owned(&sc->sc_lock)); 218 1.5.2.2 skrll 219 1.5.2.2 skrll if ((flags & I2C_F_POLL) == 0) { 220 1.5.2.2 skrll I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 221 1.5.2.2 skrll I2C_INTERRUPT_MASK_NOACK | I2C_INTERRUPT_MASK_ARB_LOST | 222 1.5.2.2 skrll I2C_INTERRUPT_MASK_TIMEOUT | 223 1.5.2.2 skrll I2C_INTERRUPT_MASK_ALL_PACKETS_XFER_COMPLETE); 224 1.5.2.2 skrll } 225 1.5.2.2 skrll 226 1.5.2.2 skrll const uint32_t flush_mask = 227 1.5.2.2 skrll I2C_FIFO_CONTROL_TX_FIFO_FLUSH | I2C_FIFO_CONTROL_RX_FIFO_FLUSH; 228 1.5.2.2 skrll 229 1.5.2.2 skrll I2C_SET_CLEAR(sc, I2C_FIFO_CONTROL_REG, flush_mask, 0); 230 1.5.2.2 skrll for (retry = 10000; retry > 0; retry--) { 231 1.5.2.2 skrll const uint32_t v = I2C_READ(sc, I2C_FIFO_CONTROL_REG); 232 1.5.2.2 skrll if ((v & flush_mask) == 0) 233 1.5.2.2 skrll break; 234 1.5.2.2 skrll delay(1); 235 1.5.2.2 skrll } 236 1.5.2.2 skrll if (retry == 0) { 237 1.5.2.2 skrll device_printf(sc->sc_dev, "timeout flushing FIFO\n"); 238 1.5.2.2 skrll return EIO; 239 1.5.2.2 skrll } 240 1.5.2.2 skrll 241 1.5.2.2 skrll if (cmdlen > 0) { 242 1.5.2.2 skrll error = tegra_i2c_write(sc, addr, cmdbuf, cmdlen, flags); 243 1.5.2.2 skrll if (error) { 244 1.5.2.2 skrll goto done; 245 1.5.2.2 skrll } 246 1.5.2.2 skrll } 247 1.5.2.2 skrll 248 1.5.2.2 skrll if (I2C_OP_READ_P(op)) { 249 1.5.2.2 skrll error = tegra_i2c_read(sc, addr, buf, buflen, flags); 250 1.5.2.2 skrll } else { 251 1.5.2.2 skrll error = tegra_i2c_write(sc, addr, buf, buflen, flags); 252 1.5.2.2 skrll } 253 1.5.2.2 skrll 254 1.5.2.2 skrll done: 255 1.5.2.2 skrll if ((flags & I2C_F_POLL) == 0) { 256 1.5.2.2 skrll I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 0); 257 1.5.2.2 skrll } 258 1.5.2.2 skrll 259 1.5.2.2 skrll if (error) { 260 1.5.2.2 skrll tegra_i2c_init(sc); 261 1.5.2.2 skrll } 262 1.5.2.2 skrll 263 1.5.2.2 skrll return error; 264 1.5.2.2 skrll } 265 1.5.2.2 skrll 266 1.5.2.2 skrll static int 267 1.5.2.2 skrll tegra_i2c_wait(struct tegra_i2c_softc *sc, int flags) 268 1.5.2.2 skrll { 269 1.5.2.2 skrll int error, retry; 270 1.5.2.2 skrll uint32_t stat = 0; 271 1.5.2.2 skrll 272 1.5.2.2 skrll retry = (flags & I2C_F_POLL) ? 100000 : 100; 273 1.5.2.2 skrll 274 1.5.2.2 skrll while (--retry > 0) { 275 1.5.2.2 skrll if ((flags & I2C_F_POLL) == 0) { 276 1.5.2.2 skrll error = cv_timedwait_sig(&sc->sc_cv, &sc->sc_lock, 277 1.5.2.2 skrll max(mstohz(10), 1)); 278 1.5.2.2 skrll if (error) { 279 1.5.2.2 skrll return error; 280 1.5.2.2 skrll } 281 1.5.2.2 skrll } 282 1.5.2.2 skrll stat = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 283 1.5.2.2 skrll if (stat & I2C_INTERRUPT_STATUS_PACKET_XFER_COMPLETE) { 284 1.5.2.2 skrll break; 285 1.5.2.2 skrll } 286 1.5.2.2 skrll if (flags & I2C_F_POLL) { 287 1.5.2.2 skrll delay(10); 288 1.5.2.2 skrll } 289 1.5.2.2 skrll } 290 1.5.2.2 skrll if (retry == 0) { 291 1.5.2.2 skrll stat = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 292 1.5.2.2 skrll device_printf(sc->sc_dev, "timed out, status = %#x\n", stat); 293 1.5.2.2 skrll return ETIMEDOUT; 294 1.5.2.2 skrll } 295 1.5.2.2 skrll 296 1.5.2.2 skrll const uint32_t err_mask = 297 1.5.2.2 skrll I2C_INTERRUPT_STATUS_NOACK | 298 1.5.2.2 skrll I2C_INTERRUPT_STATUS_ARB_LOST | 299 1.5.2.2 skrll I2C_INTERRUPT_MASK_TIMEOUT; 300 1.5.2.2 skrll 301 1.5.2.2 skrll if (stat & err_mask) { 302 1.5.2.2 skrll device_printf(sc->sc_dev, "error, status = %#x\n", stat); 303 1.5.2.2 skrll return EIO; 304 1.5.2.2 skrll } 305 1.5.2.2 skrll 306 1.5.2.2 skrll return 0; 307 1.5.2.2 skrll } 308 1.5.2.2 skrll 309 1.5.2.2 skrll static int 310 1.5.2.2 skrll tegra_i2c_write(struct tegra_i2c_softc *sc, i2c_addr_t addr, const uint8_t *buf, 311 1.5.2.2 skrll size_t buflen, int flags) 312 1.5.2.2 skrll { 313 1.5.2.2 skrll const uint8_t *p = buf; 314 1.5.2.2 skrll size_t n, resid = buflen; 315 1.5.2.2 skrll uint32_t data; 316 1.5.2.2 skrll int retry; 317 1.5.2.2 skrll 318 1.5.2.2 skrll const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 319 1.5.2.2 skrll I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 320 1.5.2.2 skrll 321 1.5.2.2 skrll /* Generic Header 0 */ 322 1.5.2.2 skrll I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 323 1.5.2.2 skrll __SHIFTIN(I2C_IOPACKET_WORD0_PROTHDRSZ_REQ, 324 1.5.2.2 skrll I2C_IOPACKET_WORD0_PROTHDRSZ) | 325 1.5.2.2 skrll __SHIFTIN(sc->sc_port, I2C_IOPACKET_WORD0_CONTROLLERID) | 326 1.5.2.2 skrll __SHIFTIN(1, I2C_IOPACKET_WORD0_PKTID) | 327 1.5.2.2 skrll __SHIFTIN(I2C_IOPACKET_WORD0_PROTOCOL_I2C, 328 1.5.2.2 skrll I2C_IOPACKET_WORD0_PROTOCOL) | 329 1.5.2.2 skrll __SHIFTIN(I2C_IOPACKET_WORD0_PKTTYPE_REQ, 330 1.5.2.2 skrll I2C_IOPACKET_WORD0_PKTTYPE)); 331 1.5.2.2 skrll /* Generic Header 1 */ 332 1.5.2.2 skrll I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 333 1.5.2.2 skrll __SHIFTIN(buflen - 1, I2C_IOPACKET_WORD1_PAYLOADSIZE)); 334 1.5.2.2 skrll /* I2C Master Transmit Packet Header */ 335 1.5.2.2 skrll I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 336 1.5.2.2 skrll I2C_IOPACKET_XMITHDR_IE | 337 1.5.2.2 skrll __SHIFTIN((addr << 1), I2C_IOPACKET_XMITHDR_SLAVE_ADDR)); 338 1.5.2.2 skrll 339 1.5.2.2 skrll /* Transmit data */ 340 1.5.2.2 skrll while (resid > 0) { 341 1.5.2.2 skrll retry = 10000; 342 1.5.2.2 skrll while (--retry > 0) { 343 1.5.2.2 skrll const uint32_t fs = I2C_READ(sc, I2C_FIFO_STATUS_REG); 344 1.5.2.2 skrll const u_int cnt = 345 1.5.2.2 skrll __SHIFTOUT(fs, I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT); 346 1.5.2.2 skrll if (cnt > 0) 347 1.5.2.2 skrll break; 348 1.5.2.2 skrll delay(10); 349 1.5.2.2 skrll } 350 1.5.2.2 skrll if (retry == 0) { 351 1.5.2.2 skrll device_printf(sc->sc_dev, "TX FIFO timeout\n"); 352 1.5.2.2 skrll return ETIMEDOUT; 353 1.5.2.2 skrll } 354 1.5.2.2 skrll 355 1.5.2.2 skrll for (n = 0, data = 0; n < min(resid, 4); n++) { 356 1.5.2.2 skrll data |= (uint32_t)p[n] << (n * 8); 357 1.5.2.2 skrll } 358 1.5.2.2 skrll I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, data); 359 1.5.2.2 skrll resid -= min(resid, 4); 360 1.5.2.2 skrll p += min(resid, 4); 361 1.5.2.2 skrll } 362 1.5.2.2 skrll 363 1.5.2.2 skrll return tegra_i2c_wait(sc, flags); 364 1.5.2.2 skrll } 365 1.5.2.2 skrll 366 1.5.2.2 skrll static int 367 1.5.2.2 skrll tegra_i2c_read(struct tegra_i2c_softc *sc, i2c_addr_t addr, uint8_t *buf, 368 1.5.2.2 skrll size_t buflen, int flags) 369 1.5.2.2 skrll { 370 1.5.2.2 skrll uint8_t *p = buf; 371 1.5.2.2 skrll size_t n, resid = buflen; 372 1.5.2.2 skrll uint32_t data; 373 1.5.2.2 skrll int retry; 374 1.5.2.2 skrll 375 1.5.2.2 skrll const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 376 1.5.2.2 skrll I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 377 1.5.2.2 skrll 378 1.5.2.2 skrll /* Generic Header 0 */ 379 1.5.2.2 skrll I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 380 1.5.2.2 skrll __SHIFTIN(I2C_IOPACKET_WORD0_PROTHDRSZ_REQ, 381 1.5.2.2 skrll I2C_IOPACKET_WORD0_PROTHDRSZ) | 382 1.5.2.2 skrll __SHIFTIN(sc->sc_port, I2C_IOPACKET_WORD0_CONTROLLERID) | 383 1.5.2.2 skrll __SHIFTIN(1, I2C_IOPACKET_WORD0_PKTID) | 384 1.5.2.2 skrll __SHIFTIN(I2C_IOPACKET_WORD0_PROTOCOL_I2C, 385 1.5.2.2 skrll I2C_IOPACKET_WORD0_PROTOCOL) | 386 1.5.2.2 skrll __SHIFTIN(I2C_IOPACKET_WORD0_PKTTYPE_REQ, 387 1.5.2.2 skrll I2C_IOPACKET_WORD0_PKTTYPE)); 388 1.5.2.2 skrll /* Generic Header 1 */ 389 1.5.2.2 skrll I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 390 1.5.2.2 skrll __SHIFTIN(buflen - 1, I2C_IOPACKET_WORD1_PAYLOADSIZE)); 391 1.5.2.2 skrll /* I2C Master Transmit Packet Header */ 392 1.5.2.2 skrll I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 393 1.5.2.2 skrll I2C_IOPACKET_XMITHDR_IE | I2C_IOPACKET_XMITHDR_READ | 394 1.5.2.2 skrll __SHIFTIN((addr << 1) | 1, I2C_IOPACKET_XMITHDR_SLAVE_ADDR)); 395 1.5.2.2 skrll 396 1.5.2.2 skrll while (resid > 0) { 397 1.5.2.2 skrll retry = 10000; 398 1.5.2.2 skrll while (--retry > 0) { 399 1.5.2.2 skrll const uint32_t fs = I2C_READ(sc, I2C_FIFO_STATUS_REG); 400 1.5.2.2 skrll const u_int cnt = 401 1.5.2.2 skrll __SHIFTOUT(fs, I2C_FIFO_STATUS_RX_FIFO_FULL_CNT); 402 1.5.2.2 skrll if (cnt > 0) 403 1.5.2.2 skrll break; 404 1.5.2.2 skrll delay(10); 405 1.5.2.2 skrll } 406 1.5.2.2 skrll if (retry == 0) { 407 1.5.2.2 skrll device_printf(sc->sc_dev, "RX FIFO timeout\n"); 408 1.5.2.2 skrll return ETIMEDOUT; 409 1.5.2.2 skrll } 410 1.5.2.2 skrll 411 1.5.2.2 skrll data = I2C_READ(sc, I2C_RX_FIFO_REG); 412 1.5.2.2 skrll for (n = 0; n < min(resid, 4); n++) { 413 1.5.2.2 skrll p[n] = (data >> (n * 8)) & 0xff; 414 1.5.2.2 skrll } 415 1.5.2.2 skrll resid -= min(resid, 4); 416 1.5.2.2 skrll p += min(resid, 4); 417 1.5.2.2 skrll } 418 1.5.2.2 skrll 419 1.5.2.2 skrll return tegra_i2c_wait(sc, flags); 420 1.5.2.2 skrll } 421 1.5.2.2 skrll 422 1.5.2.2 skrll void 423 1.5.2.2 skrll tegra_i2c_dvc_write(uint8_t addr, uint32_t data, size_t datalen) 424 1.5.2.2 skrll { 425 1.5.2.2 skrll bus_space_tag_t bst = &armv7_generic_bs_tag; 426 1.5.2.2 skrll bus_space_handle_t bsh; 427 1.5.2.2 skrll 428 1.5.2.2 skrll bus_space_subregion(bst, tegra_apb_bsh, TEGRA_I2C5_OFFSET, 429 1.5.2.2 skrll TEGRA_I2C5_SIZE, &bsh); 430 1.5.2.2 skrll 431 1.5.2.2 skrll bus_space_write_4(bst, bsh, I2C_CMD_ADDR0_REG, addr << 1); 432 1.5.2.2 skrll bus_space_write_4(bst, bsh, I2C_CMD_DATA1_REG, data); 433 1.5.2.2 skrll bus_space_write_4(bst, bsh, I2C_CNFG_REG, 434 1.5.2.2 skrll __SHIFTIN(datalen - 1, I2C_CNFG_LENGTH) | 435 1.5.2.2 skrll I2C_CNFG_NEW_MASTER_FSM | 436 1.5.2.2 skrll I2C_CNFG_SEND); 437 1.5.2.2 skrll } 438
Indexes created Thu Oct 02 07:10:07 GMT 2025