tegra_i2c.c revision 1.1
1 /* $NetBSD: tegra_i2c.c,v 1.1 2015/05/10 23:50:21 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "locators.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: tegra_i2c.c,v 1.1 2015/05/10 23:50:21 jmcneill Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 41 #include <dev/i2c/i2cvar.h> 42 43 #include <arm/nvidia/tegra_reg.h> 44 #include <arm/nvidia/tegra_i2creg.h> 45 #include <arm/nvidia/tegra_var.h> 46 47 static int tegra_i2c_match(device_t, cfdata_t, void *); 48 static void tegra_i2c_attach(device_t, device_t, void *); 49 50 struct tegra_i2c_softc { 51 device_t sc_dev; 52 bus_space_tag_t sc_bst; 53 bus_space_handle_t sc_bsh; 54 void * sc_ih; 55 56 struct i2c_controller sc_ic; 57 kmutex_t sc_lock; 58 kcondvar_t sc_cv; 59 device_t sc_i2cdev; 60 }; 61 62 static void tegra_i2c_init(struct tegra_i2c_softc *); 63 static int tegra_i2c_intr(void *); 64 65 static int tegra_i2c_acquire_bus(void *, int); 66 static void tegra_i2c_release_bus(void *, int); 67 static int tegra_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 68 size_t, void *, size_t, int); 69 70 static int tegra_i2c_wait(struct tegra_i2c_softc *, int); 71 static int tegra_i2c_write(struct tegra_i2c_softc *, i2c_addr_t, 72 const uint8_t *, size_t, int); 73 static int tegra_i2c_read(struct tegra_i2c_softc *, i2c_addr_t, uint8_t *, 74 size_t, int); 75 76 CFATTACH_DECL_NEW(tegra_i2c, sizeof(struct tegra_i2c_softc), 77 tegra_i2c_match, tegra_i2c_attach, NULL, NULL); 78 79 #define I2C_WRITE(sc, reg, val) \ 80 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 81 #define I2C_READ(sc, reg) \ 82 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 83 #define I2C_SET_CLEAR(sc, reg, setval, clrval) \ 84 tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (setval), (clrval)) 85 86 static int 87 tegra_i2c_match(device_t parent, cfdata_t cf, void *aux) 88 { 89 struct tegraio_attach_args * const tio = aux; 90 const struct tegra_locators * const loc = &tio->tio_loc; 91 92 if (loc->loc_port == TEGRAIOCF_PORT_DEFAULT) 93 return 0; 94 95 return 1; 96 } 97 98 static void 99 tegra_i2c_attach(device_t parent, device_t self, void *aux) 100 { 101 struct tegra_i2c_softc * const sc = device_private(self); 102 struct tegraio_attach_args * const tio = aux; 103 const struct tegra_locators * const loc = &tio->tio_loc; 104 struct i2cbus_attach_args iba; 105 106 sc->sc_dev = self; 107 sc->sc_bst = tio->tio_bst; 108 bus_space_subregion(tio->tio_bst, tio->tio_bsh, 109 loc->loc_offset, loc->loc_size, &sc->sc_bsh); 110 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 111 cv_init(&sc->sc_cv, device_xname(self)); 112 113 aprint_naive("\n"); 114 aprint_normal(": I2C%d\n", loc->loc_port + 1); 115 116 sc->sc_ih = intr_establish(loc->loc_intr, IPL_VM, IST_LEVEL|IST_MPSAFE, 117 tegra_i2c_intr, sc); 118 if (sc->sc_ih == NULL) { 119 aprint_error_dev(self, "couldn't establish interrupt %d\n", 120 loc->loc_intr); 121 return; 122 } 123 aprint_normal_dev(self, "interrupting on irq %d\n", loc->loc_intr); 124 125 /* Recommended setting for standard mode */ 126 tegra_car_periph_i2c_enable(loc->loc_port, 204000000); 127 128 tegra_i2c_init(sc); 129 130 sc->sc_ic.ic_cookie = sc; 131 sc->sc_ic.ic_acquire_bus = tegra_i2c_acquire_bus; 132 sc->sc_ic.ic_release_bus = tegra_i2c_release_bus; 133 sc->sc_ic.ic_exec = tegra_i2c_exec; 134 135 iba.iba_tag = &sc->sc_ic; 136 sc->sc_i2cdev = config_found_ia(self, "i2cbus", &iba, iicbus_print); 137 } 138 139 static void 140 tegra_i2c_init(struct tegra_i2c_softc *sc) 141 { 142 I2C_WRITE(sc, I2C_CLK_DIVISOR_REG, 143 __SHIFTIN(0x19, I2C_CLK_DIVISOR_STD_FAST_MODE) | 144 __SHIFTIN(0x1, I2C_CLK_DIVISOR_HSMODE)); 145 146 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 0); 147 I2C_WRITE(sc, I2C_CNFG_REG, I2C_CNFG_NEW_MASTER_FSM); 148 I2C_SET_CLEAR(sc, I2C_SL_CNFG_REG, I2C_SL_CNFG_NEWSL, 0); 149 } 150 151 static int 152 tegra_i2c_intr(void *priv) 153 { 154 struct tegra_i2c_softc * const sc = priv; 155 156 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 157 if (istatus == 0) 158 return 0; 159 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 160 161 mutex_enter(&sc->sc_lock); 162 cv_broadcast(&sc->sc_cv); 163 mutex_exit(&sc->sc_lock); 164 165 return 1; 166 } 167 168 static int 169 tegra_i2c_acquire_bus(void *priv, int flags) 170 { 171 struct tegra_i2c_softc * const sc = priv; 172 173 mutex_enter(&sc->sc_lock); 174 175 return 0; 176 } 177 178 static void 179 tegra_i2c_release_bus(void *priv, int flags) 180 { 181 struct tegra_i2c_softc * const sc = priv; 182 183 mutex_exit(&sc->sc_lock); 184 } 185 186 static int 187 tegra_i2c_exec(void *priv, i2c_op_t op, i2c_addr_t addr, const void *cmdbuf, 188 size_t cmdlen, void *buf, size_t buflen, int flags) 189 { 190 struct tegra_i2c_softc * const sc = priv; 191 int retry, error; 192 193 #if notyet 194 if (cold) 195 #endif 196 flags |= I2C_F_POLL; 197 198 KASSERT(mutex_owned(&sc->sc_lock)); 199 200 if ((flags & I2C_F_POLL) == 0) { 201 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 202 I2C_INTERRUPT_MASK_NOACK | I2C_INTERRUPT_MASK_ARB_LOST | 203 I2C_INTERRUPT_MASK_TIMEOUT | 204 I2C_INTERRUPT_MASK_ALL_PACKETS_XFER_COMPLETE); 205 } 206 207 const uint32_t flush_mask = 208 I2C_FIFO_CONTROL_TX_FIFO_FLUSH | I2C_FIFO_CONTROL_RX_FIFO_FLUSH; 209 210 I2C_SET_CLEAR(sc, I2C_FIFO_CONTROL_REG, flush_mask, 0); 211 for (retry = 10000; retry > 0; retry--) { 212 const uint32_t v = I2C_READ(sc, I2C_FIFO_CONTROL_REG); 213 if ((v & flush_mask) == 0) 214 break; 215 delay(1); 216 } 217 if (retry == 0) { 218 device_printf(sc->sc_dev, "timeout flushing FIFO\n"); 219 return EIO; 220 } 221 222 if (cmdlen > 0) { 223 error = tegra_i2c_write(sc, addr, cmdbuf, cmdlen, flags); 224 if (error) { 225 goto done; 226 } 227 } 228 229 if (I2C_OP_READ_P(op)) { 230 error = tegra_i2c_read(sc, addr, buf, buflen, flags); 231 } else { 232 error = tegra_i2c_write(sc, addr, buf, buflen, flags); 233 } 234 235 done: 236 if ((flags & I2C_F_POLL) == 0) { 237 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 0); 238 } 239 return error; 240 } 241 242 static int 243 tegra_i2c_wait(struct tegra_i2c_softc *sc, int flags) 244 { 245 const struct timeval timeout = { .tv_sec = 1, .tv_usec = 0 }; 246 struct timeval tnow, tend; 247 uint32_t stat; 248 int error; 249 250 getmicrotime(&tnow); 251 timeradd(&tnow, &timeout, &tend); 252 253 for (;;) { 254 getmicrotime(&tnow); 255 if (timercmp(&tnow, &tend, >=)) { 256 return ETIMEDOUT; 257 } 258 if ((flags & I2C_F_POLL) == 0) { 259 struct timeval trem; 260 timersub(&tend, &tnow, &trem); 261 const u_int ms = (trem.tv_sec * 1000) + 262 (trem.tv_usec / 1000); 263 KASSERT(ms > 0); 264 error = cv_timedwait_sig(&sc->sc_cv, &sc->sc_lock, 265 max(mstohz(ms), 1)); 266 if (error) { 267 return error; 268 } 269 } 270 stat = I2C_READ(sc, I2C_STATUS_REG); 271 if ((stat & I2C_STATUS_BUSY) == 0) { 272 break; 273 } 274 if (flags & I2C_F_POLL) { 275 delay(1); 276 } 277 } 278 279 280 if (__SHIFTOUT(stat, I2C_STATUS_CMD1_STAT) != 0) 281 return EIO; 282 283 return 0; 284 } 285 286 static int 287 tegra_i2c_write(struct tegra_i2c_softc *sc, i2c_addr_t addr, const uint8_t *buf, 288 size_t buflen, int flags) 289 { 290 uint32_t data, cnfg; 291 size_t n; 292 293 if (buflen > 4) 294 return EINVAL; 295 296 I2C_WRITE(sc, I2C_CMD_ADDR0_REG, addr << 1); 297 for (n = 0, data = 0; n < buflen; n++) { 298 data |= (uint32_t)buf[n] << (n * 8); 299 } 300 I2C_WRITE(sc, I2C_CMD_DATA1_REG, data); 301 302 cnfg = I2C_READ(sc, I2C_CNFG_REG); 303 cnfg &= ~I2C_CNFG_DEBOUNCE_CNT; 304 cnfg |= __SHIFTIN(2, I2C_CNFG_DEBOUNCE_CNT); 305 cnfg &= ~I2C_CNFG_LENGTH; 306 cnfg |= __SHIFTIN(buflen - 1, I2C_CNFG_LENGTH); 307 cnfg &= ~I2C_CNFG_SLV2; 308 cnfg &= ~I2C_CNFG_CMD1; 309 cnfg &= ~I2C_CNFG_NOACK; 310 cnfg &= ~I2C_CNFG_A_MOD; 311 I2C_WRITE(sc, I2C_CNFG_REG, cnfg); 312 313 I2C_SET_CLEAR(sc, I2C_BUS_CONFIG_LOAD_REG, 314 I2C_BUS_CONFIG_LOAD_MSTR_CONFIG_LOAD, 0); 315 316 I2C_SET_CLEAR(sc, I2C_CNFG_REG, I2C_CNFG_SEND, 0); 317 318 return tegra_i2c_wait(sc, flags); 319 } 320 321 static int 322 tegra_i2c_read(struct tegra_i2c_softc *sc, i2c_addr_t addr, uint8_t *buf, 323 size_t buflen, int flags) 324 { 325 uint32_t data, cnfg; 326 int error; 327 size_t n; 328 329 if (buflen > 4) 330 return EINVAL; 331 332 I2C_WRITE(sc, I2C_CMD_ADDR0_REG, (addr << 1) | 1); 333 cnfg = I2C_READ(sc, I2C_CNFG_REG); 334 cnfg &= ~I2C_CNFG_SLV2; 335 cnfg |= I2C_CNFG_CMD1; 336 cnfg &= ~I2C_CNFG_LENGTH; 337 cnfg |= __SHIFTIN(buflen - 1, I2C_CNFG_LENGTH); 338 I2C_WRITE(sc, I2C_CNFG_REG, cnfg); 339 340 I2C_SET_CLEAR(sc, I2C_CNFG_REG, I2C_CNFG_SEND, 0); 341 342 error = tegra_i2c_wait(sc, flags); 343 if (error) 344 return error; 345 346 data = I2C_READ(sc, I2C_CMD_DATA1_REG); 347 for (n = 0; n < buflen; n++) { 348 buf[n] = (data >> (n * 8)) & 0xff; 349 } 350 351 return 0; 352 } 353
Indexes created Thu Oct 02 01:09:59 GMT 2025