tegra_i2c.c revision 1.16.10.1
1 /* $NetBSD: tegra_i2c.c,v 1.16.10.1 2018/05/21 04:35:59 pgoyette Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_i2c.c,v 1.16.10.1 2018/05/21 04:35:59 pgoyette Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 39 #include <dev/i2c/i2cvar.h> 40 41 #include <arm/nvidia/tegra_reg.h> 42 #include <arm/nvidia/tegra_i2creg.h> 43 #include <arm/nvidia/tegra_var.h> 44 45 #include <dev/fdt/fdtvar.h> 46 47 static int tegra_i2c_match(device_t, cfdata_t, void *); 48 static void tegra_i2c_attach(device_t, device_t, void *); 49 50 static i2c_tag_t tegra_i2c_get_tag(device_t); 51 52 struct fdtbus_i2c_controller_func tegra_i2c_funcs = { 53 .get_tag = tegra_i2c_get_tag 54 }; 55 56 struct tegra_i2c_softc { 57 device_t sc_dev; 58 bus_space_tag_t sc_bst; 59 bus_space_handle_t sc_bsh; 60 void * sc_ih; 61 struct clk * sc_clk; 62 struct fdtbus_reset * sc_rst; 63 u_int sc_cid; 64 65 struct i2c_controller sc_ic; 66 kmutex_t sc_lock; 67 kcondvar_t sc_cv; 68 device_t sc_i2cdev; 69 }; 70 71 static void tegra_i2c_init(struct tegra_i2c_softc *); 72 static int tegra_i2c_intr(void *); 73 74 static int tegra_i2c_acquire_bus(void *, int); 75 static void tegra_i2c_release_bus(void *, int); 76 static int tegra_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 77 size_t, void *, size_t, int); 78 79 static int tegra_i2c_wait(struct tegra_i2c_softc *, int); 80 static int tegra_i2c_write(struct tegra_i2c_softc *, i2c_addr_t, 81 const uint8_t *, size_t, int, bool); 82 static int tegra_i2c_read(struct tegra_i2c_softc *, i2c_addr_t, uint8_t *, 83 size_t, int); 84 85 CFATTACH_DECL_NEW(tegra_i2c, sizeof(struct tegra_i2c_softc), 86 tegra_i2c_match, tegra_i2c_attach, NULL, NULL); 87 88 #define I2C_WRITE(sc, reg, val) \ 89 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 90 #define I2C_READ(sc, reg) \ 91 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 92 #define I2C_SET_CLEAR(sc, reg, setval, clrval) \ 93 tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (setval), (clrval)) 94 95 static int 96 tegra_i2c_match(device_t parent, cfdata_t cf, void *aux) 97 { 98 const char * const compatible[] = { 99 "nvidia,tegra210-i2c", 100 "nvidia,tegra124-i2c", 101 "nvidia,tegra114-i2c", 102 NULL 103 }; 104 struct fdt_attach_args * const faa = aux; 105 106 return of_match_compatible(faa->faa_phandle, compatible); 107 } 108 109 static void 110 tegra_i2c_attach(device_t parent, device_t self, void *aux) 111 { 112 struct tegra_i2c_softc * const sc = device_private(self); 113 struct fdt_attach_args * const faa = aux; 114 const int phandle = faa->faa_phandle; 115 struct i2cbus_attach_args iba; 116 prop_dictionary_t devs; 117 char intrstr[128]; 118 bus_addr_t addr; 119 bus_size_t size; 120 u_int address_cells; 121 int error; 122 123 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 124 aprint_error(": couldn't get registers\n"); 125 return; 126 } 127 sc->sc_clk = fdtbus_clock_get(phandle, "div-clk"); 128 if (sc->sc_clk == NULL) { 129 aprint_error(": couldn't get clock div-clk\n"); 130 return; 131 } 132 sc->sc_rst = fdtbus_reset_get(phandle, "i2c"); 133 if (sc->sc_rst == NULL) { 134 aprint_error(": couldn't get reset i2c\n"); 135 return; 136 } 137 138 sc->sc_dev = self; 139 sc->sc_bst = faa->faa_bst; 140 sc->sc_cid = device_unit(self); 141 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 142 if (error) { 143 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 144 return; 145 } 146 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 147 cv_init(&sc->sc_cv, device_xname(self)); 148 149 aprint_naive("\n"); 150 aprint_normal(": I2C\n"); 151 152 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 153 aprint_error_dev(self, "failed to decode interrupt\n"); 154 return; 155 } 156 157 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_VM, 158 FDT_INTR_MPSAFE, tegra_i2c_intr, sc); 159 if (sc->sc_ih == NULL) { 160 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 161 intrstr); 162 return; 163 } 164 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 165 166 /* 167 * Recommended setting for standard mode is to use an I2C source div 168 * of 20 (Tegra K1 Technical Reference Manual, Table 137) 169 */ 170 fdtbus_reset_assert(sc->sc_rst); 171 error = clk_set_rate(sc->sc_clk, 20400000); 172 if (error) { 173 aprint_error_dev(self, "couldn't set frequency: %d\n", error); 174 return; 175 } 176 error = clk_enable(sc->sc_clk); 177 if (error) { 178 aprint_error_dev(self, "couldn't enable clock: %d\n", error); 179 return; 180 } 181 fdtbus_reset_deassert(sc->sc_rst); 182 183 tegra_i2c_init(sc); 184 185 sc->sc_ic.ic_cookie = sc; 186 sc->sc_ic.ic_acquire_bus = tegra_i2c_acquire_bus; 187 sc->sc_ic.ic_release_bus = tegra_i2c_release_bus; 188 sc->sc_ic.ic_exec = tegra_i2c_exec; 189 190 fdtbus_register_i2c_controller(self, phandle, &tegra_i2c_funcs); 191 192 devs = prop_dictionary_create(); 193 194 if (of_getprop_uint32(phandle, "#address-cells", &address_cells)) 195 address_cells = 1; 196 197 of_enter_i2c_devs(devs, faa->faa_phandle, address_cells * 4, 0); 198 199 memset(&iba, 0, sizeof(iba)); 200 iba.iba_tag = &sc->sc_ic; 201 iba.iba_child_devices = prop_dictionary_get(devs, "i2c-child-devices"); 202 if (iba.iba_child_devices != NULL) 203 prop_object_retain(iba.iba_child_devices); 204 prop_object_release(devs); 205 206 sc->sc_i2cdev = config_found_ia(self, "i2cbus", &iba, iicbus_print); 207 } 208 209 static i2c_tag_t 210 tegra_i2c_get_tag(device_t dev) 211 { 212 struct tegra_i2c_softc * const sc = device_private(dev); 213 214 return &sc->sc_ic; 215 } 216 217 static void 218 tegra_i2c_init(struct tegra_i2c_softc *sc) 219 { 220 int retry = 10000; 221 222 I2C_WRITE(sc, I2C_CLK_DIVISOR_REG, 223 __SHIFTIN(0x19, I2C_CLK_DIVISOR_STD_FAST_MODE) | 224 __SHIFTIN(0x1, I2C_CLK_DIVISOR_HSMODE)); 225 226 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 0); 227 I2C_WRITE(sc, I2C_CNFG_REG, 228 I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN); 229 I2C_SET_CLEAR(sc, I2C_SL_CNFG_REG, I2C_SL_CNFG_NEWSL, 0); 230 I2C_WRITE(sc, I2C_FIFO_CONTROL_REG, 231 __SHIFTIN(7, I2C_FIFO_CONTROL_TX_FIFO_TRIG) | 232 __SHIFTIN(0, I2C_FIFO_CONTROL_RX_FIFO_TRIG)); 233 234 I2C_WRITE(sc, I2C_BUS_CONFIG_LOAD_REG, 235 I2C_BUS_CONFIG_LOAD_MSTR_CONFIG_LOAD); 236 while (--retry > 0) { 237 if (I2C_READ(sc, I2C_BUS_CONFIG_LOAD_REG) == 0) 238 break; 239 delay(10); 240 } 241 if (retry == 0) { 242 device_printf(sc->sc_dev, "config load timeout\n"); 243 } 244 } 245 246 static int 247 tegra_i2c_intr(void *priv) 248 { 249 struct tegra_i2c_softc * const sc = priv; 250 251 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 252 if (istatus == 0) 253 return 0; 254 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 255 256 mutex_enter(&sc->sc_lock); 257 cv_broadcast(&sc->sc_cv); 258 mutex_exit(&sc->sc_lock); 259 260 return 1; 261 } 262 263 static int 264 tegra_i2c_acquire_bus(void *priv, int flags) 265 { 266 struct tegra_i2c_softc * const sc = priv; 267 268 mutex_enter(&sc->sc_lock); 269 270 return 0; 271 } 272 273 static void 274 tegra_i2c_release_bus(void *priv, int flags) 275 { 276 struct tegra_i2c_softc * const sc = priv; 277 278 mutex_exit(&sc->sc_lock); 279 } 280 281 static int 282 tegra_i2c_exec(void *priv, i2c_op_t op, i2c_addr_t addr, const void *cmdbuf, 283 size_t cmdlen, void *buf, size_t buflen, int flags) 284 { 285 struct tegra_i2c_softc * const sc = priv; 286 int retry, error; 287 288 #if notyet 289 if (cold) 290 #endif 291 flags |= I2C_F_POLL; 292 293 KASSERT(mutex_owned(&sc->sc_lock)); 294 295 if ((flags & I2C_F_POLL) == 0) { 296 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 297 I2C_INTERRUPT_MASK_NOACK | I2C_INTERRUPT_MASK_ARB_LOST | 298 I2C_INTERRUPT_MASK_TIMEOUT | 299 I2C_INTERRUPT_MASK_ALL_PACKETS_XFER_COMPLETE); 300 } 301 302 const uint32_t flush_mask = 303 I2C_FIFO_CONTROL_TX_FIFO_FLUSH | I2C_FIFO_CONTROL_RX_FIFO_FLUSH; 304 305 I2C_SET_CLEAR(sc, I2C_FIFO_CONTROL_REG, flush_mask, 0); 306 for (retry = 10000; retry > 0; retry--) { 307 const uint32_t v = I2C_READ(sc, I2C_FIFO_CONTROL_REG); 308 if ((v & flush_mask) == 0) 309 break; 310 delay(1); 311 } 312 if (retry == 0) { 313 device_printf(sc->sc_dev, "timeout flushing FIFO\n"); 314 return EIO; 315 } 316 317 if (cmdlen > 0) { 318 error = tegra_i2c_write(sc, addr, cmdbuf, cmdlen, flags, 319 buflen > 0 ? true : false); 320 if (error) { 321 goto done; 322 } 323 } 324 325 if (I2C_OP_READ_P(op)) { 326 error = tegra_i2c_read(sc, addr, buf, buflen, flags); 327 } else { 328 error = tegra_i2c_write(sc, addr, buf, buflen, flags, false); 329 } 330 331 done: 332 if ((flags & I2C_F_POLL) == 0) { 333 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 0); 334 } 335 336 if (error) { 337 tegra_i2c_init(sc); 338 } 339 340 return error; 341 } 342 343 static int 344 tegra_i2c_wait(struct tegra_i2c_softc *sc, int flags) 345 { 346 int error, retry; 347 uint32_t stat = 0; 348 349 retry = (flags & I2C_F_POLL) ? 100000 : 100; 350 351 while (--retry > 0) { 352 if ((flags & I2C_F_POLL) == 0) { 353 error = cv_timedwait_sig(&sc->sc_cv, &sc->sc_lock, 354 max(mstohz(10), 1)); 355 if (error) { 356 return error; 357 } 358 } 359 stat = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 360 if (stat & I2C_INTERRUPT_STATUS_PACKET_XFER_COMPLETE) { 361 break; 362 } 363 if (flags & I2C_F_POLL) { 364 delay(10); 365 } 366 } 367 if (retry == 0) { 368 stat = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 369 device_printf(sc->sc_dev, "timed out, status = %#x\n", stat); 370 return ETIMEDOUT; 371 } 372 373 const uint32_t err_mask = 374 I2C_INTERRUPT_STATUS_NOACK | 375 I2C_INTERRUPT_STATUS_ARB_LOST | 376 I2C_INTERRUPT_MASK_TIMEOUT; 377 378 if (stat & err_mask) { 379 device_printf(sc->sc_dev, "error, status = %#x\n", stat); 380 return EIO; 381 } 382 383 return 0; 384 } 385 386 static int 387 tegra_i2c_write(struct tegra_i2c_softc *sc, i2c_addr_t addr, const uint8_t *buf, 388 size_t buflen, int flags, bool repeat_start) 389 { 390 const uint8_t *p = buf; 391 size_t n, resid = buflen; 392 uint32_t data; 393 int retry; 394 395 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 396 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 397 398 /* Generic Header 0 */ 399 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 400 __SHIFTIN(I2C_IOPACKET_WORD0_PROTHDRSZ_REQ, 401 I2C_IOPACKET_WORD0_PROTHDRSZ) | 402 __SHIFTIN(sc->sc_cid, I2C_IOPACKET_WORD0_CONTROLLERID) | 403 __SHIFTIN(1, I2C_IOPACKET_WORD0_PKTID) | 404 __SHIFTIN(I2C_IOPACKET_WORD0_PROTOCOL_I2C, 405 I2C_IOPACKET_WORD0_PROTOCOL) | 406 __SHIFTIN(I2C_IOPACKET_WORD0_PKTTYPE_REQ, 407 I2C_IOPACKET_WORD0_PKTTYPE)); 408 /* Generic Header 1 */ 409 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 410 __SHIFTIN(buflen - 1, I2C_IOPACKET_WORD1_PAYLOADSIZE)); 411 /* I2C Master Transmit Packet Header */ 412 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 413 I2C_IOPACKET_XMITHDR_IE | 414 (repeat_start ? I2C_IOPACKET_XMITHDR_REPEAT_STARTSTOP : 0) | 415 __SHIFTIN((addr << 1), I2C_IOPACKET_XMITHDR_SLAVE_ADDR)); 416 417 /* Transmit data */ 418 while (resid > 0) { 419 retry = 10000; 420 while (--retry > 0) { 421 const uint32_t fs = I2C_READ(sc, I2C_FIFO_STATUS_REG); 422 const u_int cnt = 423 __SHIFTOUT(fs, I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT); 424 if (cnt > 0) 425 break; 426 delay(10); 427 } 428 if (retry == 0) { 429 device_printf(sc->sc_dev, "TX FIFO timeout\n"); 430 return ETIMEDOUT; 431 } 432 433 for (n = 0, data = 0; n < min(resid, 4); n++) { 434 data |= (uint32_t)p[n] << (n * 8); 435 } 436 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, data); 437 p += min(resid, 4); 438 resid -= min(resid, 4); 439 } 440 441 return tegra_i2c_wait(sc, flags); 442 } 443 444 static int 445 tegra_i2c_read(struct tegra_i2c_softc *sc, i2c_addr_t addr, uint8_t *buf, 446 size_t buflen, int flags) 447 { 448 uint8_t *p = buf; 449 size_t n, resid = buflen; 450 uint32_t data; 451 int retry; 452 453 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 454 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 455 456 /* Generic Header 0 */ 457 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 458 __SHIFTIN(I2C_IOPACKET_WORD0_PROTHDRSZ_REQ, 459 I2C_IOPACKET_WORD0_PROTHDRSZ) | 460 __SHIFTIN(sc->sc_cid, I2C_IOPACKET_WORD0_CONTROLLERID) | 461 __SHIFTIN(1, I2C_IOPACKET_WORD0_PKTID) | 462 __SHIFTIN(I2C_IOPACKET_WORD0_PROTOCOL_I2C, 463 I2C_IOPACKET_WORD0_PROTOCOL) | 464 __SHIFTIN(I2C_IOPACKET_WORD0_PKTTYPE_REQ, 465 I2C_IOPACKET_WORD0_PKTTYPE)); 466 /* Generic Header 1 */ 467 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 468 __SHIFTIN(buflen - 1, I2C_IOPACKET_WORD1_PAYLOADSIZE)); 469 /* I2C Master Transmit Packet Header */ 470 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 471 I2C_IOPACKET_XMITHDR_IE | I2C_IOPACKET_XMITHDR_READ | 472 __SHIFTIN((addr << 1) | 1, I2C_IOPACKET_XMITHDR_SLAVE_ADDR)); 473 474 while (resid > 0) { 475 retry = 10000; 476 while (--retry > 0) { 477 const uint32_t fs = I2C_READ(sc, I2C_FIFO_STATUS_REG); 478 const u_int cnt = 479 __SHIFTOUT(fs, I2C_FIFO_STATUS_RX_FIFO_FULL_CNT); 480 if (cnt > 0) 481 break; 482 delay(10); 483 } 484 if (retry == 0) { 485 device_printf(sc->sc_dev, "RX FIFO timeout\n"); 486 return ETIMEDOUT; 487 } 488 489 data = I2C_READ(sc, I2C_RX_FIFO_REG); 490 for (n = 0; n < min(resid, 4); n++) { 491 p[n] = (data >> (n * 8)) & 0xff; 492 } 493 p += min(resid, 4); 494 resid -= min(resid, 4); 495 } 496 497 return tegra_i2c_wait(sc, flags); 498 } 499
Indexes created Thu Oct 02 07:10:07 GMT 2025