tegra_i2c.c revision 1.17.2.2
1 /* $NetBSD: tegra_i2c.c,v 1.17.2.2 2020/04/08 14:07:30 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_i2c.c,v 1.17.2.2 2020/04/08 14:07:30 martin Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 39 #include <dev/i2c/i2cvar.h> 40 41 #include <arm/nvidia/tegra_reg.h> 42 #include <arm/nvidia/tegra_i2creg.h> 43 #include <arm/nvidia/tegra_var.h> 44 45 #include <dev/fdt/fdtvar.h> 46 47 static int tegra_i2c_match(device_t, cfdata_t, void *); 48 static void tegra_i2c_attach(device_t, device_t, void *); 49 50 static i2c_tag_t tegra_i2c_get_tag(device_t); 51 52 struct fdtbus_i2c_controller_func tegra_i2c_funcs = { 53 .get_tag = tegra_i2c_get_tag 54 }; 55 56 struct tegra_i2c_softc { 57 device_t sc_dev; 58 bus_space_tag_t sc_bst; 59 bus_space_handle_t sc_bsh; 60 void * sc_ih; 61 struct clk * sc_clk; 62 struct fdtbus_reset * sc_rst; 63 u_int sc_cid; 64 65 struct i2c_controller sc_ic; 66 kmutex_t sc_intr_lock; 67 kcondvar_t sc_intr_wait; 68 }; 69 70 static void tegra_i2c_init(struct tegra_i2c_softc *); 71 static int tegra_i2c_intr(void *); 72 73 static int tegra_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 74 size_t, void *, size_t, int); 75 76 static int tegra_i2c_wait(struct tegra_i2c_softc *, int); 77 static int tegra_i2c_write(struct tegra_i2c_softc *, i2c_addr_t, 78 const uint8_t *, size_t, int, bool); 79 static int tegra_i2c_read(struct tegra_i2c_softc *, i2c_addr_t, uint8_t *, 80 size_t, int); 81 82 CFATTACH_DECL_NEW(tegra_i2c, sizeof(struct tegra_i2c_softc), 83 tegra_i2c_match, tegra_i2c_attach, NULL, NULL); 84 85 #define I2C_WRITE(sc, reg, val) \ 86 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 87 #define I2C_READ(sc, reg) \ 88 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 89 #define I2C_SET_CLEAR(sc, reg, setval, clrval) \ 90 tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (setval), (clrval)) 91 92 static int 93 tegra_i2c_match(device_t parent, cfdata_t cf, void *aux) 94 { 95 const char * const compatible[] = { 96 "nvidia,tegra210-i2c", 97 "nvidia,tegra124-i2c", 98 "nvidia,tegra114-i2c", 99 NULL 100 }; 101 struct fdt_attach_args * const faa = aux; 102 103 return of_match_compatible(faa->faa_phandle, compatible); 104 } 105 106 static void 107 tegra_i2c_attach(device_t parent, device_t self, void *aux) 108 { 109 struct tegra_i2c_softc * const sc = device_private(self); 110 struct fdt_attach_args * const faa = aux; 111 const int phandle = faa->faa_phandle; 112 char intrstr[128]; 113 bus_addr_t addr; 114 bus_size_t size; 115 int error; 116 117 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 118 aprint_error(": couldn't get registers\n"); 119 return; 120 } 121 sc->sc_clk = fdtbus_clock_get(phandle, "div-clk"); 122 if (sc->sc_clk == NULL) { 123 aprint_error(": couldn't get clock div-clk\n"); 124 return; 125 } 126 sc->sc_rst = fdtbus_reset_get(phandle, "i2c"); 127 if (sc->sc_rst == NULL) { 128 aprint_error(": couldn't get reset i2c\n"); 129 return; 130 } 131 132 sc->sc_dev = self; 133 sc->sc_bst = faa->faa_bst; 134 sc->sc_cid = device_unit(self); 135 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 136 if (error) { 137 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", 138 addr, error); 139 return; 140 } 141 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_VM); 142 cv_init(&sc->sc_intr_wait, device_xname(self)); 143 144 aprint_naive("\n"); 145 aprint_normal(": I2C\n"); 146 147 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 148 aprint_error_dev(self, "failed to decode interrupt\n"); 149 return; 150 } 151 152 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_VM, 153 FDT_INTR_MPSAFE, tegra_i2c_intr, sc); 154 if (sc->sc_ih == NULL) { 155 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 156 intrstr); 157 return; 158 } 159 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 160 161 /* 162 * Recommended setting for standard mode is to use an I2C source div 163 * of 20 (Tegra K1 Technical Reference Manual, Table 137) 164 */ 165 fdtbus_reset_assert(sc->sc_rst); 166 error = clk_set_rate(sc->sc_clk, 20400000); 167 if (error) { 168 aprint_error_dev(self, "couldn't set frequency: %d\n", error); 169 return; 170 } 171 error = clk_enable(sc->sc_clk); 172 if (error) { 173 aprint_error_dev(self, "couldn't enable clock: %d\n", error); 174 return; 175 } 176 fdtbus_reset_deassert(sc->sc_rst); 177 178 mutex_enter(&sc->sc_intr_lock); 179 tegra_i2c_init(sc); 180 mutex_exit(&sc->sc_intr_lock); 181 182 iic_tag_init(&sc->sc_ic); 183 sc->sc_ic.ic_cookie = sc; 184 sc->sc_ic.ic_exec = tegra_i2c_exec; 185 186 fdtbus_register_i2c_controller(self, phandle, &tegra_i2c_funcs); 187 188 fdtbus_attach_i2cbus(self, phandle, &sc->sc_ic, iicbus_print); 189 } 190 191 static i2c_tag_t 192 tegra_i2c_get_tag(device_t dev) 193 { 194 struct tegra_i2c_softc * const sc = device_private(dev); 195 196 return &sc->sc_ic; 197 } 198 199 static void 200 tegra_i2c_init(struct tegra_i2c_softc *sc) 201 { 202 int retry = 10000; 203 204 I2C_WRITE(sc, I2C_CLK_DIVISOR_REG, 205 __SHIFTIN(0x19, I2C_CLK_DIVISOR_STD_FAST_MODE) | 206 __SHIFTIN(0x1, I2C_CLK_DIVISOR_HSMODE)); 207 208 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 0); 209 I2C_WRITE(sc, I2C_CNFG_REG, 210 I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN); 211 I2C_SET_CLEAR(sc, I2C_SL_CNFG_REG, I2C_SL_CNFG_NEWSL, 0); 212 I2C_WRITE(sc, I2C_FIFO_CONTROL_REG, 213 __SHIFTIN(7, I2C_FIFO_CONTROL_TX_FIFO_TRIG) | 214 __SHIFTIN(0, I2C_FIFO_CONTROL_RX_FIFO_TRIG)); 215 216 I2C_WRITE(sc, I2C_BUS_CONFIG_LOAD_REG, 217 I2C_BUS_CONFIG_LOAD_MSTR_CONFIG_LOAD); 218 while (--retry > 0) { 219 if (I2C_READ(sc, I2C_BUS_CONFIG_LOAD_REG) == 0) 220 break; 221 delay(10); 222 } 223 if (retry == 0) { 224 device_printf(sc->sc_dev, "config load timeout\n"); 225 } 226 } 227 228 static int 229 tegra_i2c_intr(void *priv) 230 { 231 struct tegra_i2c_softc * const sc = priv; 232 233 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 234 if (istatus == 0) 235 return 0; 236 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 237 238 mutex_enter(&sc->sc_intr_lock); 239 cv_broadcast(&sc->sc_intr_wait); 240 mutex_exit(&sc->sc_intr_lock); 241 242 return 1; 243 } 244 245 static int 246 tegra_i2c_exec(void *priv, i2c_op_t op, i2c_addr_t addr, const void *cmdbuf, 247 size_t cmdlen, void *buf, size_t buflen, int flags) 248 { 249 struct tegra_i2c_softc * const sc = priv; 250 int retry, error; 251 252 /* 253 * XXXJRT This is probably no longer necessary? Before these 254 * changes, the bus lock was also used for the interrupt handler, 255 * and there would be a deadlock when the interrupt handler tried to 256 * acquire it again. The bus lock is now owned by the mid-layer and 257 * we have our own interrupt lock. 258 */ 259 flags |= I2C_F_POLL; 260 261 if (buflen == 0 && cmdlen == 0) 262 return EINVAL; 263 264 mutex_enter(&sc->sc_intr_lock); 265 266 if ((flags & I2C_F_POLL) == 0) { 267 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 268 I2C_INTERRUPT_MASK_NOACK | I2C_INTERRUPT_MASK_ARB_LOST | 269 I2C_INTERRUPT_MASK_TIMEOUT | 270 I2C_INTERRUPT_MASK_ALL_PACKETS_XFER_COMPLETE); 271 } 272 273 const uint32_t flush_mask = 274 I2C_FIFO_CONTROL_TX_FIFO_FLUSH | I2C_FIFO_CONTROL_RX_FIFO_FLUSH; 275 276 I2C_SET_CLEAR(sc, I2C_FIFO_CONTROL_REG, flush_mask, 0); 277 for (retry = 10000; retry > 0; retry--) { 278 const uint32_t v = I2C_READ(sc, I2C_FIFO_CONTROL_REG); 279 if ((v & flush_mask) == 0) 280 break; 281 delay(1); 282 } 283 if (retry == 0) { 284 mutex_exit(&sc->sc_intr_lock); 285 device_printf(sc->sc_dev, "timeout flushing FIFO\n"); 286 return EIO; 287 } 288 289 if (cmdlen > 0) { 290 error = tegra_i2c_write(sc, addr, cmdbuf, cmdlen, flags, 291 buflen > 0 ? true : false); 292 if (error) { 293 goto done; 294 } 295 } 296 297 if (buflen > 0) { 298 if (I2C_OP_READ_P(op)) { 299 error = tegra_i2c_read(sc, addr, buf, buflen, flags); 300 } else { 301 error = tegra_i2c_write(sc, addr, buf, buflen, flags, false); 302 } 303 } 304 305 done: 306 if ((flags & I2C_F_POLL) == 0) { 307 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 0); 308 } 309 310 if (error) { 311 tegra_i2c_init(sc); 312 } 313 314 mutex_exit(&sc->sc_intr_lock); 315 316 return error; 317 } 318 319 static int 320 tegra_i2c_wait(struct tegra_i2c_softc *sc, int flags) 321 { 322 int error, retry; 323 uint32_t stat = 0; 324 325 retry = (flags & I2C_F_POLL) ? 100000 : 100; 326 327 while (--retry > 0) { 328 if ((flags & I2C_F_POLL) == 0) { 329 error = cv_timedwait_sig(&sc->sc_intr_wait, 330 &sc->sc_intr_lock, 331 uimax(mstohz(10), 1)); 332 if (error) { 333 return error; 334 } 335 } 336 stat = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 337 if (stat & I2C_INTERRUPT_STATUS_PACKET_XFER_COMPLETE) { 338 break; 339 } 340 if (flags & I2C_F_POLL) { 341 delay(10); 342 } 343 } 344 if (retry == 0) { 345 #ifdef TEGRA_I2C_DEBUG 346 device_printf(sc->sc_dev, "timed out, status = %#x\n", stat); 347 #endif 348 return ETIMEDOUT; 349 } 350 351 const uint32_t err_mask = 352 I2C_INTERRUPT_STATUS_NOACK | 353 I2C_INTERRUPT_STATUS_ARB_LOST | 354 I2C_INTERRUPT_MASK_TIMEOUT; 355 356 if (stat & err_mask) { 357 device_printf(sc->sc_dev, "error, status = %#x\n", stat); 358 return EIO; 359 } 360 361 return 0; 362 } 363 364 static int 365 tegra_i2c_write(struct tegra_i2c_softc *sc, i2c_addr_t addr, const uint8_t *buf, 366 size_t buflen, int flags, bool repeat_start) 367 { 368 const uint8_t *p = buf; 369 size_t n, resid = buflen; 370 uint32_t data; 371 int retry; 372 373 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 374 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 375 376 /* Generic Header 0 */ 377 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 378 __SHIFTIN(I2C_IOPACKET_WORD0_PROTHDRSZ_REQ, 379 I2C_IOPACKET_WORD0_PROTHDRSZ) | 380 __SHIFTIN(sc->sc_cid, I2C_IOPACKET_WORD0_CONTROLLERID) | 381 __SHIFTIN(1, I2C_IOPACKET_WORD0_PKTID) | 382 __SHIFTIN(I2C_IOPACKET_WORD0_PROTOCOL_I2C, 383 I2C_IOPACKET_WORD0_PROTOCOL) | 384 __SHIFTIN(I2C_IOPACKET_WORD0_PKTTYPE_REQ, 385 I2C_IOPACKET_WORD0_PKTTYPE)); 386 /* Generic Header 1 */ 387 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 388 __SHIFTIN(buflen - 1, I2C_IOPACKET_WORD1_PAYLOADSIZE)); 389 /* I2C Master Transmit Packet Header */ 390 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 391 I2C_IOPACKET_XMITHDR_IE | 392 (repeat_start ? I2C_IOPACKET_XMITHDR_REPEAT_STARTSTOP : 0) | 393 __SHIFTIN((addr << 1), I2C_IOPACKET_XMITHDR_SLAVE_ADDR)); 394 395 /* Transmit data */ 396 while (resid > 0) { 397 retry = 10000; 398 while (--retry > 0) { 399 const uint32_t fs = I2C_READ(sc, I2C_FIFO_STATUS_REG); 400 const u_int cnt = 401 __SHIFTOUT(fs, I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT); 402 if (cnt > 0) 403 break; 404 delay(10); 405 } 406 if (retry == 0) { 407 device_printf(sc->sc_dev, "TX FIFO timeout\n"); 408 return ETIMEDOUT; 409 } 410 411 for (n = 0, data = 0; n < uimin(resid, 4); n++) { 412 data |= (uint32_t)p[n] << (n * 8); 413 } 414 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, data); 415 p += uimin(resid, 4); 416 resid -= uimin(resid, 4); 417 } 418 419 return tegra_i2c_wait(sc, flags); 420 } 421 422 static int 423 tegra_i2c_read(struct tegra_i2c_softc *sc, i2c_addr_t addr, uint8_t *buf, 424 size_t buflen, int flags) 425 { 426 uint8_t *p = buf; 427 size_t n, resid = buflen; 428 uint32_t data; 429 int retry; 430 431 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 432 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 433 434 /* Generic Header 0 */ 435 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 436 __SHIFTIN(I2C_IOPACKET_WORD0_PROTHDRSZ_REQ, 437 I2C_IOPACKET_WORD0_PROTHDRSZ) | 438 __SHIFTIN(sc->sc_cid, I2C_IOPACKET_WORD0_CONTROLLERID) | 439 __SHIFTIN(1, I2C_IOPACKET_WORD0_PKTID) | 440 __SHIFTIN(I2C_IOPACKET_WORD0_PROTOCOL_I2C, 441 I2C_IOPACKET_WORD0_PROTOCOL) | 442 __SHIFTIN(I2C_IOPACKET_WORD0_PKTTYPE_REQ, 443 I2C_IOPACKET_WORD0_PKTTYPE)); 444 /* Generic Header 1 */ 445 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 446 __SHIFTIN(buflen - 1, I2C_IOPACKET_WORD1_PAYLOADSIZE)); 447 /* I2C Master Transmit Packet Header */ 448 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 449 I2C_IOPACKET_XMITHDR_IE | I2C_IOPACKET_XMITHDR_READ | 450 __SHIFTIN((addr << 1) | 1, I2C_IOPACKET_XMITHDR_SLAVE_ADDR)); 451 452 while (resid > 0) { 453 retry = 10000; 454 while (--retry > 0) { 455 const uint32_t fs = I2C_READ(sc, I2C_FIFO_STATUS_REG); 456 const u_int cnt = 457 __SHIFTOUT(fs, I2C_FIFO_STATUS_RX_FIFO_FULL_CNT); 458 if (cnt > 0) 459 break; 460 delay(10); 461 } 462 if (retry == 0) { 463 device_printf(sc->sc_dev, "RX FIFO timeout\n"); 464 return ETIMEDOUT; 465 } 466 467 data = I2C_READ(sc, I2C_RX_FIFO_REG); 468 for (n = 0; n < uimin(resid, 4); n++) { 469 p[n] = (data >> (n * 8)) & 0xff; 470 } 471 p += uimin(resid, 4); 472 resid -= uimin(resid, 4); 473 } 474 475 return tegra_i2c_wait(sc, flags); 476 } 477
Indexes created Thu Oct 02 01:09:59 GMT 2025