tegra_i2c.c revision 1.2
1 /* $NetBSD: tegra_i2c.c,v 1.2 2015/05/16 21:31:39 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "locators.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: tegra_i2c.c,v 1.2 2015/05/16 21:31:39 jmcneill Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 41 #include <dev/i2c/i2cvar.h> 42 43 #include <arm/nvidia/tegra_reg.h> 44 #include <arm/nvidia/tegra_i2creg.h> 45 #include <arm/nvidia/tegra_var.h> 46 47 static int tegra_i2c_match(device_t, cfdata_t, void *); 48 static void tegra_i2c_attach(device_t, device_t, void *); 49 50 struct tegra_i2c_softc { 51 device_t sc_dev; 52 bus_space_tag_t sc_bst; 53 bus_space_handle_t sc_bsh; 54 void * sc_ih; 55 u_int sc_port; 56 57 struct i2c_controller sc_ic; 58 kmutex_t sc_lock; 59 kcondvar_t sc_cv; 60 device_t sc_i2cdev; 61 }; 62 63 static void tegra_i2c_init(struct tegra_i2c_softc *); 64 static int tegra_i2c_intr(void *); 65 66 static int tegra_i2c_acquire_bus(void *, int); 67 static void tegra_i2c_release_bus(void *, int); 68 static int tegra_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 69 size_t, void *, size_t, int); 70 71 static int tegra_i2c_wait(struct tegra_i2c_softc *, int); 72 static int tegra_i2c_write(struct tegra_i2c_softc *, i2c_addr_t, 73 const uint8_t *, size_t, int); 74 static int tegra_i2c_read(struct tegra_i2c_softc *, i2c_addr_t, uint8_t *, 75 size_t, int); 76 77 CFATTACH_DECL_NEW(tegra_i2c, sizeof(struct tegra_i2c_softc), 78 tegra_i2c_match, tegra_i2c_attach, NULL, NULL); 79 80 #define I2C_WRITE(sc, reg, val) \ 81 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 82 #define I2C_READ(sc, reg) \ 83 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 84 #define I2C_SET_CLEAR(sc, reg, setval, clrval) \ 85 tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (setval), (clrval)) 86 87 static int 88 tegra_i2c_match(device_t parent, cfdata_t cf, void *aux) 89 { 90 struct tegraio_attach_args * const tio = aux; 91 const struct tegra_locators * const loc = &tio->tio_loc; 92 93 if (loc->loc_port == TEGRAIOCF_PORT_DEFAULT) 94 return 0; 95 96 return 1; 97 } 98 99 static void 100 tegra_i2c_attach(device_t parent, device_t self, void *aux) 101 { 102 struct tegra_i2c_softc * const sc = device_private(self); 103 struct tegraio_attach_args * const tio = aux; 104 const struct tegra_locators * const loc = &tio->tio_loc; 105 struct i2cbus_attach_args iba; 106 107 sc->sc_dev = self; 108 sc->sc_bst = tio->tio_bst; 109 bus_space_subregion(tio->tio_bst, tio->tio_bsh, 110 loc->loc_offset, loc->loc_size, &sc->sc_bsh); 111 sc->sc_port = loc->loc_port; 112 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 113 cv_init(&sc->sc_cv, device_xname(self)); 114 115 aprint_naive("\n"); 116 aprint_normal(": I2C%d\n", loc->loc_port + 1); 117 118 sc->sc_ih = intr_establish(loc->loc_intr, IPL_VM, IST_LEVEL|IST_MPSAFE, 119 tegra_i2c_intr, sc); 120 if (sc->sc_ih == NULL) { 121 aprint_error_dev(self, "couldn't establish interrupt %d\n", 122 loc->loc_intr); 123 return; 124 } 125 aprint_normal_dev(self, "interrupting on irq %d\n", loc->loc_intr); 126 127 /* Recommended setting for standard mode */ 128 tegra_car_periph_i2c_enable(loc->loc_port, 204000000); 129 130 tegra_i2c_init(sc); 131 132 sc->sc_ic.ic_cookie = sc; 133 sc->sc_ic.ic_acquire_bus = tegra_i2c_acquire_bus; 134 sc->sc_ic.ic_release_bus = tegra_i2c_release_bus; 135 sc->sc_ic.ic_exec = tegra_i2c_exec; 136 137 iba.iba_tag = &sc->sc_ic; 138 sc->sc_i2cdev = config_found_ia(self, "i2cbus", &iba, iicbus_print); 139 } 140 141 static void 142 tegra_i2c_init(struct tegra_i2c_softc *sc) 143 { 144 I2C_WRITE(sc, I2C_CLK_DIVISOR_REG, 145 __SHIFTIN(0x19, I2C_CLK_DIVISOR_STD_FAST_MODE) | 146 __SHIFTIN(0x1, I2C_CLK_DIVISOR_HSMODE)); 147 148 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 0); 149 I2C_WRITE(sc, I2C_CNFG_REG, 150 I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN); 151 I2C_SET_CLEAR(sc, I2C_SL_CNFG_REG, I2C_SL_CNFG_NEWSL, 0); 152 } 153 154 static int 155 tegra_i2c_intr(void *priv) 156 { 157 struct tegra_i2c_softc * const sc = priv; 158 159 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 160 if (istatus == 0) 161 return 0; 162 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 163 164 mutex_enter(&sc->sc_lock); 165 cv_broadcast(&sc->sc_cv); 166 mutex_exit(&sc->sc_lock); 167 168 return 1; 169 } 170 171 static int 172 tegra_i2c_acquire_bus(void *priv, int flags) 173 { 174 struct tegra_i2c_softc * const sc = priv; 175 176 mutex_enter(&sc->sc_lock); 177 178 return 0; 179 } 180 181 static void 182 tegra_i2c_release_bus(void *priv, int flags) 183 { 184 struct tegra_i2c_softc * const sc = priv; 185 186 mutex_exit(&sc->sc_lock); 187 } 188 189 static int 190 tegra_i2c_exec(void *priv, i2c_op_t op, i2c_addr_t addr, const void *cmdbuf, 191 size_t cmdlen, void *buf, size_t buflen, int flags) 192 { 193 struct tegra_i2c_softc * const sc = priv; 194 int retry, error; 195 196 #if notyet 197 if (cold) 198 #endif 199 flags |= I2C_F_POLL; 200 201 KASSERT(mutex_owned(&sc->sc_lock)); 202 203 if ((flags & I2C_F_POLL) == 0) { 204 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 205 I2C_INTERRUPT_MASK_NOACK | I2C_INTERRUPT_MASK_ARB_LOST | 206 I2C_INTERRUPT_MASK_TIMEOUT | 207 I2C_INTERRUPT_MASK_ALL_PACKETS_XFER_COMPLETE); 208 } 209 210 const uint32_t flush_mask = 211 I2C_FIFO_CONTROL_TX_FIFO_FLUSH | I2C_FIFO_CONTROL_RX_FIFO_FLUSH; 212 213 I2C_SET_CLEAR(sc, I2C_FIFO_CONTROL_REG, flush_mask, 0); 214 for (retry = 10000; retry > 0; retry--) { 215 const uint32_t v = I2C_READ(sc, I2C_FIFO_CONTROL_REG); 216 if ((v & flush_mask) == 0) 217 break; 218 delay(1); 219 } 220 if (retry == 0) { 221 device_printf(sc->sc_dev, "timeout flushing FIFO\n"); 222 return EIO; 223 } 224 225 if (cmdlen > 0) { 226 error = tegra_i2c_write(sc, addr, cmdbuf, cmdlen, flags); 227 if (error) { 228 goto done; 229 } 230 } 231 232 if (I2C_OP_READ_P(op)) { 233 error = tegra_i2c_read(sc, addr, buf, buflen, flags); 234 } else { 235 error = tegra_i2c_write(sc, addr, buf, buflen, flags); 236 } 237 238 done: 239 if ((flags & I2C_F_POLL) == 0) { 240 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 0); 241 } 242 return error; 243 } 244 245 static int 246 tegra_i2c_wait(struct tegra_i2c_softc *sc, int flags) 247 { 248 int error, retry; 249 uint32_t stat = 0; 250 251 retry = (flags & I2C_F_POLL) ? 100000 : 100; 252 253 while (--retry > 0) { 254 if ((flags & I2C_F_POLL) == 0) { 255 error = cv_timedwait_sig(&sc->sc_cv, &sc->sc_lock, 256 max(mstohz(10), 1)); 257 if (error) { 258 return error; 259 } 260 } 261 stat = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 262 if (stat & I2C_INTERRUPT_STATUS_PACKET_XFER_COMPLETE) { 263 break; 264 } 265 if (flags & I2C_F_POLL) { 266 delay(10); 267 } 268 } 269 if (retry == 0) { 270 stat = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 271 device_printf(sc->sc_dev, "timed out, status = %#x\n", stat); 272 return ETIMEDOUT; 273 } 274 275 const uint32_t err_mask = 276 I2C_INTERRUPT_STATUS_NOACK | 277 I2C_INTERRUPT_STATUS_ARB_LOST | 278 I2C_INTERRUPT_MASK_TIMEOUT; 279 280 if (stat & err_mask) { 281 device_printf(sc->sc_dev, "error, status = %#x\n", stat); 282 return EIO; 283 } 284 285 return 0; 286 } 287 288 static int 289 tegra_i2c_write(struct tegra_i2c_softc *sc, i2c_addr_t addr, const uint8_t *buf, 290 size_t buflen, int flags) 291 { 292 const uint8_t *p = buf; 293 size_t n, resid = buflen; 294 uint32_t data; 295 int retry; 296 297 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 298 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 299 300 /* Generic Header 0 */ 301 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 302 __SHIFTIN(I2C_IOPACKET_WORD0_PROTHDRSZ_REQ, 303 I2C_IOPACKET_WORD0_PROTHDRSZ) | 304 __SHIFTIN(sc->sc_port, I2C_IOPACKET_WORD0_CONTROLLERID) | 305 __SHIFTIN(1, I2C_IOPACKET_WORD0_PKTID) | 306 __SHIFTIN(I2C_IOPACKET_WORD0_PROTOCOL_I2C, 307 I2C_IOPACKET_WORD0_PROTOCOL) | 308 __SHIFTIN(I2C_IOPACKET_WORD0_PKTTYPE_REQ, 309 I2C_IOPACKET_WORD0_PKTTYPE)); 310 /* Generic Header 1 */ 311 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 312 __SHIFTIN(buflen - 1, I2C_IOPACKET_WORD1_PAYLOADSIZE)); 313 /* I2C Master Transmit Packet Header */ 314 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 315 I2C_IOPACKET_XMITHDR_IE | 316 __SHIFTIN((addr << 1), I2C_IOPACKET_XMITHDR_SLAVE_ADDR)); 317 318 /* Transmit data */ 319 while (resid > 0) { 320 retry = 10000; 321 while (--retry > 0) { 322 const uint32_t fs = I2C_READ(sc, I2C_FIFO_STATUS_REG); 323 const u_int cnt = 324 __SHIFTOUT(fs, I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT); 325 if (cnt > 0) 326 break; 327 delay(10); 328 } 329 if (retry == 0) { 330 device_printf(sc->sc_dev, "TX FIFO timeout\n"); 331 return ETIMEDOUT; 332 } 333 334 for (n = 0, data = 0; n < min(resid, 4); n++) { 335 data |= (uint32_t)p[n] << (n * 8); 336 } 337 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, data); 338 resid -= min(resid, 4); 339 p += min(resid, 4); 340 } 341 342 return tegra_i2c_wait(sc, flags); 343 } 344 345 static int 346 tegra_i2c_read(struct tegra_i2c_softc *sc, i2c_addr_t addr, uint8_t *buf, 347 size_t buflen, int flags) 348 { 349 uint8_t *p = buf; 350 size_t n, resid = buflen; 351 uint32_t data; 352 int error, retry; 353 354 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 355 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 356 357 /* Generic Header 0 */ 358 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 359 __SHIFTIN(I2C_IOPACKET_WORD0_PROTHDRSZ_REQ, 360 I2C_IOPACKET_WORD0_PROTHDRSZ) | 361 __SHIFTIN(sc->sc_port, I2C_IOPACKET_WORD0_CONTROLLERID) | 362 __SHIFTIN(1, I2C_IOPACKET_WORD0_PKTID) | 363 __SHIFTIN(I2C_IOPACKET_WORD0_PROTOCOL_I2C, 364 I2C_IOPACKET_WORD0_PROTOCOL) | 365 __SHIFTIN(I2C_IOPACKET_WORD0_PKTTYPE_REQ, 366 I2C_IOPACKET_WORD0_PKTTYPE)); 367 /* Generic Header 1 */ 368 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 369 __SHIFTIN(buflen - 1, I2C_IOPACKET_WORD1_PAYLOADSIZE)); 370 /* I2C Master Transmit Packet Header */ 371 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 372 I2C_IOPACKET_XMITHDR_IE | I2C_IOPACKET_XMITHDR_READ | 373 __SHIFTIN((addr << 1) | 1, I2C_IOPACKET_XMITHDR_SLAVE_ADDR)); 374 375 if ((error = tegra_i2c_wait(sc, flags)) != 0) { 376 return error; 377 } 378 379 while (resid > 0) { 380 retry = 10000; 381 while (--retry > 0) { 382 const uint32_t fs = I2C_READ(sc, I2C_FIFO_STATUS_REG); 383 const u_int cnt = 384 __SHIFTOUT(fs, I2C_FIFO_STATUS_RX_FIFO_FULL_CNT); 385 if (cnt > 0) 386 break; 387 delay(10); 388 } 389 if (retry == 0) { 390 device_printf(sc->sc_dev, "RX FIFO timeout\n"); 391 return ETIMEDOUT; 392 } 393 394 data = I2C_READ(sc, I2C_RX_FIFO_REG); 395 for (n = 0; n < min(resid, 4); n++) { 396 p[n] = (data >> (n * 8)) & 0xff; 397 } 398 resid -= min(resid, 4); 399 p += min(resid, 4); 400 } 401 402 return 0; 403 } 404
Indexes created Thu Oct 02 01:09:59 GMT 2025