tegra_i2c.c revision 1.23.8.1
1 /* $NetBSD: tegra_i2c.c,v 1.23.8.1 2021/01/03 16:34:52 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_i2c.c,v 1.23.8.1 2021/01/03 16:34:52 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 39 #include <dev/i2c/i2cvar.h> 40 41 #include <arm/nvidia/tegra_reg.h> 42 #include <arm/nvidia/tegra_i2creg.h> 43 #include <arm/nvidia/tegra_var.h> 44 45 #include <dev/fdt/fdtvar.h> 46 47 static int tegra_i2c_match(device_t, cfdata_t, void *); 48 static void tegra_i2c_attach(device_t, device_t, void *); 49 50 struct tegra_i2c_softc { 51 device_t sc_dev; 52 bus_space_tag_t sc_bst; 53 bus_space_handle_t sc_bsh; 54 void * sc_ih; 55 struct clk * sc_clk; 56 struct fdtbus_reset * sc_rst; 57 u_int sc_cid; 58 59 struct i2c_controller sc_ic; 60 kmutex_t sc_intr_lock; 61 kcondvar_t sc_intr_wait; 62 }; 63 64 static void tegra_i2c_init(struct tegra_i2c_softc *); 65 static int tegra_i2c_intr(void *); 66 67 static int tegra_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 68 size_t, void *, size_t, int); 69 70 static int tegra_i2c_wait(struct tegra_i2c_softc *, int); 71 static int tegra_i2c_write(struct tegra_i2c_softc *, i2c_addr_t, 72 const uint8_t *, size_t, int, bool); 73 static int tegra_i2c_read(struct tegra_i2c_softc *, i2c_addr_t, uint8_t *, 74 size_t, int); 75 76 CFATTACH_DECL_NEW(tegra_i2c, sizeof(struct tegra_i2c_softc), 77 tegra_i2c_match, tegra_i2c_attach, NULL, NULL); 78 79 #define I2C_WRITE(sc, reg, val) \ 80 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 81 #define I2C_READ(sc, reg) \ 82 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 83 #define I2C_SET_CLEAR(sc, reg, setval, clrval) \ 84 tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (setval), (clrval)) 85 86 static int 87 tegra_i2c_match(device_t parent, cfdata_t cf, void *aux) 88 { 89 const char * const compatible[] = { 90 "nvidia,tegra210-i2c", 91 "nvidia,tegra124-i2c", 92 "nvidia,tegra114-i2c", 93 NULL 94 }; 95 struct fdt_attach_args * const faa = aux; 96 97 return of_match_compatible(faa->faa_phandle, compatible); 98 } 99 100 static void 101 tegra_i2c_attach(device_t parent, device_t self, void *aux) 102 { 103 struct tegra_i2c_softc * const sc = device_private(self); 104 struct fdt_attach_args * const faa = aux; 105 const int phandle = faa->faa_phandle; 106 char intrstr[128]; 107 bus_addr_t addr; 108 bus_size_t size; 109 int error; 110 111 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 112 aprint_error(": couldn't get registers\n"); 113 return; 114 } 115 sc->sc_clk = fdtbus_clock_get(phandle, "div-clk"); 116 if (sc->sc_clk == NULL) { 117 aprint_error(": couldn't get clock div-clk\n"); 118 return; 119 } 120 sc->sc_rst = fdtbus_reset_get(phandle, "i2c"); 121 if (sc->sc_rst == NULL) { 122 aprint_error(": couldn't get reset i2c\n"); 123 return; 124 } 125 126 sc->sc_dev = self; 127 sc->sc_bst = faa->faa_bst; 128 sc->sc_cid = device_unit(self); 129 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 130 if (error) { 131 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", 132 addr, error); 133 return; 134 } 135 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_VM); 136 cv_init(&sc->sc_intr_wait, device_xname(self)); 137 138 aprint_naive("\n"); 139 aprint_normal(": I2C\n"); 140 141 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 142 aprint_error_dev(self, "failed to decode interrupt\n"); 143 return; 144 } 145 146 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_VM, 147 FDT_INTR_MPSAFE, tegra_i2c_intr, sc); 148 if (sc->sc_ih == NULL) { 149 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 150 intrstr); 151 return; 152 } 153 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 154 155 /* 156 * Recommended setting for standard mode is to use an I2C source div 157 * of 20 (Tegra K1 Technical Reference Manual, Table 137) 158 */ 159 fdtbus_reset_assert(sc->sc_rst); 160 error = clk_set_rate(sc->sc_clk, 20400000); 161 if (error) { 162 aprint_error_dev(self, "couldn't set frequency: %d\n", error); 163 return; 164 } 165 error = clk_enable(sc->sc_clk); 166 if (error) { 167 aprint_error_dev(self, "couldn't enable clock: %d\n", error); 168 return; 169 } 170 fdtbus_reset_deassert(sc->sc_rst); 171 172 mutex_enter(&sc->sc_intr_lock); 173 tegra_i2c_init(sc); 174 mutex_exit(&sc->sc_intr_lock); 175 176 iic_tag_init(&sc->sc_ic); 177 sc->sc_ic.ic_cookie = sc; 178 sc->sc_ic.ic_exec = tegra_i2c_exec; 179 180 fdtbus_register_i2c_controller(&sc->sc_ic, phandle); 181 182 fdtbus_attach_i2cbus(self, phandle, &sc->sc_ic, iicbus_print); 183 } 184 185 static void 186 tegra_i2c_init(struct tegra_i2c_softc *sc) 187 { 188 int retry = 10000; 189 190 I2C_WRITE(sc, I2C_CLK_DIVISOR_REG, 191 __SHIFTIN(0x19, I2C_CLK_DIVISOR_STD_FAST_MODE) | 192 __SHIFTIN(0x1, I2C_CLK_DIVISOR_HSMODE)); 193 194 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 0); 195 I2C_WRITE(sc, I2C_CNFG_REG, 196 I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN); 197 I2C_SET_CLEAR(sc, I2C_SL_CNFG_REG, I2C_SL_CNFG_NEWSL, 0); 198 I2C_WRITE(sc, I2C_FIFO_CONTROL_REG, 199 __SHIFTIN(7, I2C_FIFO_CONTROL_TX_FIFO_TRIG) | 200 __SHIFTIN(0, I2C_FIFO_CONTROL_RX_FIFO_TRIG)); 201 202 I2C_WRITE(sc, I2C_BUS_CONFIG_LOAD_REG, 203 I2C_BUS_CONFIG_LOAD_MSTR_CONFIG_LOAD); 204 while (--retry > 0) { 205 if (I2C_READ(sc, I2C_BUS_CONFIG_LOAD_REG) == 0) 206 break; 207 delay(10); 208 } 209 if (retry == 0) { 210 device_printf(sc->sc_dev, "config load timeout\n"); 211 } 212 } 213 214 static int 215 tegra_i2c_intr(void *priv) 216 { 217 struct tegra_i2c_softc * const sc = priv; 218 219 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 220 if (istatus == 0) 221 return 0; 222 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 223 224 mutex_enter(&sc->sc_intr_lock); 225 cv_broadcast(&sc->sc_intr_wait); 226 mutex_exit(&sc->sc_intr_lock); 227 228 return 1; 229 } 230 231 static int 232 tegra_i2c_exec(void *priv, i2c_op_t op, i2c_addr_t addr, const void *cmdbuf, 233 size_t cmdlen, void *buf, size_t buflen, int flags) 234 { 235 struct tegra_i2c_softc * const sc = priv; 236 int retry, error; 237 238 /* 239 * XXXJRT This is probably no longer necessary? Before these 240 * changes, the bus lock was also used for the interrupt handler, 241 * and there would be a deadlock when the interrupt handler tried to 242 * acquire it again. The bus lock is now owned by the mid-layer and 243 * we have our own interrupt lock. 244 */ 245 flags |= I2C_F_POLL; 246 247 if (buflen == 0 && cmdlen == 0) 248 return EINVAL; 249 250 mutex_enter(&sc->sc_intr_lock); 251 252 if ((flags & I2C_F_POLL) == 0) { 253 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 254 I2C_INTERRUPT_MASK_NOACK | I2C_INTERRUPT_MASK_ARB_LOST | 255 I2C_INTERRUPT_MASK_TIMEOUT | 256 I2C_INTERRUPT_MASK_ALL_PACKETS_XFER_COMPLETE); 257 } 258 259 const uint32_t flush_mask = 260 I2C_FIFO_CONTROL_TX_FIFO_FLUSH | I2C_FIFO_CONTROL_RX_FIFO_FLUSH; 261 262 I2C_SET_CLEAR(sc, I2C_FIFO_CONTROL_REG, flush_mask, 0); 263 for (retry = 10000; retry > 0; retry--) { 264 const uint32_t v = I2C_READ(sc, I2C_FIFO_CONTROL_REG); 265 if ((v & flush_mask) == 0) 266 break; 267 delay(1); 268 } 269 if (retry == 0) { 270 mutex_exit(&sc->sc_intr_lock); 271 device_printf(sc->sc_dev, "timeout flushing FIFO\n"); 272 return EIO; 273 } 274 275 if (cmdlen > 0) { 276 error = tegra_i2c_write(sc, addr, cmdbuf, cmdlen, flags, 277 buflen > 0 ? true : false); 278 if (error) { 279 goto done; 280 } 281 } 282 283 if (buflen > 0) { 284 if (I2C_OP_READ_P(op)) { 285 error = tegra_i2c_read(sc, addr, buf, buflen, flags); 286 } else { 287 error = tegra_i2c_write(sc, addr, buf, buflen, flags, false); 288 } 289 } 290 291 done: 292 if ((flags & I2C_F_POLL) == 0) { 293 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 0); 294 } 295 296 if (error) { 297 tegra_i2c_init(sc); 298 } 299 300 mutex_exit(&sc->sc_intr_lock); 301 302 return error; 303 } 304 305 static int 306 tegra_i2c_wait(struct tegra_i2c_softc *sc, int flags) 307 { 308 int error, retry; 309 uint32_t stat = 0; 310 311 retry = (flags & I2C_F_POLL) ? 100000 : 100; 312 313 while (--retry > 0) { 314 if ((flags & I2C_F_POLL) == 0) { 315 error = cv_timedwait_sig(&sc->sc_intr_wait, 316 &sc->sc_intr_lock, 317 uimax(mstohz(10), 1)); 318 if (error) { 319 return error; 320 } 321 } 322 stat = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 323 if (stat & I2C_INTERRUPT_STATUS_PACKET_XFER_COMPLETE) { 324 break; 325 } 326 if (flags & I2C_F_POLL) { 327 delay(10); 328 } 329 } 330 if (retry == 0) { 331 #ifdef TEGRA_I2C_DEBUG 332 device_printf(sc->sc_dev, "timed out, status = %#x\n", stat); 333 #endif 334 return ETIMEDOUT; 335 } 336 337 const uint32_t err_mask = 338 I2C_INTERRUPT_STATUS_NOACK | 339 I2C_INTERRUPT_STATUS_ARB_LOST | 340 I2C_INTERRUPT_MASK_TIMEOUT; 341 342 if (stat & err_mask) { 343 device_printf(sc->sc_dev, "error, status = %#x\n", stat); 344 return EIO; 345 } 346 347 return 0; 348 } 349 350 static int 351 tegra_i2c_write(struct tegra_i2c_softc *sc, i2c_addr_t addr, const uint8_t *buf, 352 size_t buflen, int flags, bool repeat_start) 353 { 354 const uint8_t *p = buf; 355 size_t n, resid = buflen; 356 uint32_t data; 357 int retry; 358 359 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 360 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 361 362 /* Generic Header 0 */ 363 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 364 __SHIFTIN(I2C_IOPACKET_WORD0_PROTHDRSZ_REQ, 365 I2C_IOPACKET_WORD0_PROTHDRSZ) | 366 __SHIFTIN(sc->sc_cid, I2C_IOPACKET_WORD0_CONTROLLERID) | 367 __SHIFTIN(1, I2C_IOPACKET_WORD0_PKTID) | 368 __SHIFTIN(I2C_IOPACKET_WORD0_PROTOCOL_I2C, 369 I2C_IOPACKET_WORD0_PROTOCOL) | 370 __SHIFTIN(I2C_IOPACKET_WORD0_PKTTYPE_REQ, 371 I2C_IOPACKET_WORD0_PKTTYPE)); 372 /* Generic Header 1 */ 373 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 374 __SHIFTIN(buflen - 1, I2C_IOPACKET_WORD1_PAYLOADSIZE)); 375 /* I2C Master Transmit Packet Header */ 376 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 377 I2C_IOPACKET_XMITHDR_IE | 378 (repeat_start ? I2C_IOPACKET_XMITHDR_REPEAT_STARTSTOP : 0) | 379 __SHIFTIN((addr << 1), I2C_IOPACKET_XMITHDR_SLAVE_ADDR)); 380 381 /* Transmit data */ 382 while (resid > 0) { 383 retry = 10000; 384 while (--retry > 0) { 385 const uint32_t fs = I2C_READ(sc, I2C_FIFO_STATUS_REG); 386 const u_int cnt = 387 __SHIFTOUT(fs, I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT); 388 if (cnt > 0) 389 break; 390 delay(10); 391 } 392 if (retry == 0) { 393 device_printf(sc->sc_dev, "TX FIFO timeout\n"); 394 return ETIMEDOUT; 395 } 396 397 for (n = 0, data = 0; n < uimin(resid, 4); n++) { 398 data |= (uint32_t)p[n] << (n * 8); 399 } 400 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, data); 401 p += uimin(resid, 4); 402 resid -= uimin(resid, 4); 403 } 404 405 return tegra_i2c_wait(sc, flags); 406 } 407 408 static int 409 tegra_i2c_read(struct tegra_i2c_softc *sc, i2c_addr_t addr, uint8_t *buf, 410 size_t buflen, int flags) 411 { 412 uint8_t *p = buf; 413 size_t n, resid = buflen; 414 uint32_t data; 415 int retry; 416 417 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 418 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 419 420 /* Generic Header 0 */ 421 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 422 __SHIFTIN(I2C_IOPACKET_WORD0_PROTHDRSZ_REQ, 423 I2C_IOPACKET_WORD0_PROTHDRSZ) | 424 __SHIFTIN(sc->sc_cid, I2C_IOPACKET_WORD0_CONTROLLERID) | 425 __SHIFTIN(1, I2C_IOPACKET_WORD0_PKTID) | 426 __SHIFTIN(I2C_IOPACKET_WORD0_PROTOCOL_I2C, 427 I2C_IOPACKET_WORD0_PROTOCOL) | 428 __SHIFTIN(I2C_IOPACKET_WORD0_PKTTYPE_REQ, 429 I2C_IOPACKET_WORD0_PKTTYPE)); 430 /* Generic Header 1 */ 431 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 432 __SHIFTIN(buflen - 1, I2C_IOPACKET_WORD1_PAYLOADSIZE)); 433 /* I2C Master Transmit Packet Header */ 434 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 435 I2C_IOPACKET_XMITHDR_IE | I2C_IOPACKET_XMITHDR_READ | 436 __SHIFTIN((addr << 1) | 1, I2C_IOPACKET_XMITHDR_SLAVE_ADDR)); 437 438 while (resid > 0) { 439 retry = 10000; 440 while (--retry > 0) { 441 const uint32_t fs = I2C_READ(sc, I2C_FIFO_STATUS_REG); 442 const u_int cnt = 443 __SHIFTOUT(fs, I2C_FIFO_STATUS_RX_FIFO_FULL_CNT); 444 if (cnt > 0) 445 break; 446 delay(10); 447 } 448 if (retry == 0) { 449 device_printf(sc->sc_dev, "RX FIFO timeout\n"); 450 return ETIMEDOUT; 451 } 452 453 data = I2C_READ(sc, I2C_RX_FIFO_REG); 454 for (n = 0; n < uimin(resid, 4); n++) { 455 p[n] = (data >> (n * 8)) & 0xff; 456 } 457 p += uimin(resid, 4); 458 resid -= uimin(resid, 4); 459 } 460 461 return tegra_i2c_wait(sc, flags); 462 } 463
Indexes created Thu Oct 02 07:10:07 GMT 2025