tegra_i2c.c revision 1.26.4.1
1 /* $NetBSD: tegra_i2c.c,v 1.26.4.1 2021/05/19 03:14:24 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_i2c.c,v 1.26.4.1 2021/05/19 03:14:24 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 39 #include <dev/i2c/i2cvar.h> 40 41 #include <arm/nvidia/tegra_reg.h> 42 #include <arm/nvidia/tegra_i2creg.h> 43 #include <arm/nvidia/tegra_var.h> 44 45 #include <dev/fdt/fdtvar.h> 46 47 static int tegra_i2c_match(device_t, cfdata_t, void *); 48 static void tegra_i2c_attach(device_t, device_t, void *); 49 50 struct tegra_i2c_softc { 51 device_t sc_dev; 52 bus_space_tag_t sc_bst; 53 bus_space_handle_t sc_bsh; 54 void * sc_ih; 55 struct clk * sc_clk; 56 struct fdtbus_reset * sc_rst; 57 u_int sc_cid; 58 59 struct i2c_controller sc_ic; 60 kmutex_t sc_intr_lock; 61 kcondvar_t sc_intr_wait; 62 }; 63 64 static void tegra_i2c_init(struct tegra_i2c_softc *); 65 static int tegra_i2c_intr(void *); 66 67 static int tegra_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 68 size_t, void *, size_t, int); 69 70 static int tegra_i2c_wait(struct tegra_i2c_softc *, int); 71 static int tegra_i2c_write(struct tegra_i2c_softc *, i2c_addr_t, 72 const uint8_t *, size_t, int, bool); 73 static int tegra_i2c_read(struct tegra_i2c_softc *, i2c_addr_t, uint8_t *, 74 size_t, int); 75 76 CFATTACH_DECL_NEW(tegra_i2c, sizeof(struct tegra_i2c_softc), 77 tegra_i2c_match, tegra_i2c_attach, NULL, NULL); 78 79 #define I2C_WRITE(sc, reg, val) \ 80 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 81 #define I2C_READ(sc, reg) \ 82 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 83 #define I2C_SET_CLEAR(sc, reg, setval, clrval) \ 84 tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (setval), (clrval)) 85 86 static const struct device_compatible_entry compat_data[] = { 87 { .compat = "nvidia,tegra210-i2c" }, 88 { .compat = "nvidia,tegra124-i2c" }, 89 { .compat = "nvidia,tegra114-i2c" }, 90 DEVICE_COMPAT_EOL 91 }; 92 93 static int 94 tegra_i2c_match(device_t parent, cfdata_t cf, void *aux) 95 { 96 struct fdt_attach_args * const faa = aux; 97 98 return of_compatible_match(faa->faa_phandle, compat_data); 99 } 100 101 static void 102 tegra_i2c_attach(device_t parent, device_t self, void *aux) 103 { 104 struct tegra_i2c_softc * const sc = device_private(self); 105 struct fdt_attach_args * const faa = aux; 106 const int phandle = faa->faa_phandle; 107 char intrstr[128]; 108 bus_addr_t addr; 109 bus_size_t size; 110 int error; 111 112 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 113 aprint_error(": couldn't get registers\n"); 114 return; 115 } 116 sc->sc_clk = fdtbus_clock_get(phandle, "div-clk"); 117 if (sc->sc_clk == NULL) { 118 aprint_error(": couldn't get clock div-clk\n"); 119 return; 120 } 121 sc->sc_rst = fdtbus_reset_get(phandle, "i2c"); 122 if (sc->sc_rst == NULL) { 123 aprint_error(": couldn't get reset i2c\n"); 124 return; 125 } 126 127 sc->sc_dev = self; 128 sc->sc_bst = faa->faa_bst; 129 sc->sc_cid = device_unit(self); 130 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 131 if (error) { 132 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", 133 addr, error); 134 return; 135 } 136 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_VM); 137 cv_init(&sc->sc_intr_wait, device_xname(self)); 138 139 aprint_naive("\n"); 140 aprint_normal(": I2C\n"); 141 142 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 143 aprint_error_dev(self, "failed to decode interrupt\n"); 144 return; 145 } 146 147 sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_VM, 148 FDT_INTR_MPSAFE, tegra_i2c_intr, sc, device_xname(self)); 149 if (sc->sc_ih == NULL) { 150 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 151 intrstr); 152 return; 153 } 154 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 155 156 /* 157 * Recommended setting for standard mode is to use an I2C source div 158 * of 20 (Tegra K1 Technical Reference Manual, Table 137) 159 */ 160 fdtbus_reset_assert(sc->sc_rst); 161 error = clk_set_rate(sc->sc_clk, 20400000); 162 if (error) { 163 aprint_error_dev(self, "couldn't set frequency: %d\n", error); 164 return; 165 } 166 error = clk_enable(sc->sc_clk); 167 if (error) { 168 aprint_error_dev(self, "couldn't enable clock: %d\n", error); 169 return; 170 } 171 fdtbus_reset_deassert(sc->sc_rst); 172 173 mutex_enter(&sc->sc_intr_lock); 174 tegra_i2c_init(sc); 175 mutex_exit(&sc->sc_intr_lock); 176 177 iic_tag_init(&sc->sc_ic); 178 sc->sc_ic.ic_cookie = sc; 179 sc->sc_ic.ic_exec = tegra_i2c_exec; 180 181 fdtbus_register_i2c_controller(&sc->sc_ic, phandle); 182 183 struct i2cbus_attach_args iba = { 184 .iba_tag = &sc->sc_ic, 185 }; 186 config_found(self, &iba, iicbus_print, 187 CFARG_DEVHANDLE, device_handle(self), 188 CFARG_EOL); 189 } 190 191 static void 192 tegra_i2c_init(struct tegra_i2c_softc *sc) 193 { 194 int retry = 10000; 195 196 I2C_WRITE(sc, I2C_CLK_DIVISOR_REG, 197 __SHIFTIN(0x19, I2C_CLK_DIVISOR_STD_FAST_MODE) | 198 __SHIFTIN(0x1, I2C_CLK_DIVISOR_HSMODE)); 199 200 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 0); 201 I2C_WRITE(sc, I2C_CNFG_REG, 202 I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN); 203 I2C_SET_CLEAR(sc, I2C_SL_CNFG_REG, I2C_SL_CNFG_NEWSL, 0); 204 I2C_WRITE(sc, I2C_FIFO_CONTROL_REG, 205 __SHIFTIN(7, I2C_FIFO_CONTROL_TX_FIFO_TRIG) | 206 __SHIFTIN(0, I2C_FIFO_CONTROL_RX_FIFO_TRIG)); 207 208 I2C_WRITE(sc, I2C_BUS_CONFIG_LOAD_REG, 209 I2C_BUS_CONFIG_LOAD_MSTR_CONFIG_LOAD); 210 while (--retry > 0) { 211 if (I2C_READ(sc, I2C_BUS_CONFIG_LOAD_REG) == 0) 212 break; 213 delay(10); 214 } 215 if (retry == 0) { 216 device_printf(sc->sc_dev, "config load timeout\n"); 217 } 218 } 219 220 static int 221 tegra_i2c_intr(void *priv) 222 { 223 struct tegra_i2c_softc * const sc = priv; 224 225 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 226 if (istatus == 0) 227 return 0; 228 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 229 230 mutex_enter(&sc->sc_intr_lock); 231 cv_broadcast(&sc->sc_intr_wait); 232 mutex_exit(&sc->sc_intr_lock); 233 234 return 1; 235 } 236 237 static int 238 tegra_i2c_exec(void *priv, i2c_op_t op, i2c_addr_t addr, const void *cmdbuf, 239 size_t cmdlen, void *buf, size_t buflen, int flags) 240 { 241 struct tegra_i2c_softc * const sc = priv; 242 int retry, error; 243 244 /* 245 * XXXJRT This is probably no longer necessary? Before these 246 * changes, the bus lock was also used for the interrupt handler, 247 * and there would be a deadlock when the interrupt handler tried to 248 * acquire it again. The bus lock is now owned by the mid-layer and 249 * we have our own interrupt lock. 250 */ 251 flags |= I2C_F_POLL; 252 253 if (buflen == 0 && cmdlen == 0) 254 return EINVAL; 255 256 mutex_enter(&sc->sc_intr_lock); 257 258 if ((flags & I2C_F_POLL) == 0) { 259 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 260 I2C_INTERRUPT_MASK_NOACK | I2C_INTERRUPT_MASK_ARB_LOST | 261 I2C_INTERRUPT_MASK_TIMEOUT | 262 I2C_INTERRUPT_MASK_ALL_PACKETS_XFER_COMPLETE); 263 } 264 265 const uint32_t flush_mask = 266 I2C_FIFO_CONTROL_TX_FIFO_FLUSH | I2C_FIFO_CONTROL_RX_FIFO_FLUSH; 267 268 I2C_SET_CLEAR(sc, I2C_FIFO_CONTROL_REG, flush_mask, 0); 269 for (retry = 10000; retry > 0; retry--) { 270 const uint32_t v = I2C_READ(sc, I2C_FIFO_CONTROL_REG); 271 if ((v & flush_mask) == 0) 272 break; 273 delay(1); 274 } 275 if (retry == 0) { 276 mutex_exit(&sc->sc_intr_lock); 277 device_printf(sc->sc_dev, "timeout flushing FIFO\n"); 278 return EIO; 279 } 280 281 if (cmdlen > 0) { 282 error = tegra_i2c_write(sc, addr, cmdbuf, cmdlen, flags, 283 buflen > 0 ? true : false); 284 if (error) { 285 goto done; 286 } 287 } 288 289 if (buflen > 0) { 290 if (I2C_OP_READ_P(op)) { 291 error = tegra_i2c_read(sc, addr, buf, buflen, flags); 292 } else { 293 error = tegra_i2c_write(sc, addr, buf, buflen, flags, false); 294 } 295 } 296 297 done: 298 if ((flags & I2C_F_POLL) == 0) { 299 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 0); 300 } 301 302 if (error) { 303 tegra_i2c_init(sc); 304 } 305 306 mutex_exit(&sc->sc_intr_lock); 307 308 return error; 309 } 310 311 static int 312 tegra_i2c_wait(struct tegra_i2c_softc *sc, int flags) 313 { 314 int error, retry; 315 uint32_t stat = 0; 316 317 retry = (flags & I2C_F_POLL) ? 100000 : 100; 318 319 while (--retry > 0) { 320 if ((flags & I2C_F_POLL) == 0) { 321 error = cv_timedwait_sig(&sc->sc_intr_wait, 322 &sc->sc_intr_lock, 323 uimax(mstohz(10), 1)); 324 if (error) { 325 return error; 326 } 327 } 328 stat = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 329 if (stat & I2C_INTERRUPT_STATUS_PACKET_XFER_COMPLETE) { 330 break; 331 } 332 if (flags & I2C_F_POLL) { 333 delay(10); 334 } 335 } 336 if (retry == 0) { 337 #ifdef TEGRA_I2C_DEBUG 338 device_printf(sc->sc_dev, "timed out, status = %#x\n", stat); 339 #endif 340 return ETIMEDOUT; 341 } 342 343 const uint32_t err_mask = 344 I2C_INTERRUPT_STATUS_NOACK | 345 I2C_INTERRUPT_STATUS_ARB_LOST | 346 I2C_INTERRUPT_MASK_TIMEOUT; 347 348 if (stat & err_mask) { 349 device_printf(sc->sc_dev, "error, status = %#x\n", stat); 350 return EIO; 351 } 352 353 return 0; 354 } 355 356 static int 357 tegra_i2c_write(struct tegra_i2c_softc *sc, i2c_addr_t addr, const uint8_t *buf, 358 size_t buflen, int flags, bool repeat_start) 359 { 360 const uint8_t *p = buf; 361 size_t n, resid = buflen; 362 uint32_t data; 363 int retry; 364 365 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 366 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 367 368 /* Generic Header 0 */ 369 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 370 __SHIFTIN(I2C_IOPACKET_WORD0_PROTHDRSZ_REQ, 371 I2C_IOPACKET_WORD0_PROTHDRSZ) | 372 __SHIFTIN(sc->sc_cid, I2C_IOPACKET_WORD0_CONTROLLERID) | 373 __SHIFTIN(1, I2C_IOPACKET_WORD0_PKTID) | 374 __SHIFTIN(I2C_IOPACKET_WORD0_PROTOCOL_I2C, 375 I2C_IOPACKET_WORD0_PROTOCOL) | 376 __SHIFTIN(I2C_IOPACKET_WORD0_PKTTYPE_REQ, 377 I2C_IOPACKET_WORD0_PKTTYPE)); 378 /* Generic Header 1 */ 379 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 380 __SHIFTIN(buflen - 1, I2C_IOPACKET_WORD1_PAYLOADSIZE)); 381 /* I2C Master Transmit Packet Header */ 382 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 383 I2C_IOPACKET_XMITHDR_IE | 384 (repeat_start ? I2C_IOPACKET_XMITHDR_REPEAT_STARTSTOP : 0) | 385 __SHIFTIN((addr << 1), I2C_IOPACKET_XMITHDR_SLAVE_ADDR)); 386 387 /* Transmit data */ 388 while (resid > 0) { 389 retry = 10000; 390 while (--retry > 0) { 391 const uint32_t fs = I2C_READ(sc, I2C_FIFO_STATUS_REG); 392 const u_int cnt = 393 __SHIFTOUT(fs, I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT); 394 if (cnt > 0) 395 break; 396 delay(10); 397 } 398 if (retry == 0) { 399 device_printf(sc->sc_dev, "TX FIFO timeout\n"); 400 return ETIMEDOUT; 401 } 402 403 for (n = 0, data = 0; n < uimin(resid, 4); n++) { 404 data |= (uint32_t)p[n] << (n * 8); 405 } 406 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, data); 407 p += uimin(resid, 4); 408 resid -= uimin(resid, 4); 409 } 410 411 return tegra_i2c_wait(sc, flags); 412 } 413 414 static int 415 tegra_i2c_read(struct tegra_i2c_softc *sc, i2c_addr_t addr, uint8_t *buf, 416 size_t buflen, int flags) 417 { 418 uint8_t *p = buf; 419 size_t n, resid = buflen; 420 uint32_t data; 421 int retry; 422 423 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 424 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 425 426 /* Generic Header 0 */ 427 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 428 __SHIFTIN(I2C_IOPACKET_WORD0_PROTHDRSZ_REQ, 429 I2C_IOPACKET_WORD0_PROTHDRSZ) | 430 __SHIFTIN(sc->sc_cid, I2C_IOPACKET_WORD0_CONTROLLERID) | 431 __SHIFTIN(1, I2C_IOPACKET_WORD0_PKTID) | 432 __SHIFTIN(I2C_IOPACKET_WORD0_PROTOCOL_I2C, 433 I2C_IOPACKET_WORD0_PROTOCOL) | 434 __SHIFTIN(I2C_IOPACKET_WORD0_PKTTYPE_REQ, 435 I2C_IOPACKET_WORD0_PKTTYPE)); 436 /* Generic Header 1 */ 437 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 438 __SHIFTIN(buflen - 1, I2C_IOPACKET_WORD1_PAYLOADSIZE)); 439 /* I2C Master Transmit Packet Header */ 440 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 441 I2C_IOPACKET_XMITHDR_IE | I2C_IOPACKET_XMITHDR_READ | 442 __SHIFTIN((addr << 1) | 1, I2C_IOPACKET_XMITHDR_SLAVE_ADDR)); 443 444 while (resid > 0) { 445 retry = 10000; 446 while (--retry > 0) { 447 const uint32_t fs = I2C_READ(sc, I2C_FIFO_STATUS_REG); 448 const u_int cnt = 449 __SHIFTOUT(fs, I2C_FIFO_STATUS_RX_FIFO_FULL_CNT); 450 if (cnt > 0) 451 break; 452 delay(10); 453 } 454 if (retry == 0) { 455 device_printf(sc->sc_dev, "RX FIFO timeout\n"); 456 return ETIMEDOUT; 457 } 458 459 data = I2C_READ(sc, I2C_RX_FIFO_REG); 460 for (n = 0; n < uimin(resid, 4); n++) { 461 p[n] = (data >> (n * 8)) & 0xff; 462 } 463 p += uimin(resid, 4); 464 resid -= uimin(resid, 4); 465 } 466 467 return tegra_i2c_wait(sc, flags); 468 } 469
Indexes created Thu Oct 02 01:09:59 GMT 2025