tegra_i2c.c revision 1.27
1 /* $NetBSD: tegra_i2c.c,v 1.27 2025/09/16 11:41:25 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_i2c.c,v 1.27 2025/09/16 11:41:25 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 39 #include <dev/i2c/i2cvar.h> 40 41 #include <arm/nvidia/tegra_reg.h> 42 #include <arm/nvidia/tegra_i2creg.h> 43 #include <arm/nvidia/tegra_var.h> 44 45 #include <dev/fdt/fdtvar.h> 46 47 static int tegra_i2c_match(device_t, cfdata_t, void *); 48 static void tegra_i2c_attach(device_t, device_t, void *); 49 50 struct tegra_i2c_softc { 51 device_t sc_dev; 52 bus_space_tag_t sc_bst; 53 bus_space_handle_t sc_bsh; 54 void * sc_ih; 55 struct clk * sc_clk; 56 struct fdtbus_reset * sc_rst; 57 u_int sc_cid; 58 59 struct i2c_controller sc_ic; 60 kmutex_t sc_intr_lock; 61 kcondvar_t sc_intr_wait; 62 }; 63 64 static void tegra_i2c_init(struct tegra_i2c_softc *); 65 static int tegra_i2c_intr(void *); 66 67 static int tegra_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 68 size_t, void *, size_t, int); 69 70 static int tegra_i2c_wait(struct tegra_i2c_softc *, int); 71 static int tegra_i2c_write(struct tegra_i2c_softc *, i2c_addr_t, 72 const uint8_t *, size_t, int, bool); 73 static int tegra_i2c_read(struct tegra_i2c_softc *, i2c_addr_t, uint8_t *, 74 size_t, int); 75 76 CFATTACH_DECL_NEW(tegra_i2c, sizeof(struct tegra_i2c_softc), 77 tegra_i2c_match, tegra_i2c_attach, NULL, NULL); 78 79 #define I2C_WRITE(sc, reg, val) \ 80 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 81 #define I2C_READ(sc, reg) \ 82 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 83 #define I2C_SET_CLEAR(sc, reg, setval, clrval) \ 84 tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (setval), (clrval)) 85 86 static const struct device_compatible_entry compat_data[] = { 87 { .compat = "nvidia,tegra210-i2c" }, 88 { .compat = "nvidia,tegra124-i2c" }, 89 { .compat = "nvidia,tegra114-i2c" }, 90 DEVICE_COMPAT_EOL 91 }; 92 93 static int 94 tegra_i2c_match(device_t parent, cfdata_t cf, void *aux) 95 { 96 struct fdt_attach_args * const faa = aux; 97 98 return of_compatible_match(faa->faa_phandle, compat_data); 99 } 100 101 static void 102 tegra_i2c_attach(device_t parent, device_t self, void *aux) 103 { 104 struct tegra_i2c_softc * const sc = device_private(self); 105 struct fdt_attach_args * const faa = aux; 106 const int phandle = faa->faa_phandle; 107 char intrstr[128]; 108 bus_addr_t addr; 109 bus_size_t size; 110 int error; 111 112 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 113 aprint_error(": couldn't get registers\n"); 114 return; 115 } 116 sc->sc_clk = fdtbus_clock_get(phandle, "div-clk"); 117 if (sc->sc_clk == NULL) { 118 aprint_error(": couldn't get clock div-clk\n"); 119 return; 120 } 121 sc->sc_rst = fdtbus_reset_get(phandle, "i2c"); 122 if (sc->sc_rst == NULL) { 123 aprint_error(": couldn't get reset i2c\n"); 124 return; 125 } 126 127 sc->sc_dev = self; 128 sc->sc_bst = faa->faa_bst; 129 sc->sc_cid = device_unit(self); 130 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 131 if (error) { 132 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", 133 addr, error); 134 return; 135 } 136 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_VM); 137 cv_init(&sc->sc_intr_wait, device_xname(self)); 138 139 aprint_naive("\n"); 140 aprint_normal(": I2C\n"); 141 142 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 143 aprint_error_dev(self, "failed to decode interrupt\n"); 144 return; 145 } 146 147 sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_VM, 148 FDT_INTR_MPSAFE, tegra_i2c_intr, sc, device_xname(self)); 149 if (sc->sc_ih == NULL) { 150 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 151 intrstr); 152 return; 153 } 154 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 155 156 /* 157 * Recommended setting for standard mode is to use an I2C source div 158 * of 20 (Tegra K1 Technical Reference Manual, Table 137) 159 */ 160 fdtbus_reset_assert(sc->sc_rst); 161 error = clk_set_rate(sc->sc_clk, 20400000); 162 if (error) { 163 aprint_error_dev(self, "couldn't set frequency: %d\n", error); 164 return; 165 } 166 error = clk_enable(sc->sc_clk); 167 if (error) { 168 aprint_error_dev(self, "couldn't enable clock: %d\n", error); 169 return; 170 } 171 fdtbus_reset_deassert(sc->sc_rst); 172 173 mutex_enter(&sc->sc_intr_lock); 174 tegra_i2c_init(sc); 175 mutex_exit(&sc->sc_intr_lock); 176 177 iic_tag_init(&sc->sc_ic); 178 sc->sc_ic.ic_cookie = sc; 179 sc->sc_ic.ic_exec = tegra_i2c_exec; 180 181 fdtbus_register_i2c_controller(&sc->sc_ic, phandle); 182 183 iicbus_attach(self, &sc->sc_ic); 184 } 185 186 static void 187 tegra_i2c_init(struct tegra_i2c_softc *sc) 188 { 189 int retry = 10000; 190 191 I2C_WRITE(sc, I2C_CLK_DIVISOR_REG, 192 __SHIFTIN(0x19, I2C_CLK_DIVISOR_STD_FAST_MODE) | 193 __SHIFTIN(0x1, I2C_CLK_DIVISOR_HSMODE)); 194 195 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 0); 196 I2C_WRITE(sc, I2C_CNFG_REG, 197 I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN); 198 I2C_SET_CLEAR(sc, I2C_SL_CNFG_REG, I2C_SL_CNFG_NEWSL, 0); 199 I2C_WRITE(sc, I2C_FIFO_CONTROL_REG, 200 __SHIFTIN(7, I2C_FIFO_CONTROL_TX_FIFO_TRIG) | 201 __SHIFTIN(0, I2C_FIFO_CONTROL_RX_FIFO_TRIG)); 202 203 I2C_WRITE(sc, I2C_BUS_CONFIG_LOAD_REG, 204 I2C_BUS_CONFIG_LOAD_MSTR_CONFIG_LOAD); 205 while (--retry > 0) { 206 if (I2C_READ(sc, I2C_BUS_CONFIG_LOAD_REG) == 0) 207 break; 208 delay(10); 209 } 210 if (retry == 0) { 211 device_printf(sc->sc_dev, "config load timeout\n"); 212 } 213 } 214 215 static int 216 tegra_i2c_intr(void *priv) 217 { 218 struct tegra_i2c_softc * const sc = priv; 219 220 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 221 if (istatus == 0) 222 return 0; 223 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 224 225 mutex_enter(&sc->sc_intr_lock); 226 cv_broadcast(&sc->sc_intr_wait); 227 mutex_exit(&sc->sc_intr_lock); 228 229 return 1; 230 } 231 232 static int 233 tegra_i2c_exec(void *priv, i2c_op_t op, i2c_addr_t addr, const void *cmdbuf, 234 size_t cmdlen, void *buf, size_t buflen, int flags) 235 { 236 struct tegra_i2c_softc * const sc = priv; 237 int retry, error; 238 239 /* 240 * XXXJRT This is probably no longer necessary? Before these 241 * changes, the bus lock was also used for the interrupt handler, 242 * and there would be a deadlock when the interrupt handler tried to 243 * acquire it again. The bus lock is now owned by the mid-layer and 244 * we have our own interrupt lock. 245 */ 246 flags |= I2C_F_POLL; 247 248 if (buflen == 0 && cmdlen == 0) 249 return EINVAL; 250 251 mutex_enter(&sc->sc_intr_lock); 252 253 if ((flags & I2C_F_POLL) == 0) { 254 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 255 I2C_INTERRUPT_MASK_NOACK | I2C_INTERRUPT_MASK_ARB_LOST | 256 I2C_INTERRUPT_MASK_TIMEOUT | 257 I2C_INTERRUPT_MASK_ALL_PACKETS_XFER_COMPLETE); 258 } 259 260 const uint32_t flush_mask = 261 I2C_FIFO_CONTROL_TX_FIFO_FLUSH | I2C_FIFO_CONTROL_RX_FIFO_FLUSH; 262 263 I2C_SET_CLEAR(sc, I2C_FIFO_CONTROL_REG, flush_mask, 0); 264 for (retry = 10000; retry > 0; retry--) { 265 const uint32_t v = I2C_READ(sc, I2C_FIFO_CONTROL_REG); 266 if ((v & flush_mask) == 0) 267 break; 268 delay(1); 269 } 270 if (retry == 0) { 271 mutex_exit(&sc->sc_intr_lock); 272 device_printf(sc->sc_dev, "timeout flushing FIFO\n"); 273 return EIO; 274 } 275 276 if (cmdlen > 0) { 277 error = tegra_i2c_write(sc, addr, cmdbuf, cmdlen, flags, 278 buflen > 0 ? true : false); 279 if (error) { 280 goto done; 281 } 282 } 283 284 if (buflen > 0) { 285 if (I2C_OP_READ_P(op)) { 286 error = tegra_i2c_read(sc, addr, buf, buflen, flags); 287 } else { 288 error = tegra_i2c_write(sc, addr, buf, buflen, flags, false); 289 } 290 } 291 292 done: 293 if ((flags & I2C_F_POLL) == 0) { 294 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 0); 295 } 296 297 if (error) { 298 tegra_i2c_init(sc); 299 } 300 301 mutex_exit(&sc->sc_intr_lock); 302 303 return error; 304 } 305 306 static int 307 tegra_i2c_wait(struct tegra_i2c_softc *sc, int flags) 308 { 309 int error, retry; 310 uint32_t stat = 0; 311 312 retry = (flags & I2C_F_POLL) ? 100000 : 100; 313 314 while (--retry > 0) { 315 if ((flags & I2C_F_POLL) == 0) { 316 error = cv_timedwait_sig(&sc->sc_intr_wait, 317 &sc->sc_intr_lock, 318 uimax(mstohz(10), 1)); 319 if (error) { 320 return error; 321 } 322 } 323 stat = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 324 if (stat & I2C_INTERRUPT_STATUS_PACKET_XFER_COMPLETE) { 325 break; 326 } 327 if (flags & I2C_F_POLL) { 328 delay(10); 329 } 330 } 331 if (retry == 0) { 332 #ifdef TEGRA_I2C_DEBUG 333 device_printf(sc->sc_dev, "timed out, status = %#x\n", stat); 334 #endif 335 return ETIMEDOUT; 336 } 337 338 const uint32_t err_mask = 339 I2C_INTERRUPT_STATUS_NOACK | 340 I2C_INTERRUPT_STATUS_ARB_LOST | 341 I2C_INTERRUPT_MASK_TIMEOUT; 342 343 if (stat & err_mask) { 344 device_printf(sc->sc_dev, "error, status = %#x\n", stat); 345 return EIO; 346 } 347 348 return 0; 349 } 350 351 static int 352 tegra_i2c_write(struct tegra_i2c_softc *sc, i2c_addr_t addr, const uint8_t *buf, 353 size_t buflen, int flags, bool repeat_start) 354 { 355 const uint8_t *p = buf; 356 size_t n, resid = buflen; 357 uint32_t data; 358 int retry; 359 360 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 361 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 362 363 /* Generic Header 0 */ 364 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 365 __SHIFTIN(I2C_IOPACKET_WORD0_PROTHDRSZ_REQ, 366 I2C_IOPACKET_WORD0_PROTHDRSZ) | 367 __SHIFTIN(sc->sc_cid, I2C_IOPACKET_WORD0_CONTROLLERID) | 368 __SHIFTIN(1, I2C_IOPACKET_WORD0_PKTID) | 369 __SHIFTIN(I2C_IOPACKET_WORD0_PROTOCOL_I2C, 370 I2C_IOPACKET_WORD0_PROTOCOL) | 371 __SHIFTIN(I2C_IOPACKET_WORD0_PKTTYPE_REQ, 372 I2C_IOPACKET_WORD0_PKTTYPE)); 373 /* Generic Header 1 */ 374 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 375 __SHIFTIN(buflen - 1, I2C_IOPACKET_WORD1_PAYLOADSIZE)); 376 /* I2C Master Transmit Packet Header */ 377 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 378 I2C_IOPACKET_XMITHDR_IE | 379 (repeat_start ? I2C_IOPACKET_XMITHDR_REPEAT_STARTSTOP : 0) | 380 __SHIFTIN((addr << 1), I2C_IOPACKET_XMITHDR_SLAVE_ADDR)); 381 382 /* Transmit data */ 383 while (resid > 0) { 384 retry = 10000; 385 while (--retry > 0) { 386 const uint32_t fs = I2C_READ(sc, I2C_FIFO_STATUS_REG); 387 const u_int cnt = 388 __SHIFTOUT(fs, I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT); 389 if (cnt > 0) 390 break; 391 delay(10); 392 } 393 if (retry == 0) { 394 device_printf(sc->sc_dev, "TX FIFO timeout\n"); 395 return ETIMEDOUT; 396 } 397 398 for (n = 0, data = 0; n < uimin(resid, 4); n++) { 399 data |= (uint32_t)p[n] << (n * 8); 400 } 401 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, data); 402 p += uimin(resid, 4); 403 resid -= uimin(resid, 4); 404 } 405 406 return tegra_i2c_wait(sc, flags); 407 } 408 409 static int 410 tegra_i2c_read(struct tegra_i2c_softc *sc, i2c_addr_t addr, uint8_t *buf, 411 size_t buflen, int flags) 412 { 413 uint8_t *p = buf; 414 size_t n, resid = buflen; 415 uint32_t data; 416 int retry; 417 418 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 419 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 420 421 /* Generic Header 0 */ 422 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 423 __SHIFTIN(I2C_IOPACKET_WORD0_PROTHDRSZ_REQ, 424 I2C_IOPACKET_WORD0_PROTHDRSZ) | 425 __SHIFTIN(sc->sc_cid, I2C_IOPACKET_WORD0_CONTROLLERID) | 426 __SHIFTIN(1, I2C_IOPACKET_WORD0_PKTID) | 427 __SHIFTIN(I2C_IOPACKET_WORD0_PROTOCOL_I2C, 428 I2C_IOPACKET_WORD0_PROTOCOL) | 429 __SHIFTIN(I2C_IOPACKET_WORD0_PKTTYPE_REQ, 430 I2C_IOPACKET_WORD0_PKTTYPE)); 431 /* Generic Header 1 */ 432 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 433 __SHIFTIN(buflen - 1, I2C_IOPACKET_WORD1_PAYLOADSIZE)); 434 /* I2C Master Transmit Packet Header */ 435 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 436 I2C_IOPACKET_XMITHDR_IE | I2C_IOPACKET_XMITHDR_READ | 437 __SHIFTIN((addr << 1) | 1, I2C_IOPACKET_XMITHDR_SLAVE_ADDR)); 438 439 while (resid > 0) { 440 retry = 10000; 441 while (--retry > 0) { 442 const uint32_t fs = I2C_READ(sc, I2C_FIFO_STATUS_REG); 443 const u_int cnt = 444 __SHIFTOUT(fs, I2C_FIFO_STATUS_RX_FIFO_FULL_CNT); 445 if (cnt > 0) 446 break; 447 delay(10); 448 } 449 if (retry == 0) { 450 device_printf(sc->sc_dev, "RX FIFO timeout\n"); 451 return ETIMEDOUT; 452 } 453 454 data = I2C_READ(sc, I2C_RX_FIFO_REG); 455 for (n = 0; n < uimin(resid, 4); n++) { 456 p[n] = (data >> (n * 8)) & 0xff; 457 } 458 p += uimin(resid, 4); 459 resid -= uimin(resid, 4); 460 } 461 462 return tegra_i2c_wait(sc, flags); 463 } 464
Indexes created Thu Oct 02 01:09:59 GMT 2025