tegra_i2c.c revision 1.28
1 /* $NetBSD: tegra_i2c.c,v 1.28 2025/09/16 11:55:16 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_i2c.c,v 1.28 2025/09/16 11:55:16 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 39 #include <dev/i2c/i2cvar.h> 40 41 #include <arm/nvidia/tegra_reg.h> 42 #include <arm/nvidia/tegra_i2creg.h> 43 #include <arm/nvidia/tegra_var.h> 44 45 #include <dev/fdt/fdtvar.h> 46 47 static int tegra_i2c_match(device_t, cfdata_t, void *); 48 static void tegra_i2c_attach(device_t, device_t, void *); 49 50 struct tegra_i2c_softc { 51 device_t sc_dev; 52 bus_space_tag_t sc_bst; 53 bus_space_handle_t sc_bsh; 54 void * sc_ih; 55 struct clk * sc_clk; 56 struct fdtbus_reset * sc_rst; 57 u_int sc_cid; 58 59 struct i2c_controller sc_ic; 60 kmutex_t sc_intr_lock; 61 kcondvar_t sc_intr_wait; 62 }; 63 64 static void tegra_i2c_init(struct tegra_i2c_softc *); 65 static int tegra_i2c_intr(void *); 66 67 static int tegra_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 68 size_t, void *, size_t, int); 69 70 static int tegra_i2c_wait(struct tegra_i2c_softc *, int); 71 static int tegra_i2c_write(struct tegra_i2c_softc *, i2c_addr_t, 72 const uint8_t *, size_t, int, bool); 73 static int tegra_i2c_read(struct tegra_i2c_softc *, i2c_addr_t, uint8_t *, 74 size_t, int); 75 76 CFATTACH_DECL_NEW(tegra_i2c, sizeof(struct tegra_i2c_softc), 77 tegra_i2c_match, tegra_i2c_attach, NULL, NULL); 78 79 #define I2C_WRITE(sc, reg, val) \ 80 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 81 #define I2C_READ(sc, reg) \ 82 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 83 #define I2C_SET_CLEAR(sc, reg, setval, clrval) \ 84 tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (setval), (clrval)) 85 86 static const struct device_compatible_entry compat_data[] = { 87 { .compat = "nvidia,tegra210-i2c" }, 88 { .compat = "nvidia,tegra124-i2c" }, 89 { .compat = "nvidia,tegra114-i2c" }, 90 DEVICE_COMPAT_EOL 91 }; 92 93 static int 94 tegra_i2c_match(device_t parent, cfdata_t cf, void *aux) 95 { 96 struct fdt_attach_args * const faa = aux; 97 98 return of_compatible_match(faa->faa_phandle, compat_data); 99 } 100 101 static void 102 tegra_i2c_attach(device_t parent, device_t self, void *aux) 103 { 104 struct tegra_i2c_softc * const sc = device_private(self); 105 struct fdt_attach_args * const faa = aux; 106 const int phandle = faa->faa_phandle; 107 char intrstr[128]; 108 bus_addr_t addr; 109 bus_size_t size; 110 int error; 111 112 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 113 aprint_error(": couldn't get registers\n"); 114 return; 115 } 116 sc->sc_clk = fdtbus_clock_get(phandle, "div-clk"); 117 if (sc->sc_clk == NULL) { 118 aprint_error(": couldn't get clock div-clk\n"); 119 return; 120 } 121 sc->sc_rst = fdtbus_reset_get(phandle, "i2c"); 122 if (sc->sc_rst == NULL) { 123 aprint_error(": couldn't get reset i2c\n"); 124 return; 125 } 126 127 sc->sc_dev = self; 128 sc->sc_bst = faa->faa_bst; 129 sc->sc_cid = device_unit(self); 130 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 131 if (error) { 132 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", 133 addr, error); 134 return; 135 } 136 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_VM); 137 cv_init(&sc->sc_intr_wait, device_xname(self)); 138 139 aprint_naive("\n"); 140 aprint_normal(": I2C\n"); 141 142 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 143 aprint_error_dev(self, "failed to decode interrupt\n"); 144 return; 145 } 146 147 sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_VM, 148 FDT_INTR_MPSAFE, tegra_i2c_intr, sc, device_xname(self)); 149 if (sc->sc_ih == NULL) { 150 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 151 intrstr); 152 return; 153 } 154 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 155 156 /* 157 * Recommended setting for standard mode is to use an I2C source div 158 * of 20 (Tegra K1 Technical Reference Manual, Table 137) 159 */ 160 fdtbus_reset_assert(sc->sc_rst); 161 error = clk_set_rate(sc->sc_clk, 20400000); 162 if (error) { 163 aprint_error_dev(self, "couldn't set frequency: %d\n", error); 164 return; 165 } 166 error = clk_enable(sc->sc_clk); 167 if (error) { 168 aprint_error_dev(self, "couldn't enable clock: %d\n", error); 169 return; 170 } 171 fdtbus_reset_deassert(sc->sc_rst); 172 173 mutex_enter(&sc->sc_intr_lock); 174 tegra_i2c_init(sc); 175 mutex_exit(&sc->sc_intr_lock); 176 177 iic_tag_init(&sc->sc_ic); 178 sc->sc_ic.ic_cookie = sc; 179 sc->sc_ic.ic_exec = tegra_i2c_exec; 180 181 iicbus_attach(self, &sc->sc_ic); 182 } 183 184 static void 185 tegra_i2c_init(struct tegra_i2c_softc *sc) 186 { 187 int retry = 10000; 188 189 I2C_WRITE(sc, I2C_CLK_DIVISOR_REG, 190 __SHIFTIN(0x19, I2C_CLK_DIVISOR_STD_FAST_MODE) | 191 __SHIFTIN(0x1, I2C_CLK_DIVISOR_HSMODE)); 192 193 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 0); 194 I2C_WRITE(sc, I2C_CNFG_REG, 195 I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN); 196 I2C_SET_CLEAR(sc, I2C_SL_CNFG_REG, I2C_SL_CNFG_NEWSL, 0); 197 I2C_WRITE(sc, I2C_FIFO_CONTROL_REG, 198 __SHIFTIN(7, I2C_FIFO_CONTROL_TX_FIFO_TRIG) | 199 __SHIFTIN(0, I2C_FIFO_CONTROL_RX_FIFO_TRIG)); 200 201 I2C_WRITE(sc, I2C_BUS_CONFIG_LOAD_REG, 202 I2C_BUS_CONFIG_LOAD_MSTR_CONFIG_LOAD); 203 while (--retry > 0) { 204 if (I2C_READ(sc, I2C_BUS_CONFIG_LOAD_REG) == 0) 205 break; 206 delay(10); 207 } 208 if (retry == 0) { 209 device_printf(sc->sc_dev, "config load timeout\n"); 210 } 211 } 212 213 static int 214 tegra_i2c_intr(void *priv) 215 { 216 struct tegra_i2c_softc * const sc = priv; 217 218 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 219 if (istatus == 0) 220 return 0; 221 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 222 223 mutex_enter(&sc->sc_intr_lock); 224 cv_broadcast(&sc->sc_intr_wait); 225 mutex_exit(&sc->sc_intr_lock); 226 227 return 1; 228 } 229 230 static int 231 tegra_i2c_exec(void *priv, i2c_op_t op, i2c_addr_t addr, const void *cmdbuf, 232 size_t cmdlen, void *buf, size_t buflen, int flags) 233 { 234 struct tegra_i2c_softc * const sc = priv; 235 int retry, error; 236 237 /* 238 * XXXJRT This is probably no longer necessary? Before these 239 * changes, the bus lock was also used for the interrupt handler, 240 * and there would be a deadlock when the interrupt handler tried to 241 * acquire it again. The bus lock is now owned by the mid-layer and 242 * we have our own interrupt lock. 243 */ 244 flags |= I2C_F_POLL; 245 246 if (buflen == 0 && cmdlen == 0) 247 return EINVAL; 248 249 mutex_enter(&sc->sc_intr_lock); 250 251 if ((flags & I2C_F_POLL) == 0) { 252 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 253 I2C_INTERRUPT_MASK_NOACK | I2C_INTERRUPT_MASK_ARB_LOST | 254 I2C_INTERRUPT_MASK_TIMEOUT | 255 I2C_INTERRUPT_MASK_ALL_PACKETS_XFER_COMPLETE); 256 } 257 258 const uint32_t flush_mask = 259 I2C_FIFO_CONTROL_TX_FIFO_FLUSH | I2C_FIFO_CONTROL_RX_FIFO_FLUSH; 260 261 I2C_SET_CLEAR(sc, I2C_FIFO_CONTROL_REG, flush_mask, 0); 262 for (retry = 10000; retry > 0; retry--) { 263 const uint32_t v = I2C_READ(sc, I2C_FIFO_CONTROL_REG); 264 if ((v & flush_mask) == 0) 265 break; 266 delay(1); 267 } 268 if (retry == 0) { 269 mutex_exit(&sc->sc_intr_lock); 270 device_printf(sc->sc_dev, "timeout flushing FIFO\n"); 271 return EIO; 272 } 273 274 if (cmdlen > 0) { 275 error = tegra_i2c_write(sc, addr, cmdbuf, cmdlen, flags, 276 buflen > 0 ? true : false); 277 if (error) { 278 goto done; 279 } 280 } 281 282 if (buflen > 0) { 283 if (I2C_OP_READ_P(op)) { 284 error = tegra_i2c_read(sc, addr, buf, buflen, flags); 285 } else { 286 error = tegra_i2c_write(sc, addr, buf, buflen, flags, false); 287 } 288 } 289 290 done: 291 if ((flags & I2C_F_POLL) == 0) { 292 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 0); 293 } 294 295 if (error) { 296 tegra_i2c_init(sc); 297 } 298 299 mutex_exit(&sc->sc_intr_lock); 300 301 return error; 302 } 303 304 static int 305 tegra_i2c_wait(struct tegra_i2c_softc *sc, int flags) 306 { 307 int error, retry; 308 uint32_t stat = 0; 309 310 retry = (flags & I2C_F_POLL) ? 100000 : 100; 311 312 while (--retry > 0) { 313 if ((flags & I2C_F_POLL) == 0) { 314 error = cv_timedwait_sig(&sc->sc_intr_wait, 315 &sc->sc_intr_lock, 316 uimax(mstohz(10), 1)); 317 if (error) { 318 return error; 319 } 320 } 321 stat = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 322 if (stat & I2C_INTERRUPT_STATUS_PACKET_XFER_COMPLETE) { 323 break; 324 } 325 if (flags & I2C_F_POLL) { 326 delay(10); 327 } 328 } 329 if (retry == 0) { 330 #ifdef TEGRA_I2C_DEBUG 331 device_printf(sc->sc_dev, "timed out, status = %#x\n", stat); 332 #endif 333 return ETIMEDOUT; 334 } 335 336 const uint32_t err_mask = 337 I2C_INTERRUPT_STATUS_NOACK | 338 I2C_INTERRUPT_STATUS_ARB_LOST | 339 I2C_INTERRUPT_MASK_TIMEOUT; 340 341 if (stat & err_mask) { 342 device_printf(sc->sc_dev, "error, status = %#x\n", stat); 343 return EIO; 344 } 345 346 return 0; 347 } 348 349 static int 350 tegra_i2c_write(struct tegra_i2c_softc *sc, i2c_addr_t addr, const uint8_t *buf, 351 size_t buflen, int flags, bool repeat_start) 352 { 353 const uint8_t *p = buf; 354 size_t n, resid = buflen; 355 uint32_t data; 356 int retry; 357 358 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 359 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 360 361 /* Generic Header 0 */ 362 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 363 __SHIFTIN(I2C_IOPACKET_WORD0_PROTHDRSZ_REQ, 364 I2C_IOPACKET_WORD0_PROTHDRSZ) | 365 __SHIFTIN(sc->sc_cid, I2C_IOPACKET_WORD0_CONTROLLERID) | 366 __SHIFTIN(1, I2C_IOPACKET_WORD0_PKTID) | 367 __SHIFTIN(I2C_IOPACKET_WORD0_PROTOCOL_I2C, 368 I2C_IOPACKET_WORD0_PROTOCOL) | 369 __SHIFTIN(I2C_IOPACKET_WORD0_PKTTYPE_REQ, 370 I2C_IOPACKET_WORD0_PKTTYPE)); 371 /* Generic Header 1 */ 372 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 373 __SHIFTIN(buflen - 1, I2C_IOPACKET_WORD1_PAYLOADSIZE)); 374 /* I2C Master Transmit Packet Header */ 375 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 376 I2C_IOPACKET_XMITHDR_IE | 377 (repeat_start ? I2C_IOPACKET_XMITHDR_REPEAT_STARTSTOP : 0) | 378 __SHIFTIN((addr << 1), I2C_IOPACKET_XMITHDR_SLAVE_ADDR)); 379 380 /* Transmit data */ 381 while (resid > 0) { 382 retry = 10000; 383 while (--retry > 0) { 384 const uint32_t fs = I2C_READ(sc, I2C_FIFO_STATUS_REG); 385 const u_int cnt = 386 __SHIFTOUT(fs, I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT); 387 if (cnt > 0) 388 break; 389 delay(10); 390 } 391 if (retry == 0) { 392 device_printf(sc->sc_dev, "TX FIFO timeout\n"); 393 return ETIMEDOUT; 394 } 395 396 for (n = 0, data = 0; n < uimin(resid, 4); n++) { 397 data |= (uint32_t)p[n] << (n * 8); 398 } 399 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, data); 400 p += uimin(resid, 4); 401 resid -= uimin(resid, 4); 402 } 403 404 return tegra_i2c_wait(sc, flags); 405 } 406 407 static int 408 tegra_i2c_read(struct tegra_i2c_softc *sc, i2c_addr_t addr, uint8_t *buf, 409 size_t buflen, int flags) 410 { 411 uint8_t *p = buf; 412 size_t n, resid = buflen; 413 uint32_t data; 414 int retry; 415 416 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 417 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 418 419 /* Generic Header 0 */ 420 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 421 __SHIFTIN(I2C_IOPACKET_WORD0_PROTHDRSZ_REQ, 422 I2C_IOPACKET_WORD0_PROTHDRSZ) | 423 __SHIFTIN(sc->sc_cid, I2C_IOPACKET_WORD0_CONTROLLERID) | 424 __SHIFTIN(1, I2C_IOPACKET_WORD0_PKTID) | 425 __SHIFTIN(I2C_IOPACKET_WORD0_PROTOCOL_I2C, 426 I2C_IOPACKET_WORD0_PROTOCOL) | 427 __SHIFTIN(I2C_IOPACKET_WORD0_PKTTYPE_REQ, 428 I2C_IOPACKET_WORD0_PKTTYPE)); 429 /* Generic Header 1 */ 430 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 431 __SHIFTIN(buflen - 1, I2C_IOPACKET_WORD1_PAYLOADSIZE)); 432 /* I2C Master Transmit Packet Header */ 433 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 434 I2C_IOPACKET_XMITHDR_IE | I2C_IOPACKET_XMITHDR_READ | 435 __SHIFTIN((addr << 1) | 1, I2C_IOPACKET_XMITHDR_SLAVE_ADDR)); 436 437 while (resid > 0) { 438 retry = 10000; 439 while (--retry > 0) { 440 const uint32_t fs = I2C_READ(sc, I2C_FIFO_STATUS_REG); 441 const u_int cnt = 442 __SHIFTOUT(fs, I2C_FIFO_STATUS_RX_FIFO_FULL_CNT); 443 if (cnt > 0) 444 break; 445 delay(10); 446 } 447 if (retry == 0) { 448 device_printf(sc->sc_dev, "RX FIFO timeout\n"); 449 return ETIMEDOUT; 450 } 451 452 data = I2C_READ(sc, I2C_RX_FIFO_REG); 453 for (n = 0; n < uimin(resid, 4); n++) { 454 p[n] = (data >> (n * 8)) & 0xff; 455 } 456 p += uimin(resid, 4); 457 resid -= uimin(resid, 4); 458 } 459 460 return tegra_i2c_wait(sc, flags); 461 } 462
Indexes created Thu Oct 02 07:10:07 GMT 2025