tegra_i2c.c revision 1.3
1 /* $NetBSD: tegra_i2c.c,v 1.3 2015/05/16 23:09:08 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "locators.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: tegra_i2c.c,v 1.3 2015/05/16 23:09:08 jmcneill Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 41 #include <dev/i2c/i2cvar.h> 42 43 #include <arm/nvidia/tegra_reg.h> 44 #include <arm/nvidia/tegra_i2creg.h> 45 #include <arm/nvidia/tegra_var.h> 46 47 static int tegra_i2c_match(device_t, cfdata_t, void *); 48 static void tegra_i2c_attach(device_t, device_t, void *); 49 50 struct tegra_i2c_softc { 51 device_t sc_dev; 52 bus_space_tag_t sc_bst; 53 bus_space_handle_t sc_bsh; 54 void * sc_ih; 55 u_int sc_port; 56 57 struct i2c_controller sc_ic; 58 kmutex_t sc_lock; 59 kcondvar_t sc_cv; 60 device_t sc_i2cdev; 61 }; 62 63 static void tegra_i2c_init(struct tegra_i2c_softc *); 64 static int tegra_i2c_intr(void *); 65 66 static int tegra_i2c_acquire_bus(void *, int); 67 static void tegra_i2c_release_bus(void *, int); 68 static int tegra_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 69 size_t, void *, size_t, int); 70 71 static int tegra_i2c_wait(struct tegra_i2c_softc *, int); 72 static int tegra_i2c_write(struct tegra_i2c_softc *, i2c_addr_t, 73 const uint8_t *, size_t, int); 74 static int tegra_i2c_read(struct tegra_i2c_softc *, i2c_addr_t, uint8_t *, 75 size_t, int); 76 77 CFATTACH_DECL_NEW(tegra_i2c, sizeof(struct tegra_i2c_softc), 78 tegra_i2c_match, tegra_i2c_attach, NULL, NULL); 79 80 #define I2C_WRITE(sc, reg, val) \ 81 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 82 #define I2C_READ(sc, reg) \ 83 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 84 #define I2C_SET_CLEAR(sc, reg, setval, clrval) \ 85 tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (setval), (clrval)) 86 87 static int 88 tegra_i2c_match(device_t parent, cfdata_t cf, void *aux) 89 { 90 struct tegraio_attach_args * const tio = aux; 91 const struct tegra_locators * const loc = &tio->tio_loc; 92 93 if (loc->loc_port == TEGRAIOCF_PORT_DEFAULT) 94 return 0; 95 96 return 1; 97 } 98 99 static void 100 tegra_i2c_attach(device_t parent, device_t self, void *aux) 101 { 102 struct tegra_i2c_softc * const sc = device_private(self); 103 struct tegraio_attach_args * const tio = aux; 104 const struct tegra_locators * const loc = &tio->tio_loc; 105 struct i2cbus_attach_args iba; 106 107 sc->sc_dev = self; 108 sc->sc_bst = tio->tio_bst; 109 bus_space_subregion(tio->tio_bst, tio->tio_bsh, 110 loc->loc_offset, loc->loc_size, &sc->sc_bsh); 111 sc->sc_port = loc->loc_port; 112 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 113 cv_init(&sc->sc_cv, device_xname(self)); 114 115 aprint_naive("\n"); 116 aprint_normal(": I2C%d\n", loc->loc_port + 1); 117 118 sc->sc_ih = intr_establish(loc->loc_intr, IPL_VM, IST_LEVEL|IST_MPSAFE, 119 tegra_i2c_intr, sc); 120 if (sc->sc_ih == NULL) { 121 aprint_error_dev(self, "couldn't establish interrupt %d\n", 122 loc->loc_intr); 123 return; 124 } 125 aprint_normal_dev(self, "interrupting on irq %d\n", loc->loc_intr); 126 127 /* Recommended setting for standard mode */ 128 tegra_car_periph_i2c_enable(loc->loc_port, 20400000); 129 130 tegra_i2c_init(sc); 131 132 sc->sc_ic.ic_cookie = sc; 133 sc->sc_ic.ic_acquire_bus = tegra_i2c_acquire_bus; 134 sc->sc_ic.ic_release_bus = tegra_i2c_release_bus; 135 sc->sc_ic.ic_exec = tegra_i2c_exec; 136 137 iba.iba_tag = &sc->sc_ic; 138 sc->sc_i2cdev = config_found_ia(self, "i2cbus", &iba, iicbus_print); 139 } 140 141 static void 142 tegra_i2c_init(struct tegra_i2c_softc *sc) 143 { 144 I2C_WRITE(sc, I2C_CLK_DIVISOR_REG, 145 __SHIFTIN(0x19, I2C_CLK_DIVISOR_STD_FAST_MODE) | 146 __SHIFTIN(0x1, I2C_CLK_DIVISOR_HSMODE)); 147 148 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 0); 149 I2C_WRITE(sc, I2C_CNFG_REG, 150 I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN); 151 I2C_SET_CLEAR(sc, I2C_SL_CNFG_REG, I2C_SL_CNFG_NEWSL, 0); 152 I2C_WRITE(sc, I2C_BUS_CONFIG_LOAD_REG, 153 I2C_BUS_CONFIG_LOAD_MSTR_CONFIG_LOAD); 154 } 155 156 static int 157 tegra_i2c_intr(void *priv) 158 { 159 struct tegra_i2c_softc * const sc = priv; 160 161 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 162 if (istatus == 0) 163 return 0; 164 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 165 166 mutex_enter(&sc->sc_lock); 167 cv_broadcast(&sc->sc_cv); 168 mutex_exit(&sc->sc_lock); 169 170 return 1; 171 } 172 173 static int 174 tegra_i2c_acquire_bus(void *priv, int flags) 175 { 176 struct tegra_i2c_softc * const sc = priv; 177 178 mutex_enter(&sc->sc_lock); 179 180 return 0; 181 } 182 183 static void 184 tegra_i2c_release_bus(void *priv, int flags) 185 { 186 struct tegra_i2c_softc * const sc = priv; 187 188 mutex_exit(&sc->sc_lock); 189 } 190 191 static int 192 tegra_i2c_exec(void *priv, i2c_op_t op, i2c_addr_t addr, const void *cmdbuf, 193 size_t cmdlen, void *buf, size_t buflen, int flags) 194 { 195 struct tegra_i2c_softc * const sc = priv; 196 int retry, error; 197 198 #if notyet 199 if (cold) 200 #endif 201 flags |= I2C_F_POLL; 202 203 KASSERT(mutex_owned(&sc->sc_lock)); 204 205 if ((flags & I2C_F_POLL) == 0) { 206 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 207 I2C_INTERRUPT_MASK_NOACK | I2C_INTERRUPT_MASK_ARB_LOST | 208 I2C_INTERRUPT_MASK_TIMEOUT | 209 I2C_INTERRUPT_MASK_ALL_PACKETS_XFER_COMPLETE); 210 } 211 212 const uint32_t flush_mask = 213 I2C_FIFO_CONTROL_TX_FIFO_FLUSH | I2C_FIFO_CONTROL_RX_FIFO_FLUSH; 214 215 I2C_SET_CLEAR(sc, I2C_FIFO_CONTROL_REG, flush_mask, 0); 216 for (retry = 10000; retry > 0; retry--) { 217 const uint32_t v = I2C_READ(sc, I2C_FIFO_CONTROL_REG); 218 if ((v & flush_mask) == 0) 219 break; 220 delay(1); 221 } 222 if (retry == 0) { 223 device_printf(sc->sc_dev, "timeout flushing FIFO\n"); 224 return EIO; 225 } 226 227 if (cmdlen > 0) { 228 error = tegra_i2c_write(sc, addr, cmdbuf, cmdlen, flags); 229 if (error) { 230 goto done; 231 } 232 } 233 234 if (I2C_OP_READ_P(op)) { 235 error = tegra_i2c_read(sc, addr, buf, buflen, flags); 236 } else { 237 error = tegra_i2c_write(sc, addr, buf, buflen, flags); 238 } 239 240 done: 241 if ((flags & I2C_F_POLL) == 0) { 242 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 0); 243 } 244 245 if (error) { 246 tegra_i2c_init(sc); 247 } 248 249 return error; 250 } 251 252 static int 253 tegra_i2c_wait(struct tegra_i2c_softc *sc, int flags) 254 { 255 int error, retry; 256 uint32_t stat = 0; 257 258 retry = (flags & I2C_F_POLL) ? 100000 : 100; 259 260 while (--retry > 0) { 261 if ((flags & I2C_F_POLL) == 0) { 262 error = cv_timedwait_sig(&sc->sc_cv, &sc->sc_lock, 263 max(mstohz(10), 1)); 264 if (error) { 265 return error; 266 } 267 } 268 stat = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 269 if (stat & I2C_INTERRUPT_STATUS_PACKET_XFER_COMPLETE) { 270 break; 271 } 272 if (flags & I2C_F_POLL) { 273 delay(10); 274 } 275 } 276 if (retry == 0) { 277 stat = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 278 device_printf(sc->sc_dev, "timed out, status = %#x\n", stat); 279 return ETIMEDOUT; 280 } 281 282 const uint32_t err_mask = 283 I2C_INTERRUPT_STATUS_NOACK | 284 I2C_INTERRUPT_STATUS_ARB_LOST | 285 I2C_INTERRUPT_MASK_TIMEOUT; 286 287 if (stat & err_mask) { 288 device_printf(sc->sc_dev, "error, status = %#x\n", stat); 289 return EIO; 290 } 291 292 return 0; 293 } 294 295 static int 296 tegra_i2c_write(struct tegra_i2c_softc *sc, i2c_addr_t addr, const uint8_t *buf, 297 size_t buflen, int flags) 298 { 299 const uint8_t *p = buf; 300 size_t n, resid = buflen; 301 uint32_t data; 302 int retry; 303 304 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 305 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 306 307 /* Generic Header 0 */ 308 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 309 __SHIFTIN(I2C_IOPACKET_WORD0_PROTHDRSZ_REQ, 310 I2C_IOPACKET_WORD0_PROTHDRSZ) | 311 __SHIFTIN(sc->sc_port, I2C_IOPACKET_WORD0_CONTROLLERID) | 312 __SHIFTIN(1, I2C_IOPACKET_WORD0_PKTID) | 313 __SHIFTIN(I2C_IOPACKET_WORD0_PROTOCOL_I2C, 314 I2C_IOPACKET_WORD0_PROTOCOL) | 315 __SHIFTIN(I2C_IOPACKET_WORD0_PKTTYPE_REQ, 316 I2C_IOPACKET_WORD0_PKTTYPE)); 317 /* Generic Header 1 */ 318 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 319 __SHIFTIN(buflen - 1, I2C_IOPACKET_WORD1_PAYLOADSIZE)); 320 /* I2C Master Transmit Packet Header */ 321 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 322 I2C_IOPACKET_XMITHDR_IE | 323 __SHIFTIN((addr << 1), I2C_IOPACKET_XMITHDR_SLAVE_ADDR)); 324 325 /* Transmit data */ 326 while (resid > 0) { 327 retry = 10000; 328 while (--retry > 0) { 329 const uint32_t fs = I2C_READ(sc, I2C_FIFO_STATUS_REG); 330 const u_int cnt = 331 __SHIFTOUT(fs, I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT); 332 if (cnt > 0) 333 break; 334 delay(10); 335 } 336 if (retry == 0) { 337 device_printf(sc->sc_dev, "TX FIFO timeout\n"); 338 return ETIMEDOUT; 339 } 340 341 for (n = 0, data = 0; n < min(resid, 4); n++) { 342 data |= (uint32_t)p[n] << (n * 8); 343 } 344 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, data); 345 resid -= min(resid, 4); 346 p += min(resid, 4); 347 } 348 349 return tegra_i2c_wait(sc, flags); 350 } 351 352 static int 353 tegra_i2c_read(struct tegra_i2c_softc *sc, i2c_addr_t addr, uint8_t *buf, 354 size_t buflen, int flags) 355 { 356 uint8_t *p = buf; 357 size_t n, resid = buflen; 358 uint32_t data; 359 int retry; 360 361 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 362 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 363 364 /* Generic Header 0 */ 365 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 366 __SHIFTIN(I2C_IOPACKET_WORD0_PROTHDRSZ_REQ, 367 I2C_IOPACKET_WORD0_PROTHDRSZ) | 368 __SHIFTIN(sc->sc_port, I2C_IOPACKET_WORD0_CONTROLLERID) | 369 __SHIFTIN(1, I2C_IOPACKET_WORD0_PKTID) | 370 __SHIFTIN(I2C_IOPACKET_WORD0_PROTOCOL_I2C, 371 I2C_IOPACKET_WORD0_PROTOCOL) | 372 __SHIFTIN(I2C_IOPACKET_WORD0_PKTTYPE_REQ, 373 I2C_IOPACKET_WORD0_PKTTYPE)); 374 /* Generic Header 1 */ 375 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 376 __SHIFTIN(buflen - 1, I2C_IOPACKET_WORD1_PAYLOADSIZE)); 377 /* I2C Master Transmit Packet Header */ 378 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 379 I2C_IOPACKET_XMITHDR_IE | I2C_IOPACKET_XMITHDR_READ | 380 __SHIFTIN((addr << 1) | 1, I2C_IOPACKET_XMITHDR_SLAVE_ADDR)); 381 382 while (resid > 0) { 383 retry = 10000; 384 while (--retry > 0) { 385 const uint32_t fs = I2C_READ(sc, I2C_FIFO_STATUS_REG); 386 const u_int cnt = 387 __SHIFTOUT(fs, I2C_FIFO_STATUS_RX_FIFO_FULL_CNT); 388 if (cnt > 0) 389 break; 390 delay(10); 391 } 392 if (retry == 0) { 393 device_printf(sc->sc_dev, "RX FIFO timeout\n"); 394 return ETIMEDOUT; 395 } 396 397 data = I2C_READ(sc, I2C_RX_FIFO_REG); 398 for (n = 0; n < min(resid, 4); n++) { 399 p[n] = (data >> (n * 8)) & 0xff; 400 } 401 resid -= min(resid, 4); 402 p += min(resid, 4); 403 } 404 405 return tegra_i2c_wait(sc, flags); 406 } 407
Indexes created Thu Oct 02 01:09:59 GMT 2025