tegra_i2c.c revision 1.5.2.5
1 /* $NetBSD: tegra_i2c.c,v 1.5.2.5 2016/10/05 20:55:25 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_i2c.c,v 1.5.2.5 2016/10/05 20:55:25 skrll Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 39 #include <dev/i2c/i2cvar.h> 40 41 #include <arm/nvidia/tegra_reg.h> 42 #include <arm/nvidia/tegra_i2creg.h> 43 #include <arm/nvidia/tegra_var.h> 44 45 #include <dev/fdt/fdtvar.h> 46 47 static int tegra_i2c_match(device_t, cfdata_t, void *); 48 static void tegra_i2c_attach(device_t, device_t, void *); 49 50 static i2c_tag_t tegra_i2c_get_tag(device_t); 51 52 struct fdtbus_i2c_controller_func tegra_i2c_funcs = { 53 .get_tag = tegra_i2c_get_tag 54 }; 55 56 struct tegra_i2c_softc { 57 device_t sc_dev; 58 bus_space_tag_t sc_bst; 59 bus_space_handle_t sc_bsh; 60 void * sc_ih; 61 struct clk * sc_clk; 62 struct fdtbus_reset * sc_rst; 63 u_int sc_cid; 64 65 struct i2c_controller sc_ic; 66 kmutex_t sc_lock; 67 kcondvar_t sc_cv; 68 device_t sc_i2cdev; 69 }; 70 71 static void tegra_i2c_init(struct tegra_i2c_softc *); 72 static int tegra_i2c_intr(void *); 73 74 static int tegra_i2c_acquire_bus(void *, int); 75 static void tegra_i2c_release_bus(void *, int); 76 static int tegra_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 77 size_t, void *, size_t, int); 78 79 static int tegra_i2c_wait(struct tegra_i2c_softc *, int); 80 static int tegra_i2c_write(struct tegra_i2c_softc *, i2c_addr_t, 81 const uint8_t *, size_t, int, bool); 82 static int tegra_i2c_read(struct tegra_i2c_softc *, i2c_addr_t, uint8_t *, 83 size_t, int); 84 85 CFATTACH_DECL_NEW(tegra_i2c, sizeof(struct tegra_i2c_softc), 86 tegra_i2c_match, tegra_i2c_attach, NULL, NULL); 87 88 #define I2C_WRITE(sc, reg, val) \ 89 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 90 #define I2C_READ(sc, reg) \ 91 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 92 #define I2C_SET_CLEAR(sc, reg, setval, clrval) \ 93 tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (setval), (clrval)) 94 95 static int 96 tegra_i2c_match(device_t parent, cfdata_t cf, void *aux) 97 { 98 const char * const compatible[] = { "nvidia,tegra124-i2c", NULL }; 99 struct fdt_attach_args * const faa = aux; 100 101 return of_match_compatible(faa->faa_phandle, compatible); 102 } 103 104 static void 105 tegra_i2c_attach(device_t parent, device_t self, void *aux) 106 { 107 struct tegra_i2c_softc * const sc = device_private(self); 108 struct fdt_attach_args * const faa = aux; 109 const int phandle = faa->faa_phandle; 110 struct i2cbus_attach_args iba; 111 prop_dictionary_t devs; 112 char intrstr[128]; 113 bus_addr_t addr; 114 bus_size_t size; 115 u_int address_cells; 116 int error; 117 118 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 119 aprint_error(": couldn't get registers\n"); 120 return; 121 } 122 sc->sc_clk = fdtbus_clock_get(phandle, "div-clk"); 123 if (sc->sc_clk == NULL) { 124 aprint_error(": couldn't get clock div-clk\n"); 125 return; 126 } 127 sc->sc_rst = fdtbus_reset_get(phandle, "i2c"); 128 if (sc->sc_rst == NULL) { 129 aprint_error(": couldn't get reset i2c\n"); 130 return; 131 } 132 133 sc->sc_dev = self; 134 sc->sc_bst = faa->faa_bst; 135 sc->sc_cid = device_unit(self); 136 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 137 if (error) { 138 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 139 return; 140 } 141 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 142 cv_init(&sc->sc_cv, device_xname(self)); 143 144 aprint_naive("\n"); 145 aprint_normal(": I2C\n"); 146 147 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 148 aprint_error_dev(self, "failed to decode interrupt\n"); 149 return; 150 } 151 152 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_VM, 153 FDT_INTR_MPSAFE, tegra_i2c_intr, sc); 154 if (sc->sc_ih == NULL) { 155 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 156 intrstr); 157 return; 158 } 159 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 160 161 /* 162 * Recommended setting for standard mode is to use an I2C source div 163 * of 20 (Tegra K1 Technical Reference Manual, Table 137) 164 */ 165 fdtbus_reset_assert(sc->sc_rst); 166 error = clk_set_rate(sc->sc_clk, 20400000); 167 if (error) { 168 aprint_error_dev(self, "couldn't set frequency: %d\n", error); 169 return; 170 } 171 error = clk_enable(sc->sc_clk); 172 if (error) { 173 aprint_error_dev(self, "couldn't enable clock: %d\n", error); 174 return; 175 } 176 fdtbus_reset_deassert(sc->sc_rst); 177 178 tegra_i2c_init(sc); 179 180 sc->sc_ic.ic_cookie = sc; 181 sc->sc_ic.ic_acquire_bus = tegra_i2c_acquire_bus; 182 sc->sc_ic.ic_release_bus = tegra_i2c_release_bus; 183 sc->sc_ic.ic_exec = tegra_i2c_exec; 184 185 fdtbus_register_i2c_controller(self, phandle, &tegra_i2c_funcs); 186 187 devs = prop_dictionary_create(); 188 189 if (of_getprop_uint32(phandle, "#address-cells", &address_cells)) 190 address_cells = 1; 191 192 of_enter_i2c_devs(devs, faa->faa_phandle, address_cells * 4, 0); 193 194 memset(&iba, 0, sizeof(iba)); 195 iba.iba_tag = &sc->sc_ic; 196 iba.iba_child_devices = prop_dictionary_get(devs, "i2c-child-devices"); 197 if (iba.iba_child_devices != NULL) { 198 prop_object_retain(iba.iba_child_devices); 199 } else { 200 iba.iba_child_devices = prop_array_create(); 201 } 202 prop_object_release(devs); 203 204 sc->sc_i2cdev = config_found_ia(self, "i2cbus", &iba, iicbus_print); 205 } 206 207 static i2c_tag_t 208 tegra_i2c_get_tag(device_t dev) 209 { 210 struct tegra_i2c_softc * const sc = device_private(dev); 211 212 return &sc->sc_ic; 213 } 214 215 static void 216 tegra_i2c_init(struct tegra_i2c_softc *sc) 217 { 218 int retry = 10000; 219 220 I2C_WRITE(sc, I2C_CLK_DIVISOR_REG, 221 __SHIFTIN(0x19, I2C_CLK_DIVISOR_STD_FAST_MODE) | 222 __SHIFTIN(0x1, I2C_CLK_DIVISOR_HSMODE)); 223 224 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 0); 225 I2C_WRITE(sc, I2C_CNFG_REG, 226 I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN); 227 I2C_SET_CLEAR(sc, I2C_SL_CNFG_REG, I2C_SL_CNFG_NEWSL, 0); 228 I2C_WRITE(sc, I2C_FIFO_CONTROL_REG, 229 __SHIFTIN(7, I2C_FIFO_CONTROL_TX_FIFO_TRIG) | 230 __SHIFTIN(0, I2C_FIFO_CONTROL_RX_FIFO_TRIG)); 231 232 I2C_WRITE(sc, I2C_BUS_CONFIG_LOAD_REG, 233 I2C_BUS_CONFIG_LOAD_MSTR_CONFIG_LOAD); 234 while (--retry > 0) { 235 if (I2C_READ(sc, I2C_BUS_CONFIG_LOAD_REG) == 0) 236 break; 237 delay(10); 238 } 239 if (retry == 0) { 240 device_printf(sc->sc_dev, "config load timeout\n"); 241 } 242 } 243 244 static int 245 tegra_i2c_intr(void *priv) 246 { 247 struct tegra_i2c_softc * const sc = priv; 248 249 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 250 if (istatus == 0) 251 return 0; 252 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 253 254 mutex_enter(&sc->sc_lock); 255 cv_broadcast(&sc->sc_cv); 256 mutex_exit(&sc->sc_lock); 257 258 return 1; 259 } 260 261 static int 262 tegra_i2c_acquire_bus(void *priv, int flags) 263 { 264 struct tegra_i2c_softc * const sc = priv; 265 266 mutex_enter(&sc->sc_lock); 267 268 return 0; 269 } 270 271 static void 272 tegra_i2c_release_bus(void *priv, int flags) 273 { 274 struct tegra_i2c_softc * const sc = priv; 275 276 mutex_exit(&sc->sc_lock); 277 } 278 279 static int 280 tegra_i2c_exec(void *priv, i2c_op_t op, i2c_addr_t addr, const void *cmdbuf, 281 size_t cmdlen, void *buf, size_t buflen, int flags) 282 { 283 struct tegra_i2c_softc * const sc = priv; 284 int retry, error; 285 286 #if notyet 287 if (cold) 288 #endif 289 flags |= I2C_F_POLL; 290 291 KASSERT(mutex_owned(&sc->sc_lock)); 292 293 if ((flags & I2C_F_POLL) == 0) { 294 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 295 I2C_INTERRUPT_MASK_NOACK | I2C_INTERRUPT_MASK_ARB_LOST | 296 I2C_INTERRUPT_MASK_TIMEOUT | 297 I2C_INTERRUPT_MASK_ALL_PACKETS_XFER_COMPLETE); 298 } 299 300 const uint32_t flush_mask = 301 I2C_FIFO_CONTROL_TX_FIFO_FLUSH | I2C_FIFO_CONTROL_RX_FIFO_FLUSH; 302 303 I2C_SET_CLEAR(sc, I2C_FIFO_CONTROL_REG, flush_mask, 0); 304 for (retry = 10000; retry > 0; retry--) { 305 const uint32_t v = I2C_READ(sc, I2C_FIFO_CONTROL_REG); 306 if ((v & flush_mask) == 0) 307 break; 308 delay(1); 309 } 310 if (retry == 0) { 311 device_printf(sc->sc_dev, "timeout flushing FIFO\n"); 312 return EIO; 313 } 314 315 if (cmdlen > 0) { 316 error = tegra_i2c_write(sc, addr, cmdbuf, cmdlen, flags, 317 buflen > 0 ? true : false); 318 if (error) { 319 goto done; 320 } 321 } 322 323 if (I2C_OP_READ_P(op)) { 324 error = tegra_i2c_read(sc, addr, buf, buflen, flags); 325 } else { 326 error = tegra_i2c_write(sc, addr, buf, buflen, flags, false); 327 } 328 329 done: 330 if ((flags & I2C_F_POLL) == 0) { 331 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 0); 332 } 333 334 if (error) { 335 tegra_i2c_init(sc); 336 } 337 338 return error; 339 } 340 341 static int 342 tegra_i2c_wait(struct tegra_i2c_softc *sc, int flags) 343 { 344 int error, retry; 345 uint32_t stat = 0; 346 347 retry = (flags & I2C_F_POLL) ? 100000 : 100; 348 349 while (--retry > 0) { 350 if ((flags & I2C_F_POLL) == 0) { 351 error = cv_timedwait_sig(&sc->sc_cv, &sc->sc_lock, 352 max(mstohz(10), 1)); 353 if (error) { 354 return error; 355 } 356 } 357 stat = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 358 if (stat & I2C_INTERRUPT_STATUS_PACKET_XFER_COMPLETE) { 359 break; 360 } 361 if (flags & I2C_F_POLL) { 362 delay(10); 363 } 364 } 365 if (retry == 0) { 366 stat = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 367 device_printf(sc->sc_dev, "timed out, status = %#x\n", stat); 368 return ETIMEDOUT; 369 } 370 371 const uint32_t err_mask = 372 I2C_INTERRUPT_STATUS_NOACK | 373 I2C_INTERRUPT_STATUS_ARB_LOST | 374 I2C_INTERRUPT_MASK_TIMEOUT; 375 376 if (stat & err_mask) { 377 device_printf(sc->sc_dev, "error, status = %#x\n", stat); 378 return EIO; 379 } 380 381 return 0; 382 } 383 384 static int 385 tegra_i2c_write(struct tegra_i2c_softc *sc, i2c_addr_t addr, const uint8_t *buf, 386 size_t buflen, int flags, bool repeat_start) 387 { 388 const uint8_t *p = buf; 389 size_t n, resid = buflen; 390 uint32_t data; 391 int retry; 392 393 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 394 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 395 396 /* Generic Header 0 */ 397 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 398 __SHIFTIN(I2C_IOPACKET_WORD0_PROTHDRSZ_REQ, 399 I2C_IOPACKET_WORD0_PROTHDRSZ) | 400 __SHIFTIN(sc->sc_cid, I2C_IOPACKET_WORD0_CONTROLLERID) | 401 __SHIFTIN(1, I2C_IOPACKET_WORD0_PKTID) | 402 __SHIFTIN(I2C_IOPACKET_WORD0_PROTOCOL_I2C, 403 I2C_IOPACKET_WORD0_PROTOCOL) | 404 __SHIFTIN(I2C_IOPACKET_WORD0_PKTTYPE_REQ, 405 I2C_IOPACKET_WORD0_PKTTYPE)); 406 /* Generic Header 1 */ 407 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 408 __SHIFTIN(buflen - 1, I2C_IOPACKET_WORD1_PAYLOADSIZE)); 409 /* I2C Master Transmit Packet Header */ 410 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 411 I2C_IOPACKET_XMITHDR_IE | 412 (repeat_start ? I2C_IOPACKET_XMITHDR_REPEAT_STARTSTOP : 0) | 413 __SHIFTIN((addr << 1), I2C_IOPACKET_XMITHDR_SLAVE_ADDR)); 414 415 /* Transmit data */ 416 while (resid > 0) { 417 retry = 10000; 418 while (--retry > 0) { 419 const uint32_t fs = I2C_READ(sc, I2C_FIFO_STATUS_REG); 420 const u_int cnt = 421 __SHIFTOUT(fs, I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT); 422 if (cnt > 0) 423 break; 424 delay(10); 425 } 426 if (retry == 0) { 427 device_printf(sc->sc_dev, "TX FIFO timeout\n"); 428 return ETIMEDOUT; 429 } 430 431 for (n = 0, data = 0; n < min(resid, 4); n++) { 432 data |= (uint32_t)p[n] << (n * 8); 433 } 434 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, data); 435 p += min(resid, 4); 436 resid -= min(resid, 4); 437 } 438 439 return tegra_i2c_wait(sc, flags); 440 } 441 442 static int 443 tegra_i2c_read(struct tegra_i2c_softc *sc, i2c_addr_t addr, uint8_t *buf, 444 size_t buflen, int flags) 445 { 446 uint8_t *p = buf; 447 size_t n, resid = buflen; 448 uint32_t data; 449 int retry; 450 451 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 452 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 453 454 /* Generic Header 0 */ 455 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 456 __SHIFTIN(I2C_IOPACKET_WORD0_PROTHDRSZ_REQ, 457 I2C_IOPACKET_WORD0_PROTHDRSZ) | 458 __SHIFTIN(sc->sc_cid, I2C_IOPACKET_WORD0_CONTROLLERID) | 459 __SHIFTIN(1, I2C_IOPACKET_WORD0_PKTID) | 460 __SHIFTIN(I2C_IOPACKET_WORD0_PROTOCOL_I2C, 461 I2C_IOPACKET_WORD0_PROTOCOL) | 462 __SHIFTIN(I2C_IOPACKET_WORD0_PKTTYPE_REQ, 463 I2C_IOPACKET_WORD0_PKTTYPE)); 464 /* Generic Header 1 */ 465 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 466 __SHIFTIN(buflen - 1, I2C_IOPACKET_WORD1_PAYLOADSIZE)); 467 /* I2C Master Transmit Packet Header */ 468 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 469 I2C_IOPACKET_XMITHDR_IE | I2C_IOPACKET_XMITHDR_READ | 470 __SHIFTIN((addr << 1) | 1, I2C_IOPACKET_XMITHDR_SLAVE_ADDR)); 471 472 while (resid > 0) { 473 retry = 10000; 474 while (--retry > 0) { 475 const uint32_t fs = I2C_READ(sc, I2C_FIFO_STATUS_REG); 476 const u_int cnt = 477 __SHIFTOUT(fs, I2C_FIFO_STATUS_RX_FIFO_FULL_CNT); 478 if (cnt > 0) 479 break; 480 delay(10); 481 } 482 if (retry == 0) { 483 device_printf(sc->sc_dev, "RX FIFO timeout\n"); 484 return ETIMEDOUT; 485 } 486 487 data = I2C_READ(sc, I2C_RX_FIFO_REG); 488 for (n = 0; n < min(resid, 4); n++) { 489 p[n] = (data >> (n * 8)) & 0xff; 490 } 491 p += min(resid, 4); 492 resid -= min(resid, 4); 493 } 494 495 return tegra_i2c_wait(sc, flags); 496 } 497
Indexes created Thu Oct 02 01:09:59 GMT 2025