tegra_i2c.c revision 1.5.2.6
1 /* $NetBSD: tegra_i2c.c,v 1.5.2.6 2017/08/28 17:51:31 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_i2c.c,v 1.5.2.6 2017/08/28 17:51:31 skrll Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 39 #include <dev/i2c/i2cvar.h> 40 41 #include <arm/nvidia/tegra_reg.h> 42 #include <arm/nvidia/tegra_i2creg.h> 43 #include <arm/nvidia/tegra_var.h> 44 45 #include <dev/fdt/fdtvar.h> 46 47 static int tegra_i2c_match(device_t, cfdata_t, void *); 48 static void tegra_i2c_attach(device_t, device_t, void *); 49 50 static i2c_tag_t tegra_i2c_get_tag(device_t); 51 52 struct fdtbus_i2c_controller_func tegra_i2c_funcs = { 53 .get_tag = tegra_i2c_get_tag 54 }; 55 56 struct tegra_i2c_softc { 57 device_t sc_dev; 58 bus_space_tag_t sc_bst; 59 bus_space_handle_t sc_bsh; 60 void * sc_ih; 61 struct clk * sc_clk; 62 struct fdtbus_reset * sc_rst; 63 u_int sc_cid; 64 65 struct i2c_controller sc_ic; 66 kmutex_t sc_lock; 67 kcondvar_t sc_cv; 68 device_t sc_i2cdev; 69 }; 70 71 static void tegra_i2c_init(struct tegra_i2c_softc *); 72 static int tegra_i2c_intr(void *); 73 74 static int tegra_i2c_acquire_bus(void *, int); 75 static void tegra_i2c_release_bus(void *, int); 76 static int tegra_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 77 size_t, void *, size_t, int); 78 79 static int tegra_i2c_wait(struct tegra_i2c_softc *, int); 80 static int tegra_i2c_write(struct tegra_i2c_softc *, i2c_addr_t, 81 const uint8_t *, size_t, int, bool); 82 static int tegra_i2c_read(struct tegra_i2c_softc *, i2c_addr_t, uint8_t *, 83 size_t, int); 84 85 CFATTACH_DECL_NEW(tegra_i2c, sizeof(struct tegra_i2c_softc), 86 tegra_i2c_match, tegra_i2c_attach, NULL, NULL); 87 88 #define I2C_WRITE(sc, reg, val) \ 89 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 90 #define I2C_READ(sc, reg) \ 91 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 92 #define I2C_SET_CLEAR(sc, reg, setval, clrval) \ 93 tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (setval), (clrval)) 94 95 static int 96 tegra_i2c_match(device_t parent, cfdata_t cf, void *aux) 97 { 98 const char * const compatible[] = { 99 "nvidia,tegra210-i2c", 100 "nvidia,tegra124-i2c", 101 "nvidia,tegra114-i2c", 102 NULL 103 }; 104 struct fdt_attach_args * const faa = aux; 105 106 return of_match_compatible(faa->faa_phandle, compatible); 107 } 108 109 static void 110 tegra_i2c_attach(device_t parent, device_t self, void *aux) 111 { 112 struct tegra_i2c_softc * const sc = device_private(self); 113 struct fdt_attach_args * const faa = aux; 114 const int phandle = faa->faa_phandle; 115 struct i2cbus_attach_args iba; 116 prop_dictionary_t devs; 117 char intrstr[128]; 118 bus_addr_t addr; 119 bus_size_t size; 120 u_int address_cells; 121 int error; 122 123 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 124 aprint_error(": couldn't get registers\n"); 125 return; 126 } 127 sc->sc_clk = fdtbus_clock_get(phandle, "div-clk"); 128 if (sc->sc_clk == NULL) { 129 aprint_error(": couldn't get clock div-clk\n"); 130 return; 131 } 132 sc->sc_rst = fdtbus_reset_get(phandle, "i2c"); 133 if (sc->sc_rst == NULL) { 134 aprint_error(": couldn't get reset i2c\n"); 135 return; 136 } 137 138 sc->sc_dev = self; 139 sc->sc_bst = faa->faa_bst; 140 sc->sc_cid = device_unit(self); 141 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 142 if (error) { 143 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 144 return; 145 } 146 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 147 cv_init(&sc->sc_cv, device_xname(self)); 148 149 aprint_naive("\n"); 150 aprint_normal(": I2C\n"); 151 152 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 153 aprint_error_dev(self, "failed to decode interrupt\n"); 154 return; 155 } 156 157 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_VM, 158 FDT_INTR_MPSAFE, tegra_i2c_intr, sc); 159 if (sc->sc_ih == NULL) { 160 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 161 intrstr); 162 return; 163 } 164 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 165 166 /* 167 * Recommended setting for standard mode is to use an I2C source div 168 * of 20 (Tegra K1 Technical Reference Manual, Table 137) 169 */ 170 fdtbus_reset_assert(sc->sc_rst); 171 error = clk_set_rate(sc->sc_clk, 20400000); 172 if (error) { 173 aprint_error_dev(self, "couldn't set frequency: %d\n", error); 174 return; 175 } 176 error = clk_enable(sc->sc_clk); 177 if (error) { 178 aprint_error_dev(self, "couldn't enable clock: %d\n", error); 179 return; 180 } 181 fdtbus_reset_deassert(sc->sc_rst); 182 183 tegra_i2c_init(sc); 184 185 sc->sc_ic.ic_cookie = sc; 186 sc->sc_ic.ic_acquire_bus = tegra_i2c_acquire_bus; 187 sc->sc_ic.ic_release_bus = tegra_i2c_release_bus; 188 sc->sc_ic.ic_exec = tegra_i2c_exec; 189 190 fdtbus_register_i2c_controller(self, phandle, &tegra_i2c_funcs); 191 192 devs = prop_dictionary_create(); 193 194 if (of_getprop_uint32(phandle, "#address-cells", &address_cells)) 195 address_cells = 1; 196 197 of_enter_i2c_devs(devs, faa->faa_phandle, address_cells * 4, 0); 198 199 memset(&iba, 0, sizeof(iba)); 200 iba.iba_tag = &sc->sc_ic; 201 iba.iba_child_devices = prop_dictionary_get(devs, "i2c-child-devices"); 202 if (iba.iba_child_devices != NULL) { 203 prop_object_retain(iba.iba_child_devices); 204 } else { 205 iba.iba_child_devices = prop_array_create(); 206 } 207 prop_object_release(devs); 208 209 sc->sc_i2cdev = config_found_ia(self, "i2cbus", &iba, iicbus_print); 210 } 211 212 static i2c_tag_t 213 tegra_i2c_get_tag(device_t dev) 214 { 215 struct tegra_i2c_softc * const sc = device_private(dev); 216 217 return &sc->sc_ic; 218 } 219 220 static void 221 tegra_i2c_init(struct tegra_i2c_softc *sc) 222 { 223 int retry = 10000; 224 225 I2C_WRITE(sc, I2C_CLK_DIVISOR_REG, 226 __SHIFTIN(0x19, I2C_CLK_DIVISOR_STD_FAST_MODE) | 227 __SHIFTIN(0x1, I2C_CLK_DIVISOR_HSMODE)); 228 229 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 0); 230 I2C_WRITE(sc, I2C_CNFG_REG, 231 I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN); 232 I2C_SET_CLEAR(sc, I2C_SL_CNFG_REG, I2C_SL_CNFG_NEWSL, 0); 233 I2C_WRITE(sc, I2C_FIFO_CONTROL_REG, 234 __SHIFTIN(7, I2C_FIFO_CONTROL_TX_FIFO_TRIG) | 235 __SHIFTIN(0, I2C_FIFO_CONTROL_RX_FIFO_TRIG)); 236 237 I2C_WRITE(sc, I2C_BUS_CONFIG_LOAD_REG, 238 I2C_BUS_CONFIG_LOAD_MSTR_CONFIG_LOAD); 239 while (--retry > 0) { 240 if (I2C_READ(sc, I2C_BUS_CONFIG_LOAD_REG) == 0) 241 break; 242 delay(10); 243 } 244 if (retry == 0) { 245 device_printf(sc->sc_dev, "config load timeout\n"); 246 } 247 } 248 249 static int 250 tegra_i2c_intr(void *priv) 251 { 252 struct tegra_i2c_softc * const sc = priv; 253 254 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 255 if (istatus == 0) 256 return 0; 257 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 258 259 mutex_enter(&sc->sc_lock); 260 cv_broadcast(&sc->sc_cv); 261 mutex_exit(&sc->sc_lock); 262 263 return 1; 264 } 265 266 static int 267 tegra_i2c_acquire_bus(void *priv, int flags) 268 { 269 struct tegra_i2c_softc * const sc = priv; 270 271 mutex_enter(&sc->sc_lock); 272 273 return 0; 274 } 275 276 static void 277 tegra_i2c_release_bus(void *priv, int flags) 278 { 279 struct tegra_i2c_softc * const sc = priv; 280 281 mutex_exit(&sc->sc_lock); 282 } 283 284 static int 285 tegra_i2c_exec(void *priv, i2c_op_t op, i2c_addr_t addr, const void *cmdbuf, 286 size_t cmdlen, void *buf, size_t buflen, int flags) 287 { 288 struct tegra_i2c_softc * const sc = priv; 289 int retry, error; 290 291 #if notyet 292 if (cold) 293 #endif 294 flags |= I2C_F_POLL; 295 296 KASSERT(mutex_owned(&sc->sc_lock)); 297 298 if ((flags & I2C_F_POLL) == 0) { 299 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 300 I2C_INTERRUPT_MASK_NOACK | I2C_INTERRUPT_MASK_ARB_LOST | 301 I2C_INTERRUPT_MASK_TIMEOUT | 302 I2C_INTERRUPT_MASK_ALL_PACKETS_XFER_COMPLETE); 303 } 304 305 const uint32_t flush_mask = 306 I2C_FIFO_CONTROL_TX_FIFO_FLUSH | I2C_FIFO_CONTROL_RX_FIFO_FLUSH; 307 308 I2C_SET_CLEAR(sc, I2C_FIFO_CONTROL_REG, flush_mask, 0); 309 for (retry = 10000; retry > 0; retry--) { 310 const uint32_t v = I2C_READ(sc, I2C_FIFO_CONTROL_REG); 311 if ((v & flush_mask) == 0) 312 break; 313 delay(1); 314 } 315 if (retry == 0) { 316 device_printf(sc->sc_dev, "timeout flushing FIFO\n"); 317 return EIO; 318 } 319 320 if (cmdlen > 0) { 321 error = tegra_i2c_write(sc, addr, cmdbuf, cmdlen, flags, 322 buflen > 0 ? true : false); 323 if (error) { 324 goto done; 325 } 326 } 327 328 if (I2C_OP_READ_P(op)) { 329 error = tegra_i2c_read(sc, addr, buf, buflen, flags); 330 } else { 331 error = tegra_i2c_write(sc, addr, buf, buflen, flags, false); 332 } 333 334 done: 335 if ((flags & I2C_F_POLL) == 0) { 336 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 0); 337 } 338 339 if (error) { 340 tegra_i2c_init(sc); 341 } 342 343 return error; 344 } 345 346 static int 347 tegra_i2c_wait(struct tegra_i2c_softc *sc, int flags) 348 { 349 int error, retry; 350 uint32_t stat = 0; 351 352 retry = (flags & I2C_F_POLL) ? 100000 : 100; 353 354 while (--retry > 0) { 355 if ((flags & I2C_F_POLL) == 0) { 356 error = cv_timedwait_sig(&sc->sc_cv, &sc->sc_lock, 357 max(mstohz(10), 1)); 358 if (error) { 359 return error; 360 } 361 } 362 stat = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 363 if (stat & I2C_INTERRUPT_STATUS_PACKET_XFER_COMPLETE) { 364 break; 365 } 366 if (flags & I2C_F_POLL) { 367 delay(10); 368 } 369 } 370 if (retry == 0) { 371 stat = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 372 device_printf(sc->sc_dev, "timed out, status = %#x\n", stat); 373 return ETIMEDOUT; 374 } 375 376 const uint32_t err_mask = 377 I2C_INTERRUPT_STATUS_NOACK | 378 I2C_INTERRUPT_STATUS_ARB_LOST | 379 I2C_INTERRUPT_MASK_TIMEOUT; 380 381 if (stat & err_mask) { 382 device_printf(sc->sc_dev, "error, status = %#x\n", stat); 383 return EIO; 384 } 385 386 return 0; 387 } 388 389 static int 390 tegra_i2c_write(struct tegra_i2c_softc *sc, i2c_addr_t addr, const uint8_t *buf, 391 size_t buflen, int flags, bool repeat_start) 392 { 393 const uint8_t *p = buf; 394 size_t n, resid = buflen; 395 uint32_t data; 396 int retry; 397 398 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 399 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 400 401 /* Generic Header 0 */ 402 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 403 __SHIFTIN(I2C_IOPACKET_WORD0_PROTHDRSZ_REQ, 404 I2C_IOPACKET_WORD0_PROTHDRSZ) | 405 __SHIFTIN(sc->sc_cid, I2C_IOPACKET_WORD0_CONTROLLERID) | 406 __SHIFTIN(1, I2C_IOPACKET_WORD0_PKTID) | 407 __SHIFTIN(I2C_IOPACKET_WORD0_PROTOCOL_I2C, 408 I2C_IOPACKET_WORD0_PROTOCOL) | 409 __SHIFTIN(I2C_IOPACKET_WORD0_PKTTYPE_REQ, 410 I2C_IOPACKET_WORD0_PKTTYPE)); 411 /* Generic Header 1 */ 412 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 413 __SHIFTIN(buflen - 1, I2C_IOPACKET_WORD1_PAYLOADSIZE)); 414 /* I2C Master Transmit Packet Header */ 415 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 416 I2C_IOPACKET_XMITHDR_IE | 417 (repeat_start ? I2C_IOPACKET_XMITHDR_REPEAT_STARTSTOP : 0) | 418 __SHIFTIN((addr << 1), I2C_IOPACKET_XMITHDR_SLAVE_ADDR)); 419 420 /* Transmit data */ 421 while (resid > 0) { 422 retry = 10000; 423 while (--retry > 0) { 424 const uint32_t fs = I2C_READ(sc, I2C_FIFO_STATUS_REG); 425 const u_int cnt = 426 __SHIFTOUT(fs, I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT); 427 if (cnt > 0) 428 break; 429 delay(10); 430 } 431 if (retry == 0) { 432 device_printf(sc->sc_dev, "TX FIFO timeout\n"); 433 return ETIMEDOUT; 434 } 435 436 for (n = 0, data = 0; n < min(resid, 4); n++) { 437 data |= (uint32_t)p[n] << (n * 8); 438 } 439 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, data); 440 p += min(resid, 4); 441 resid -= min(resid, 4); 442 } 443 444 return tegra_i2c_wait(sc, flags); 445 } 446 447 static int 448 tegra_i2c_read(struct tegra_i2c_softc *sc, i2c_addr_t addr, uint8_t *buf, 449 size_t buflen, int flags) 450 { 451 uint8_t *p = buf; 452 size_t n, resid = buflen; 453 uint32_t data; 454 int retry; 455 456 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 457 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 458 459 /* Generic Header 0 */ 460 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 461 __SHIFTIN(I2C_IOPACKET_WORD0_PROTHDRSZ_REQ, 462 I2C_IOPACKET_WORD0_PROTHDRSZ) | 463 __SHIFTIN(sc->sc_cid, I2C_IOPACKET_WORD0_CONTROLLERID) | 464 __SHIFTIN(1, I2C_IOPACKET_WORD0_PKTID) | 465 __SHIFTIN(I2C_IOPACKET_WORD0_PROTOCOL_I2C, 466 I2C_IOPACKET_WORD0_PROTOCOL) | 467 __SHIFTIN(I2C_IOPACKET_WORD0_PKTTYPE_REQ, 468 I2C_IOPACKET_WORD0_PKTTYPE)); 469 /* Generic Header 1 */ 470 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 471 __SHIFTIN(buflen - 1, I2C_IOPACKET_WORD1_PAYLOADSIZE)); 472 /* I2C Master Transmit Packet Header */ 473 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 474 I2C_IOPACKET_XMITHDR_IE | I2C_IOPACKET_XMITHDR_READ | 475 __SHIFTIN((addr << 1) | 1, I2C_IOPACKET_XMITHDR_SLAVE_ADDR)); 476 477 while (resid > 0) { 478 retry = 10000; 479 while (--retry > 0) { 480 const uint32_t fs = I2C_READ(sc, I2C_FIFO_STATUS_REG); 481 const u_int cnt = 482 __SHIFTOUT(fs, I2C_FIFO_STATUS_RX_FIFO_FULL_CNT); 483 if (cnt > 0) 484 break; 485 delay(10); 486 } 487 if (retry == 0) { 488 device_printf(sc->sc_dev, "RX FIFO timeout\n"); 489 return ETIMEDOUT; 490 } 491 492 data = I2C_READ(sc, I2C_RX_FIFO_REG); 493 for (n = 0; n < min(resid, 4); n++) { 494 p[n] = (data >> (n * 8)) & 0xff; 495 } 496 p += min(resid, 4); 497 resid -= min(resid, 4); 498 } 499 500 return tegra_i2c_wait(sc, flags); 501 } 502
Indexes created Thu Oct 02 01:09:59 GMT 2025