tegra_i2c.c revision 1.6
1 /* $NetBSD: tegra_i2c.c,v 1.6 2015/11/11 11:32:01 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "locators.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: tegra_i2c.c,v 1.6 2015/11/11 11:32:01 jmcneill Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 41 #include <dev/i2c/i2cvar.h> 42 43 #include <arm/nvidia/tegra_reg.h> 44 #include <arm/nvidia/tegra_i2creg.h> 45 #include <arm/nvidia/tegra_var.h> 46 47 static int tegra_i2c_match(device_t, cfdata_t, void *); 48 static void tegra_i2c_attach(device_t, device_t, void *); 49 50 struct tegra_i2c_softc { 51 device_t sc_dev; 52 bus_space_tag_t sc_bst; 53 bus_space_handle_t sc_bsh; 54 void * sc_ih; 55 u_int sc_port; 56 57 struct i2c_controller sc_ic; 58 kmutex_t sc_lock; 59 kcondvar_t sc_cv; 60 device_t sc_i2cdev; 61 }; 62 63 static void tegra_i2c_init(struct tegra_i2c_softc *); 64 static int tegra_i2c_intr(void *); 65 66 static int tegra_i2c_acquire_bus(void *, int); 67 static void tegra_i2c_release_bus(void *, int); 68 static int tegra_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 69 size_t, void *, size_t, int); 70 71 static int tegra_i2c_wait(struct tegra_i2c_softc *, int); 72 static int tegra_i2c_write(struct tegra_i2c_softc *, i2c_addr_t, 73 const uint8_t *, size_t, int, bool); 74 static int tegra_i2c_read(struct tegra_i2c_softc *, i2c_addr_t, uint8_t *, 75 size_t, int); 76 77 CFATTACH_DECL_NEW(tegra_i2c, sizeof(struct tegra_i2c_softc), 78 tegra_i2c_match, tegra_i2c_attach, NULL, NULL); 79 80 #define I2C_WRITE(sc, reg, val) \ 81 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 82 #define I2C_READ(sc, reg) \ 83 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 84 #define I2C_SET_CLEAR(sc, reg, setval, clrval) \ 85 tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (setval), (clrval)) 86 87 static int 88 tegra_i2c_match(device_t parent, cfdata_t cf, void *aux) 89 { 90 struct tegraio_attach_args * const tio = aux; 91 const struct tegra_locators * const loc = &tio->tio_loc; 92 93 if (loc->loc_port == TEGRAIOCF_PORT_DEFAULT) 94 return 0; 95 96 return 1; 97 } 98 99 static void 100 tegra_i2c_attach(device_t parent, device_t self, void *aux) 101 { 102 struct tegra_i2c_softc * const sc = device_private(self); 103 struct tegraio_attach_args * const tio = aux; 104 const struct tegra_locators * const loc = &tio->tio_loc; 105 struct i2cbus_attach_args iba; 106 107 sc->sc_dev = self; 108 sc->sc_bst = tio->tio_bst; 109 bus_space_subregion(tio->tio_bst, tio->tio_bsh, 110 loc->loc_offset, loc->loc_size, &sc->sc_bsh); 111 sc->sc_port = loc->loc_port; 112 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 113 cv_init(&sc->sc_cv, device_xname(self)); 114 115 aprint_naive("\n"); 116 aprint_normal(": I2C%d\n", loc->loc_port + 1); 117 118 sc->sc_ih = intr_establish(loc->loc_intr, IPL_VM, IST_LEVEL|IST_MPSAFE, 119 tegra_i2c_intr, sc); 120 if (sc->sc_ih == NULL) { 121 aprint_error_dev(self, "couldn't establish interrupt %d\n", 122 loc->loc_intr); 123 return; 124 } 125 aprint_normal_dev(self, "interrupting on irq %d\n", loc->loc_intr); 126 127 /* Recommended setting for standard mode */ 128 tegra_car_periph_i2c_enable(loc->loc_port, 204000000); 129 130 tegra_i2c_init(sc); 131 132 sc->sc_ic.ic_cookie = sc; 133 sc->sc_ic.ic_acquire_bus = tegra_i2c_acquire_bus; 134 sc->sc_ic.ic_release_bus = tegra_i2c_release_bus; 135 sc->sc_ic.ic_exec = tegra_i2c_exec; 136 137 iba.iba_tag = &sc->sc_ic; 138 sc->sc_i2cdev = config_found_ia(self, "i2cbus", &iba, iicbus_print); 139 } 140 141 static void 142 tegra_i2c_init(struct tegra_i2c_softc *sc) 143 { 144 int retry = 10000; 145 146 I2C_WRITE(sc, I2C_CLK_DIVISOR_REG, 147 __SHIFTIN(0x19, I2C_CLK_DIVISOR_STD_FAST_MODE) | 148 __SHIFTIN(0x1, I2C_CLK_DIVISOR_HSMODE)); 149 150 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 0); 151 I2C_WRITE(sc, I2C_CNFG_REG, 152 I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN); 153 I2C_SET_CLEAR(sc, I2C_SL_CNFG_REG, I2C_SL_CNFG_NEWSL, 0); 154 I2C_WRITE(sc, I2C_FIFO_CONTROL_REG, 155 __SHIFTIN(7, I2C_FIFO_CONTROL_TX_FIFO_TRIG) | 156 __SHIFTIN(0, I2C_FIFO_CONTROL_RX_FIFO_TRIG)); 157 158 I2C_WRITE(sc, I2C_BUS_CONFIG_LOAD_REG, 159 I2C_BUS_CONFIG_LOAD_MSTR_CONFIG_LOAD); 160 while (--retry > 0) { 161 if (I2C_READ(sc, I2C_BUS_CONFIG_LOAD_REG) == 0) 162 break; 163 delay(10); 164 } 165 if (retry == 0) { 166 device_printf(sc->sc_dev, "config load timeout\n"); 167 } 168 } 169 170 static int 171 tegra_i2c_intr(void *priv) 172 { 173 struct tegra_i2c_softc * const sc = priv; 174 175 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 176 if (istatus == 0) 177 return 0; 178 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 179 180 mutex_enter(&sc->sc_lock); 181 cv_broadcast(&sc->sc_cv); 182 mutex_exit(&sc->sc_lock); 183 184 return 1; 185 } 186 187 static int 188 tegra_i2c_acquire_bus(void *priv, int flags) 189 { 190 struct tegra_i2c_softc * const sc = priv; 191 192 mutex_enter(&sc->sc_lock); 193 194 return 0; 195 } 196 197 static void 198 tegra_i2c_release_bus(void *priv, int flags) 199 { 200 struct tegra_i2c_softc * const sc = priv; 201 202 mutex_exit(&sc->sc_lock); 203 } 204 205 static int 206 tegra_i2c_exec(void *priv, i2c_op_t op, i2c_addr_t addr, const void *cmdbuf, 207 size_t cmdlen, void *buf, size_t buflen, int flags) 208 { 209 struct tegra_i2c_softc * const sc = priv; 210 int retry, error; 211 212 #if notyet 213 if (cold) 214 #endif 215 flags |= I2C_F_POLL; 216 217 KASSERT(mutex_owned(&sc->sc_lock)); 218 219 if ((flags & I2C_F_POLL) == 0) { 220 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 221 I2C_INTERRUPT_MASK_NOACK | I2C_INTERRUPT_MASK_ARB_LOST | 222 I2C_INTERRUPT_MASK_TIMEOUT | 223 I2C_INTERRUPT_MASK_ALL_PACKETS_XFER_COMPLETE); 224 } 225 226 const uint32_t flush_mask = 227 I2C_FIFO_CONTROL_TX_FIFO_FLUSH | I2C_FIFO_CONTROL_RX_FIFO_FLUSH; 228 229 I2C_SET_CLEAR(sc, I2C_FIFO_CONTROL_REG, flush_mask, 0); 230 for (retry = 10000; retry > 0; retry--) { 231 const uint32_t v = I2C_READ(sc, I2C_FIFO_CONTROL_REG); 232 if ((v & flush_mask) == 0) 233 break; 234 delay(1); 235 } 236 if (retry == 0) { 237 device_printf(sc->sc_dev, "timeout flushing FIFO\n"); 238 return EIO; 239 } 240 241 if (cmdlen > 0) { 242 error = tegra_i2c_write(sc, addr, cmdbuf, cmdlen, flags, true); 243 if (error) { 244 goto done; 245 } 246 } 247 248 if (I2C_OP_READ_P(op)) { 249 error = tegra_i2c_read(sc, addr, buf, buflen, flags); 250 } else { 251 error = tegra_i2c_write(sc, addr, buf, buflen, flags, false); 252 } 253 254 done: 255 if ((flags & I2C_F_POLL) == 0) { 256 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 0); 257 } 258 259 if (error) { 260 tegra_i2c_init(sc); 261 } 262 263 return error; 264 } 265 266 static int 267 tegra_i2c_wait(struct tegra_i2c_softc *sc, int flags) 268 { 269 int error, retry; 270 uint32_t stat = 0; 271 272 retry = (flags & I2C_F_POLL) ? 100000 : 100; 273 274 while (--retry > 0) { 275 if ((flags & I2C_F_POLL) == 0) { 276 error = cv_timedwait_sig(&sc->sc_cv, &sc->sc_lock, 277 max(mstohz(10), 1)); 278 if (error) { 279 return error; 280 } 281 } 282 stat = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 283 if (stat & I2C_INTERRUPT_STATUS_PACKET_XFER_COMPLETE) { 284 break; 285 } 286 if (flags & I2C_F_POLL) { 287 delay(10); 288 } 289 } 290 if (retry == 0) { 291 stat = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 292 device_printf(sc->sc_dev, "timed out, status = %#x\n", stat); 293 return ETIMEDOUT; 294 } 295 296 const uint32_t err_mask = 297 I2C_INTERRUPT_STATUS_NOACK | 298 I2C_INTERRUPT_STATUS_ARB_LOST | 299 I2C_INTERRUPT_MASK_TIMEOUT; 300 301 if (stat & err_mask) { 302 device_printf(sc->sc_dev, "error, status = %#x\n", stat); 303 return EIO; 304 } 305 306 return 0; 307 } 308 309 static int 310 tegra_i2c_write(struct tegra_i2c_softc *sc, i2c_addr_t addr, const uint8_t *buf, 311 size_t buflen, int flags, bool repeat_start) 312 { 313 const uint8_t *p = buf; 314 size_t n, resid = buflen; 315 uint32_t data; 316 int retry; 317 318 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 319 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 320 321 /* Generic Header 0 */ 322 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 323 __SHIFTIN(I2C_IOPACKET_WORD0_PROTHDRSZ_REQ, 324 I2C_IOPACKET_WORD0_PROTHDRSZ) | 325 __SHIFTIN(sc->sc_port, I2C_IOPACKET_WORD0_CONTROLLERID) | 326 __SHIFTIN(1, I2C_IOPACKET_WORD0_PKTID) | 327 __SHIFTIN(I2C_IOPACKET_WORD0_PROTOCOL_I2C, 328 I2C_IOPACKET_WORD0_PROTOCOL) | 329 __SHIFTIN(I2C_IOPACKET_WORD0_PKTTYPE_REQ, 330 I2C_IOPACKET_WORD0_PKTTYPE)); 331 /* Generic Header 1 */ 332 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 333 __SHIFTIN(buflen - 1, I2C_IOPACKET_WORD1_PAYLOADSIZE)); 334 /* I2C Master Transmit Packet Header */ 335 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 336 I2C_IOPACKET_XMITHDR_IE | 337 (repeat_start ? I2C_IOPACKET_XMITHDR_REPEAT_STARTSTOP : 0) | 338 __SHIFTIN((addr << 1), I2C_IOPACKET_XMITHDR_SLAVE_ADDR)); 339 340 /* Transmit data */ 341 while (resid > 0) { 342 retry = 10000; 343 while (--retry > 0) { 344 const uint32_t fs = I2C_READ(sc, I2C_FIFO_STATUS_REG); 345 const u_int cnt = 346 __SHIFTOUT(fs, I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT); 347 if (cnt > 0) 348 break; 349 delay(10); 350 } 351 if (retry == 0) { 352 device_printf(sc->sc_dev, "TX FIFO timeout\n"); 353 return ETIMEDOUT; 354 } 355 356 for (n = 0, data = 0; n < min(resid, 4); n++) { 357 data |= (uint32_t)p[n] << (n * 8); 358 } 359 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, data); 360 resid -= min(resid, 4); 361 p += min(resid, 4); 362 } 363 364 return tegra_i2c_wait(sc, flags); 365 } 366 367 static int 368 tegra_i2c_read(struct tegra_i2c_softc *sc, i2c_addr_t addr, uint8_t *buf, 369 size_t buflen, int flags) 370 { 371 uint8_t *p = buf; 372 size_t n, resid = buflen; 373 uint32_t data; 374 int retry; 375 376 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 377 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 378 379 /* Generic Header 0 */ 380 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 381 __SHIFTIN(I2C_IOPACKET_WORD0_PROTHDRSZ_REQ, 382 I2C_IOPACKET_WORD0_PROTHDRSZ) | 383 __SHIFTIN(sc->sc_port, I2C_IOPACKET_WORD0_CONTROLLERID) | 384 __SHIFTIN(1, I2C_IOPACKET_WORD0_PKTID) | 385 __SHIFTIN(I2C_IOPACKET_WORD0_PROTOCOL_I2C, 386 I2C_IOPACKET_WORD0_PROTOCOL) | 387 __SHIFTIN(I2C_IOPACKET_WORD0_PKTTYPE_REQ, 388 I2C_IOPACKET_WORD0_PKTTYPE)); 389 /* Generic Header 1 */ 390 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 391 __SHIFTIN(buflen - 1, I2C_IOPACKET_WORD1_PAYLOADSIZE)); 392 /* I2C Master Transmit Packet Header */ 393 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 394 I2C_IOPACKET_XMITHDR_IE | I2C_IOPACKET_XMITHDR_READ | 395 __SHIFTIN((addr << 1) | 1, I2C_IOPACKET_XMITHDR_SLAVE_ADDR)); 396 397 while (resid > 0) { 398 retry = 10000; 399 while (--retry > 0) { 400 const uint32_t fs = I2C_READ(sc, I2C_FIFO_STATUS_REG); 401 const u_int cnt = 402 __SHIFTOUT(fs, I2C_FIFO_STATUS_RX_FIFO_FULL_CNT); 403 if (cnt > 0) 404 break; 405 delay(10); 406 } 407 if (retry == 0) { 408 device_printf(sc->sc_dev, "RX FIFO timeout\n"); 409 return ETIMEDOUT; 410 } 411 412 data = I2C_READ(sc, I2C_RX_FIFO_REG); 413 for (n = 0; n < min(resid, 4); n++) { 414 p[n] = (data >> (n * 8)) & 0xff; 415 } 416 resid -= min(resid, 4); 417 p += min(resid, 4); 418 } 419 420 return tegra_i2c_wait(sc, flags); 421 } 422 423 void 424 tegra_i2c_dvc_write(uint8_t addr, uint32_t data, size_t datalen) 425 { 426 bus_space_tag_t bst = &armv7_generic_bs_tag; 427 bus_space_handle_t bsh; 428 429 bus_space_subregion(bst, tegra_apb_bsh, TEGRA_I2C5_OFFSET, 430 TEGRA_I2C5_SIZE, &bsh); 431 432 bus_space_write_4(bst, bsh, I2C_CMD_ADDR0_REG, addr << 1); 433 bus_space_write_4(bst, bsh, I2C_CMD_DATA1_REG, data); 434 bus_space_write_4(bst, bsh, I2C_CNFG_REG, 435 __SHIFTIN(datalen - 1, I2C_CNFG_LENGTH) | 436 I2C_CNFG_NEW_MASTER_FSM | 437 I2C_CNFG_SEND); 438 } 439
Indexes created Thu Oct 02 01:09:59 GMT 2025