tegra_i2c.c revision 1.8
1 /* $NetBSD: tegra_i2c.c,v 1.8 2015/11/12 10:31:29 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "locators.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: tegra_i2c.c,v 1.8 2015/11/12 10:31:29 jmcneill Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 41 #include <dev/i2c/i2cvar.h> 42 43 #include <arm/nvidia/tegra_reg.h> 44 #include <arm/nvidia/tegra_i2creg.h> 45 #include <arm/nvidia/tegra_var.h> 46 47 static int tegra_i2c_match(device_t, cfdata_t, void *); 48 static void tegra_i2c_attach(device_t, device_t, void *); 49 50 struct tegra_i2c_softc { 51 device_t sc_dev; 52 bus_space_tag_t sc_bst; 53 bus_space_handle_t sc_bsh; 54 void * sc_ih; 55 u_int sc_port; 56 57 struct i2c_controller sc_ic; 58 kmutex_t sc_lock; 59 kcondvar_t sc_cv; 60 device_t sc_i2cdev; 61 }; 62 63 static void tegra_i2c_init(struct tegra_i2c_softc *); 64 static int tegra_i2c_intr(void *); 65 66 static int tegra_i2c_acquire_bus(void *, int); 67 static void tegra_i2c_release_bus(void *, int); 68 static int tegra_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 69 size_t, void *, size_t, int); 70 71 static int tegra_i2c_wait(struct tegra_i2c_softc *, int); 72 static int tegra_i2c_write(struct tegra_i2c_softc *, i2c_addr_t, 73 const uint8_t *, size_t, int, bool); 74 static int tegra_i2c_read(struct tegra_i2c_softc *, i2c_addr_t, uint8_t *, 75 size_t, int); 76 77 CFATTACH_DECL_NEW(tegra_i2c, sizeof(struct tegra_i2c_softc), 78 tegra_i2c_match, tegra_i2c_attach, NULL, NULL); 79 80 #define I2C_WRITE(sc, reg, val) \ 81 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 82 #define I2C_READ(sc, reg) \ 83 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 84 #define I2C_SET_CLEAR(sc, reg, setval, clrval) \ 85 tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (setval), (clrval)) 86 87 static int 88 tegra_i2c_match(device_t parent, cfdata_t cf, void *aux) 89 { 90 struct tegraio_attach_args * const tio = aux; 91 const struct tegra_locators * const loc = &tio->tio_loc; 92 93 if (loc->loc_port == TEGRAIOCF_PORT_DEFAULT) 94 return 0; 95 96 return 1; 97 } 98 99 static void 100 tegra_i2c_attach(device_t parent, device_t self, void *aux) 101 { 102 struct tegra_i2c_softc * const sc = device_private(self); 103 struct tegraio_attach_args * const tio = aux; 104 const struct tegra_locators * const loc = &tio->tio_loc; 105 struct i2cbus_attach_args iba; 106 107 sc->sc_dev = self; 108 sc->sc_bst = tio->tio_bst; 109 bus_space_subregion(tio->tio_bst, tio->tio_bsh, 110 loc->loc_offset, loc->loc_size, &sc->sc_bsh); 111 sc->sc_port = loc->loc_port; 112 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 113 cv_init(&sc->sc_cv, device_xname(self)); 114 115 aprint_naive("\n"); 116 aprint_normal(": I2C%d\n", loc->loc_port + 1); 117 118 sc->sc_ih = intr_establish(loc->loc_intr, IPL_VM, IST_LEVEL|IST_MPSAFE, 119 tegra_i2c_intr, sc); 120 if (sc->sc_ih == NULL) { 121 aprint_error_dev(self, "couldn't establish interrupt %d\n", 122 loc->loc_intr); 123 return; 124 } 125 aprint_normal_dev(self, "interrupting on irq %d\n", loc->loc_intr); 126 127 /* 128 * Recommended setting for standard mode is to use an I2C source div 129 * of 20 (Tegra K1 Technical Reference Manual, Table 137) 130 */ 131 tegra_car_periph_i2c_enable(loc->loc_port, 20400000); 132 133 tegra_i2c_init(sc); 134 135 sc->sc_ic.ic_cookie = sc; 136 sc->sc_ic.ic_acquire_bus = tegra_i2c_acquire_bus; 137 sc->sc_ic.ic_release_bus = tegra_i2c_release_bus; 138 sc->sc_ic.ic_exec = tegra_i2c_exec; 139 140 iba.iba_tag = &sc->sc_ic; 141 sc->sc_i2cdev = config_found_ia(self, "i2cbus", &iba, iicbus_print); 142 } 143 144 static void 145 tegra_i2c_init(struct tegra_i2c_softc *sc) 146 { 147 int retry = 10000; 148 149 I2C_WRITE(sc, I2C_CLK_DIVISOR_REG, 150 __SHIFTIN(0x19, I2C_CLK_DIVISOR_STD_FAST_MODE) | 151 __SHIFTIN(0x1, I2C_CLK_DIVISOR_HSMODE)); 152 153 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 0); 154 I2C_WRITE(sc, I2C_CNFG_REG, 155 I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN); 156 I2C_SET_CLEAR(sc, I2C_SL_CNFG_REG, I2C_SL_CNFG_NEWSL, 0); 157 I2C_WRITE(sc, I2C_FIFO_CONTROL_REG, 158 __SHIFTIN(7, I2C_FIFO_CONTROL_TX_FIFO_TRIG) | 159 __SHIFTIN(0, I2C_FIFO_CONTROL_RX_FIFO_TRIG)); 160 161 I2C_WRITE(sc, I2C_BUS_CONFIG_LOAD_REG, 162 I2C_BUS_CONFIG_LOAD_MSTR_CONFIG_LOAD); 163 while (--retry > 0) { 164 if (I2C_READ(sc, I2C_BUS_CONFIG_LOAD_REG) == 0) 165 break; 166 delay(10); 167 } 168 if (retry == 0) { 169 device_printf(sc->sc_dev, "config load timeout\n"); 170 } 171 } 172 173 static int 174 tegra_i2c_intr(void *priv) 175 { 176 struct tegra_i2c_softc * const sc = priv; 177 178 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 179 if (istatus == 0) 180 return 0; 181 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 182 183 mutex_enter(&sc->sc_lock); 184 cv_broadcast(&sc->sc_cv); 185 mutex_exit(&sc->sc_lock); 186 187 return 1; 188 } 189 190 static int 191 tegra_i2c_acquire_bus(void *priv, int flags) 192 { 193 struct tegra_i2c_softc * const sc = priv; 194 195 mutex_enter(&sc->sc_lock); 196 197 return 0; 198 } 199 200 static void 201 tegra_i2c_release_bus(void *priv, int flags) 202 { 203 struct tegra_i2c_softc * const sc = priv; 204 205 mutex_exit(&sc->sc_lock); 206 } 207 208 static int 209 tegra_i2c_exec(void *priv, i2c_op_t op, i2c_addr_t addr, const void *cmdbuf, 210 size_t cmdlen, void *buf, size_t buflen, int flags) 211 { 212 struct tegra_i2c_softc * const sc = priv; 213 int retry, error; 214 215 #if notyet 216 if (cold) 217 #endif 218 flags |= I2C_F_POLL; 219 220 KASSERT(mutex_owned(&sc->sc_lock)); 221 222 if ((flags & I2C_F_POLL) == 0) { 223 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 224 I2C_INTERRUPT_MASK_NOACK | I2C_INTERRUPT_MASK_ARB_LOST | 225 I2C_INTERRUPT_MASK_TIMEOUT | 226 I2C_INTERRUPT_MASK_ALL_PACKETS_XFER_COMPLETE); 227 } 228 229 const uint32_t flush_mask = 230 I2C_FIFO_CONTROL_TX_FIFO_FLUSH | I2C_FIFO_CONTROL_RX_FIFO_FLUSH; 231 232 I2C_SET_CLEAR(sc, I2C_FIFO_CONTROL_REG, flush_mask, 0); 233 for (retry = 10000; retry > 0; retry--) { 234 const uint32_t v = I2C_READ(sc, I2C_FIFO_CONTROL_REG); 235 if ((v & flush_mask) == 0) 236 break; 237 delay(1); 238 } 239 if (retry == 0) { 240 device_printf(sc->sc_dev, "timeout flushing FIFO\n"); 241 return EIO; 242 } 243 244 if (cmdlen > 0) { 245 error = tegra_i2c_write(sc, addr, cmdbuf, cmdlen, flags, 246 I2C_OP_READ_P(op) ? true : false); 247 if (error) { 248 goto done; 249 } 250 } 251 252 if (I2C_OP_READ_P(op)) { 253 error = tegra_i2c_read(sc, addr, buf, buflen, flags); 254 } else { 255 error = tegra_i2c_write(sc, addr, buf, buflen, flags, false); 256 } 257 258 done: 259 if ((flags & I2C_F_POLL) == 0) { 260 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 0); 261 } 262 263 if (error) { 264 tegra_i2c_init(sc); 265 } 266 267 return error; 268 } 269 270 static int 271 tegra_i2c_wait(struct tegra_i2c_softc *sc, int flags) 272 { 273 int error, retry; 274 uint32_t stat = 0; 275 276 retry = (flags & I2C_F_POLL) ? 100000 : 100; 277 278 while (--retry > 0) { 279 if ((flags & I2C_F_POLL) == 0) { 280 error = cv_timedwait_sig(&sc->sc_cv, &sc->sc_lock, 281 max(mstohz(10), 1)); 282 if (error) { 283 return error; 284 } 285 } 286 stat = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 287 if (stat & I2C_INTERRUPT_STATUS_PACKET_XFER_COMPLETE) { 288 break; 289 } 290 if (flags & I2C_F_POLL) { 291 delay(10); 292 } 293 } 294 if (retry == 0) { 295 stat = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 296 device_printf(sc->sc_dev, "timed out, status = %#x\n", stat); 297 return ETIMEDOUT; 298 } 299 300 const uint32_t err_mask = 301 I2C_INTERRUPT_STATUS_NOACK | 302 I2C_INTERRUPT_STATUS_ARB_LOST | 303 I2C_INTERRUPT_MASK_TIMEOUT; 304 305 if (stat & err_mask) { 306 device_printf(sc->sc_dev, "error, status = %#x\n", stat); 307 return EIO; 308 } 309 310 return 0; 311 } 312 313 static int 314 tegra_i2c_write(struct tegra_i2c_softc *sc, i2c_addr_t addr, const uint8_t *buf, 315 size_t buflen, int flags, bool repeat_start) 316 { 317 const uint8_t *p = buf; 318 size_t n, resid = buflen; 319 uint32_t data; 320 int retry; 321 322 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 323 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 324 325 /* Generic Header 0 */ 326 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 327 __SHIFTIN(I2C_IOPACKET_WORD0_PROTHDRSZ_REQ, 328 I2C_IOPACKET_WORD0_PROTHDRSZ) | 329 __SHIFTIN(sc->sc_port, I2C_IOPACKET_WORD0_CONTROLLERID) | 330 __SHIFTIN(1, I2C_IOPACKET_WORD0_PKTID) | 331 __SHIFTIN(I2C_IOPACKET_WORD0_PROTOCOL_I2C, 332 I2C_IOPACKET_WORD0_PROTOCOL) | 333 __SHIFTIN(I2C_IOPACKET_WORD0_PKTTYPE_REQ, 334 I2C_IOPACKET_WORD0_PKTTYPE)); 335 /* Generic Header 1 */ 336 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 337 __SHIFTIN(buflen - 1, I2C_IOPACKET_WORD1_PAYLOADSIZE)); 338 /* I2C Master Transmit Packet Header */ 339 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 340 I2C_IOPACKET_XMITHDR_IE | 341 (repeat_start ? I2C_IOPACKET_XMITHDR_REPEAT_STARTSTOP : 0) | 342 __SHIFTIN((addr << 1), I2C_IOPACKET_XMITHDR_SLAVE_ADDR)); 343 344 /* Transmit data */ 345 while (resid > 0) { 346 retry = 10000; 347 while (--retry > 0) { 348 const uint32_t fs = I2C_READ(sc, I2C_FIFO_STATUS_REG); 349 const u_int cnt = 350 __SHIFTOUT(fs, I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT); 351 if (cnt > 0) 352 break; 353 delay(10); 354 } 355 if (retry == 0) { 356 device_printf(sc->sc_dev, "TX FIFO timeout\n"); 357 return ETIMEDOUT; 358 } 359 360 for (n = 0, data = 0; n < min(resid, 4); n++) { 361 data |= (uint32_t)p[n] << (n * 8); 362 } 363 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, data); 364 resid -= min(resid, 4); 365 p += min(resid, 4); 366 } 367 368 return tegra_i2c_wait(sc, flags); 369 } 370 371 static int 372 tegra_i2c_read(struct tegra_i2c_softc *sc, i2c_addr_t addr, uint8_t *buf, 373 size_t buflen, int flags) 374 { 375 uint8_t *p = buf; 376 size_t n, resid = buflen; 377 uint32_t data; 378 int retry; 379 380 const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG); 381 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); 382 383 /* Generic Header 0 */ 384 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 385 __SHIFTIN(I2C_IOPACKET_WORD0_PROTHDRSZ_REQ, 386 I2C_IOPACKET_WORD0_PROTHDRSZ) | 387 __SHIFTIN(sc->sc_port, I2C_IOPACKET_WORD0_CONTROLLERID) | 388 __SHIFTIN(1, I2C_IOPACKET_WORD0_PKTID) | 389 __SHIFTIN(I2C_IOPACKET_WORD0_PROTOCOL_I2C, 390 I2C_IOPACKET_WORD0_PROTOCOL) | 391 __SHIFTIN(I2C_IOPACKET_WORD0_PKTTYPE_REQ, 392 I2C_IOPACKET_WORD0_PKTTYPE)); 393 /* Generic Header 1 */ 394 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 395 __SHIFTIN(buflen - 1, I2C_IOPACKET_WORD1_PAYLOADSIZE)); 396 /* I2C Master Transmit Packet Header */ 397 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, 398 I2C_IOPACKET_XMITHDR_IE | I2C_IOPACKET_XMITHDR_READ | 399 __SHIFTIN((addr << 1) | 1, I2C_IOPACKET_XMITHDR_SLAVE_ADDR)); 400 401 while (resid > 0) { 402 retry = 10000; 403 while (--retry > 0) { 404 const uint32_t fs = I2C_READ(sc, I2C_FIFO_STATUS_REG); 405 const u_int cnt = 406 __SHIFTOUT(fs, I2C_FIFO_STATUS_RX_FIFO_FULL_CNT); 407 if (cnt > 0) 408 break; 409 delay(10); 410 } 411 if (retry == 0) { 412 device_printf(sc->sc_dev, "RX FIFO timeout\n"); 413 return ETIMEDOUT; 414 } 415 416 data = I2C_READ(sc, I2C_RX_FIFO_REG); 417 for (n = 0; n < min(resid, 4); n++) { 418 p[n] = (data >> (n * 8)) & 0xff; 419 } 420 resid -= min(resid, 4); 421 p += min(resid, 4); 422 } 423 424 return tegra_i2c_wait(sc, flags); 425 } 426 427 void 428 tegra_i2c_dvc_write(uint8_t addr, uint32_t data, size_t datalen) 429 { 430 bus_space_tag_t bst = &armv7_generic_bs_tag; 431 bus_space_handle_t bsh; 432 433 bus_space_subregion(bst, tegra_apb_bsh, TEGRA_I2C5_OFFSET, 434 TEGRA_I2C5_SIZE, &bsh); 435 436 bus_space_write_4(bst, bsh, I2C_CMD_ADDR0_REG, addr << 1); 437 bus_space_write_4(bst, bsh, I2C_CMD_DATA1_REG, data); 438 bus_space_write_4(bst, bsh, I2C_CNFG_REG, 439 __SHIFTIN(datalen - 1, I2C_CNFG_LENGTH) | 440 I2C_CNFG_NEW_MASTER_FSM | 441 I2C_CNFG_SEND); 442 } 443
Indexes created Thu Oct 02 01:09:59 GMT 2025