tegra_lic.c revision 1.4 
1/* $NetBSD: tegra_lic.c,v 1.4 2017/04/22 19:20:51 jmcneill Exp $ */
2
3/*-
4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
30__KERNEL_RCSID(0, "$NetBSD: tegra_lic.c,v 1.4 2017/04/22 19:20:51 jmcneill Exp $");
31
32#include <sys/param.h>
33#include <sys/bus.h>
34#include <sys/device.h>
35#include <sys/intr.h>
36#include <sys/systm.h>
37#include <sys/kernel.h>
38#include <sys/kmem.h>
39
40#include <arm/nvidia/tegra_reg.h>
41#include <arm/nvidia/tegra_var.h>
42
43#include <arm/cortex/gic_intr.h>
44
45#include <dev/fdt/fdtvar.h>
46
47#define	LIC_CPU_IER_CLR_REG	0x28
48#define	LIC_CPU_IEP_CLASS_REG	0x2c
49
50static int	tegra_lic_match(device_t, cfdata_t, void *);
51static void	tegra_lic_attach(device_t, device_t, void *);
52
53static void *	tegra_lic_establish(device_t, u_int *, int, int,
54		    int (*)(void *), void *);
55static void	tegra_lic_disestablish(device_t, void *);
56static bool	tegra_lic_intrstr(device_t, u_int *, char *, size_t);
57
58struct fdtbus_interrupt_controller_func tegra_lic_funcs = {
59	.establish = tegra_lic_establish,
60	.disestablish = tegra_lic_disestablish,
61	.intrstr = tegra_lic_intrstr
62};
63
64struct tegra_lic_softc {
65	device_t		sc_dev;
66	int			sc_phandle;
67};
68
69CFATTACH_DECL_NEW(tegra_lic, sizeof(struct tegra_lic_softc),
70	tegra_lic_match, tegra_lic_attach, NULL, NULL);
71
72static int
73tegra_lic_match(device_t parent, cfdata_t cf, void *aux)
74{
75	const char * const compatible[] = { "nvidia,tegra124-ictlr", NULL };
76	struct fdt_attach_args * const faa = aux;
77
78	return of_match_compatible(faa->faa_phandle, compatible);
79}
80
81static void
82tegra_lic_attach(device_t parent, device_t self, void *aux)
83{
84	struct tegra_lic_softc * const sc = device_private(self);
85	struct fdt_attach_args * const faa = aux;
86	bus_space_tag_t bst;
87	bus_space_handle_t bsh;
88	bus_addr_t addr;
89	bus_size_t size;
90	int error, index;
91
92	sc->sc_dev = self;
93	sc->sc_phandle = faa->faa_phandle;
94
95	error = fdtbus_register_interrupt_controller(self, faa->faa_phandle,
96	    &tegra_lic_funcs);
97	if (error) {
98		aprint_error(": couldn't register with fdtbus: %d\n", error);
99		return;
100	}
101
102	aprint_naive("\n");
103	aprint_normal(": LIC\n");
104
105	bst = faa->faa_bst;
106	for (index = 0; ; index++) {
107		error = fdtbus_get_reg(faa->faa_phandle, index, &addr, &size);
108		if (error != 0)
109			break;
110		error = bus_space_map(bst, addr, size, 0, &bsh);
111		if (error) {
112			aprint_error_dev(self, "can't map IC#%d: %d\n",
113			    index, error);
114			continue;
115		}
116
117		/* Clear interrupt enable for CPU */
118		bus_space_write_4(bst, bsh, LIC_CPU_IER_CLR_REG, 0xffffffff);
119
120		/* Route to IRQ */
121		bus_space_write_4(bst, bsh, LIC_CPU_IEP_CLASS_REG, 0);
122
123		bus_space_unmap(bst, bsh, size);
124	}
125}
126
127static void *
128tegra_lic_establish(device_t dev, u_int *specifier, int ipl, int flags,
129    int (*func)(void *), void *arg)
130{
131	int iflags = (flags & FDT_INTR_MPSAFE) ? IST_MPSAFE : 0;
132
133	/* 1st cell is the interrupt type; 0 is SPI, 1 is PPI */
134	/* 2nd cell is the interrupt number */
135	/* 3rd cell is flags */
136
137	const u_int type = be32toh(specifier[0]);
138	const u_int intr = be32toh(specifier[1]);
139	const u_int irq = type == 0 ? IRQ_SPI(intr) : IRQ_PPI(intr);
140	const u_int trig = be32toh(specifier[2]) & 0xf;
141	const u_int level = (trig & 0x3) ? IST_EDGE : IST_LEVEL;
142
143	return intr_establish(irq, ipl, level | iflags, func, arg);
144}
145
146static void
147tegra_lic_disestablish(device_t dev, void *ih)
148{
149	intr_disestablish(ih);
150}
151
152static bool
153tegra_lic_intrstr(device_t dev, u_int *specifier, char *buf,
154    size_t buflen)
155{
156	/* 1st cell is the interrupt type; 0 is SPI, 1 is PPI */
157	/* 2nd cell is the interrupt number */
158	/* 3rd cell is flags */
159
160	const u_int type = be32toh(specifier[0]);
161	const u_int intr = be32toh(specifier[1]);
162	const u_int irq = type == 0 ? IRQ_SPI(intr) : IRQ_PPI(intr);
163
164	snprintf(buf, buflen, "irq %d", irq);
165
166	return true;
167}
168