tegra_lic.c revision 1.8 
1/* $NetBSD: tegra_lic.c,v 1.8 2021/01/27 03:10:19 thorpej Exp $ */
2
3/*-
4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
30__KERNEL_RCSID(0, "$NetBSD: tegra_lic.c,v 1.8 2021/01/27 03:10:19 thorpej Exp $");
31
32#include <sys/param.h>
33#include <sys/bus.h>
34#include <sys/device.h>
35#include <sys/intr.h>
36#include <sys/systm.h>
37#include <sys/kernel.h>
38#include <sys/kmem.h>
39
40#include <arm/nvidia/tegra_reg.h>
41#include <arm/nvidia/tegra_var.h>
42
43#include <arm/cortex/gic_intr.h>
44
45#include <dev/fdt/fdtvar.h>
46
47#define	LIC_CPU_IER_CLR_REG	0x28
48#define	LIC_CPU_IEP_CLASS_REG	0x2c
49
50static int	tegra_lic_match(device_t, cfdata_t, void *);
51static void	tegra_lic_attach(device_t, device_t, void *);
52
53static void *	tegra_lic_establish(device_t, u_int *, int, int,
54		    int (*)(void *), void *, const char *);
55static void	tegra_lic_disestablish(device_t, void *);
56static bool	tegra_lic_intrstr(device_t, u_int *, char *, size_t);
57
58struct fdtbus_interrupt_controller_func tegra_lic_funcs = {
59	.establish = tegra_lic_establish,
60	.disestablish = tegra_lic_disestablish,
61	.intrstr = tegra_lic_intrstr
62};
63
64struct tegra_lic_softc {
65	device_t		sc_dev;
66	int			sc_phandle;
67};
68
69CFATTACH_DECL_NEW(tegra_lic, sizeof(struct tegra_lic_softc),
70	tegra_lic_match, tegra_lic_attach, NULL, NULL);
71
72static const struct device_compatible_entry compat_data[] = {
73	{ .compat = "nvidia,tegra210-ictlr" },
74	{ .compat = "nvidia,tegra124-ictlr" },
75	DEVICE_COMPAT_EOL
76};
77
78static int
79tegra_lic_match(device_t parent, cfdata_t cf, void *aux)
80{
81	struct fdt_attach_args * const faa = aux;
82
83	return of_compatible_match(faa->faa_phandle, compat_data);
84}
85
86static void
87tegra_lic_attach(device_t parent, device_t self, void *aux)
88{
89	struct tegra_lic_softc * const sc = device_private(self);
90	struct fdt_attach_args * const faa = aux;
91	bus_space_tag_t bst;
92	bus_space_handle_t bsh;
93	bus_addr_t addr;
94	bus_size_t size;
95	int error, index;
96
97	sc->sc_dev = self;
98	sc->sc_phandle = faa->faa_phandle;
99
100	error = fdtbus_register_interrupt_controller(self, faa->faa_phandle,
101	    &tegra_lic_funcs);
102	if (error) {
103		aprint_error(": couldn't register with fdtbus: %d\n", error);
104		return;
105	}
106
107	aprint_naive("\n");
108	aprint_normal(": LIC\n");
109
110	bst = faa->faa_bst;
111	for (index = 0; ; index++) {
112		error = fdtbus_get_reg(faa->faa_phandle, index, &addr, &size);
113		if (error != 0)
114			break;
115		error = bus_space_map(bst, addr, size, 0, &bsh);
116		if (error) {
117			aprint_error_dev(self, "can't map IC#%d: %d\n",
118			    index, error);
119			continue;
120		}
121
122		/* Clear interrupt enable for CPU */
123		bus_space_write_4(bst, bsh, LIC_CPU_IER_CLR_REG, 0xffffffff);
124
125		/* Route to IRQ */
126		bus_space_write_4(bst, bsh, LIC_CPU_IEP_CLASS_REG, 0);
127
128		bus_space_unmap(bst, bsh, size);
129	}
130}
131
132static void *
133tegra_lic_establish(device_t dev, u_int *specifier, int ipl, int flags,
134    int (*func)(void *), void *arg, const char *xname)
135{
136	int iflags = (flags & FDT_INTR_MPSAFE) ? IST_MPSAFE : 0;
137
138	/* 1st cell is the interrupt type; 0 is SPI, 1 is PPI */
139	/* 2nd cell is the interrupt number */
140	/* 3rd cell is flags */
141
142	const u_int type = be32toh(specifier[0]);
143	const u_int intr = be32toh(specifier[1]);
144	const u_int irq = type == 0 ? IRQ_SPI(intr) : IRQ_PPI(intr);
145	const u_int trig = be32toh(specifier[2]) & 0xf;
146	const u_int level = (trig & FDT_INTR_TYPE_DOUBLE_EDGE)
147	    ? IST_EDGE : IST_LEVEL;
148
149	return intr_establish_xname(irq, ipl, level | iflags, func, arg,
150	    xname);
151}
152
153static void
154tegra_lic_disestablish(device_t dev, void *ih)
155{
156	intr_disestablish(ih);
157}
158
159static bool
160tegra_lic_intrstr(device_t dev, u_int *specifier, char *buf,
161    size_t buflen)
162{
163	/* 1st cell is the interrupt type; 0 is SPI, 1 is PPI */
164	/* 2nd cell is the interrupt number */
165	/* 3rd cell is flags */
166
167	const u_int type = be32toh(specifier[0]);
168	const u_int intr = be32toh(specifier[1]);
169	const u_int irq = type == 0 ? IRQ_SPI(intr) : IRQ_PPI(intr);
170
171	snprintf(buf, buflen, "irq %d", irq);
172
173	return true;
174}
175