tegra_pcie.c revision 1.17
1 /* $NetBSD: tegra_pcie.c,v 1.17 2017/04/16 22:38:04 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_pcie.c,v 1.17 2017/04/16 22:38:04 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/extent.h> 39 #include <sys/queue.h> 40 #include <sys/mutex.h> 41 #include <sys/kmem.h> 42 43 #include <arm/cpufunc.h> 44 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pciconf.h> 48 49 #include <arm/nvidia/tegra_reg.h> 50 #include <arm/nvidia/tegra_pciereg.h> 51 #include <arm/nvidia/tegra_var.h> 52 53 #include <dev/fdt/fdtvar.h> 54 55 /* Interrupt handle flags */ 56 #define IH_MPSAFE 0x80000000 57 58 static int tegra_pcie_match(device_t, cfdata_t, void *); 59 static void tegra_pcie_attach(device_t, device_t, void *); 60 61 #define TEGRA_PCIE_NBUS 256 62 #define TEGRA_PCIE_ECFB (1<<(12 - 8)) /* extended conf frags per bus */ 63 64 struct tegra_pcie_ih { 65 int (*ih_callback)(void *); 66 void *ih_arg; 67 int ih_ipl; 68 int ih_mpsafe; 69 TAILQ_ENTRY(tegra_pcie_ih) ih_entry; 70 }; 71 72 struct tegra_pcie_softc { 73 device_t sc_dev; 74 bus_dma_tag_t sc_dmat; 75 bus_space_tag_t sc_bst; 76 bus_space_handle_t sc_bsh_afi; 77 bus_space_handle_t sc_bsh_rpconf; 78 int sc_phandle; 79 80 struct arm32_pci_chipset sc_pc; 81 82 void *sc_ih; 83 84 kmutex_t sc_lock; 85 86 TAILQ_HEAD(, tegra_pcie_ih) sc_intrs; 87 u_int sc_intrgen; 88 89 bus_space_handle_t sc_bsh_extc[TEGRA_PCIE_NBUS-1][TEGRA_PCIE_ECFB]; 90 }; 91 92 static int tegra_pcie_intr(void *); 93 static void tegra_pcie_init(pci_chipset_tag_t, void *); 94 static void tegra_pcie_enable(struct tegra_pcie_softc *); 95 static void tegra_pcie_setup(struct tegra_pcie_softc * const); 96 static void tegra_pcie_conf_frag_map(struct tegra_pcie_softc * const, 97 uint, uint); 98 static void tegra_pcie_conf_map_bus(struct tegra_pcie_softc * const, uint); 99 static void tegra_pcie_conf_map_buses(struct tegra_pcie_softc * const); 100 101 static void tegra_pcie_attach_hook(device_t, device_t, 102 struct pcibus_attach_args *); 103 static int tegra_pcie_bus_maxdevs(void *, int); 104 static pcitag_t tegra_pcie_make_tag(void *, int, int, int); 105 static void tegra_pcie_decompose_tag(void *, pcitag_t, int *, int *, int *); 106 static pcireg_t tegra_pcie_conf_read(void *, pcitag_t, int); 107 static void tegra_pcie_conf_write(void *, pcitag_t, int, pcireg_t); 108 static int tegra_pcie_conf_hook(void *, int, int, int, pcireg_t); 109 static void tegra_pcie_conf_interrupt(void *, int, int, int, int, int *); 110 111 static int tegra_pcie_intr_map(const struct pci_attach_args *, 112 pci_intr_handle_t *); 113 static const char *tegra_pcie_intr_string(void *, pci_intr_handle_t, 114 char *, size_t); 115 const struct evcnt *tegra_pcie_intr_evcnt(void *, pci_intr_handle_t); 116 static int tegra_pcie_intr_setattr(void *, pci_intr_handle_t *, int, 117 uint64_t); 118 static void * tegra_pcie_intr_establish(void *, pci_intr_handle_t, 119 int, int (*)(void *), void *); 120 static void tegra_pcie_intr_disestablish(void *, void *); 121 122 CFATTACH_DECL_NEW(tegra_pcie, sizeof(struct tegra_pcie_softc), 123 tegra_pcie_match, tegra_pcie_attach, NULL, NULL); 124 125 static int 126 tegra_pcie_match(device_t parent, cfdata_t cf, void *aux) 127 { 128 const char * const compatible[] = { "nvidia,tegra124-pcie", NULL }; 129 struct fdt_attach_args * const faa = aux; 130 131 return of_match_compatible(faa->faa_phandle, compatible); 132 } 133 134 static void 135 tegra_pcie_attach(device_t parent, device_t self, void *aux) 136 { 137 struct tegra_pcie_softc * const sc = device_private(self); 138 struct fdt_attach_args * const faa = aux; 139 struct extent *ioext, *memext, *pmemext; 140 struct pcibus_attach_args pba; 141 bus_addr_t afi_addr, cs_addr; 142 bus_size_t afi_size, cs_size; 143 char intrstr[128]; 144 int error; 145 146 if (fdtbus_get_reg(faa->faa_phandle, 1, &afi_addr, &afi_size) != 0) { 147 aprint_error(": couldn't get afi registers\n"); 148 return; 149 } 150 #if notyet 151 if (fdtbus_get_reg(faa->faa_phandle, 2, &cs_addr, &cs_size) != 0) { 152 aprint_error(": couldn't get cs registers\n"); 153 return; 154 } 155 #else 156 cs_addr = TEGRA_PCIE_RPCONF_BASE; 157 cs_size = TEGRA_PCIE_RPCONF_SIZE; 158 #endif 159 160 sc->sc_dev = self; 161 sc->sc_dmat = faa->faa_dmat; 162 sc->sc_bst = faa->faa_bst; 163 sc->sc_phandle = faa->faa_phandle; 164 error = bus_space_map(sc->sc_bst, afi_addr, afi_size, 0, 165 &sc->sc_bsh_afi); 166 if (error) { 167 aprint_error(": couldn't map afi registers: %d\n", error); 168 return; 169 } 170 error = bus_space_map(sc->sc_bst, cs_addr, cs_size, 0, 171 &sc->sc_bsh_rpconf); 172 if (error) { 173 aprint_error(": couldn't map cs registers: %d\n", error); 174 return; 175 } 176 177 tegra_pcie_conf_map_buses(sc); 178 179 TAILQ_INIT(&sc->sc_intrs); 180 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 181 182 aprint_naive("\n"); 183 aprint_normal(": PCIE\n"); 184 185 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) { 186 aprint_error_dev(self, "failed to decode interrupt\n"); 187 return; 188 } 189 190 sc->sc_ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_VM, 191 FDT_INTR_MPSAFE, tegra_pcie_intr, sc); 192 if (sc->sc_ih == NULL) { 193 aprint_error_dev(self, "failed to establish interrupt on %s\n", 194 intrstr); 195 return; 196 } 197 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 198 199 tegra_pcie_setup(sc); 200 201 tegra_pcie_init(&sc->sc_pc, sc); 202 203 ioext = extent_create("pciio", TEGRA_PCIE_IO_BASE, 204 TEGRA_PCIE_IO_BASE + TEGRA_PCIE_IO_SIZE - 1, 205 NULL, 0, EX_NOWAIT); 206 memext = extent_create("pcimem", TEGRA_PCIE_MEM_BASE, 207 TEGRA_PCIE_MEM_BASE + TEGRA_PCIE_MEM_SIZE - 1, 208 NULL, 0, EX_NOWAIT); 209 pmemext = extent_create("pcipmem", TEGRA_PCIE_PMEM_BASE, 210 TEGRA_PCIE_PMEM_BASE + TEGRA_PCIE_PMEM_SIZE - 1, 211 NULL, 0, EX_NOWAIT); 212 213 error = pci_configure_bus(&sc->sc_pc, ioext, memext, pmemext, 0, 214 arm_dcache_align); 215 216 extent_destroy(ioext); 217 extent_destroy(memext); 218 extent_destroy(pmemext); 219 220 if (error) { 221 aprint_error_dev(self, "configuration failed (%d)\n", 222 error); 223 return; 224 } 225 226 tegra_pcie_enable(sc); 227 228 memset(&pba, 0, sizeof(pba)); 229 pba.pba_flags = PCI_FLAGS_MRL_OKAY | 230 PCI_FLAGS_MRM_OKAY | 231 PCI_FLAGS_MWI_OKAY | 232 PCI_FLAGS_MEM_OKAY | 233 PCI_FLAGS_IO_OKAY; 234 pba.pba_iot = sc->sc_bst; 235 pba.pba_memt = sc->sc_bst; 236 pba.pba_dmat = sc->sc_dmat; 237 pba.pba_pc = &sc->sc_pc; 238 pba.pba_bus = 0; 239 240 config_found_ia(self, "pcibus", &pba, pcibusprint); 241 } 242 243 static int 244 tegra_pcie_legacy_intr(struct tegra_pcie_softc *sc) 245 { 246 const uint32_t msg = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, 247 AFI_MSG_REG); 248 struct tegra_pcie_ih *pcie_ih; 249 int rv = 0; 250 251 if (msg & (AFI_MSG_INT0|AFI_MSG_INT1)) { 252 mutex_enter(&sc->sc_lock); 253 const u_int lastgen = sc->sc_intrgen; 254 TAILQ_FOREACH(pcie_ih, &sc->sc_intrs, ih_entry) { 255 int (*callback)(void *) = pcie_ih->ih_callback; 256 void *arg = pcie_ih->ih_arg; 257 const int mpsafe = pcie_ih->ih_mpsafe; 258 mutex_exit(&sc->sc_lock); 259 260 if (!mpsafe) 261 KERNEL_LOCK(1, curlwp); 262 rv += callback(arg); 263 if (!mpsafe) 264 KERNEL_UNLOCK_ONE(curlwp); 265 266 mutex_enter(&sc->sc_lock); 267 if (lastgen != sc->sc_intrgen) 268 break; 269 } 270 mutex_exit(&sc->sc_lock); 271 } else if (msg & (AFI_MSG_PM_PME0|AFI_MSG_PM_PME1)) { 272 device_printf(sc->sc_dev, "PM PME message; AFI_MSG=%08x\n", 273 msg); 274 } else { 275 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_MSG_REG, msg); 276 rv = 1; 277 } 278 279 return rv; 280 } 281 282 static int 283 tegra_pcie_intr(void *priv) 284 { 285 struct tegra_pcie_softc *sc = priv; 286 int rv; 287 288 const uint32_t code = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, 289 AFI_INTR_CODE_REG); 290 const uint32_t sig = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, 291 AFI_INTR_SIGNATURE_REG); 292 293 switch (__SHIFTOUT(code, AFI_INTR_CODE_INT_CODE)) { 294 case AFI_INTR_CODE_SM_MSG: 295 rv = tegra_pcie_legacy_intr(sc); 296 break; 297 default: 298 device_printf(sc->sc_dev, "intr: code %#x sig %#x\n", 299 code, sig); 300 rv = 1; 301 break; 302 } 303 304 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_INTR_CODE_REG, 0); 305 306 return rv; 307 } 308 309 static void 310 tegra_pcie_setup(struct tegra_pcie_softc * const sc) 311 { 312 size_t i; 313 314 /* 315 * Map PCI address spaces into ARM address space via 316 * HyperTransport-like "FPCI". 317 */ 318 static const struct { uint32_t size, base, fpci; } pcie_init_table[] = { 319 /* 320 * === BEWARE === 321 * 322 * We depend on our TEGRA_PCIE_IO window overlaping the 323 * TEGRA_PCIE_A1 window to allow us to use the same 324 * bus_space_tag for both PCI IO and Memory spaces. 325 * 326 * 0xfdfc000000-0xfdfdffffff is the FPCI/HyperTransport 327 * mapping for 0x0000000-0x1ffffff of PCI IO space. 328 */ 329 { TEGRA_PCIE_IO_SIZE >> 12, TEGRA_PCIE_IO_BASE, 330 (0xfdfc000000 + TEGRA_PCIE_IO_BASE) >> 8 | 0, }, 331 332 /* HyperTransport Technology Type 1 Address Format */ 333 { TEGRA_PCIE_CONF_SIZE >> 12, TEGRA_PCIE_CONF_BASE, 334 0xfdff000000 >> 8 | 0, }, 335 336 /* 1:1 MMIO mapping */ 337 { TEGRA_PCIE_MEM_SIZE >> 12, TEGRA_PCIE_MEM_BASE, 338 TEGRA_PCIE_MEM_BASE >> 8 | 1, }, 339 340 /* Extended HyperTransport Technology Type 1 Address Format */ 341 { TEGRA_PCIE_EXTC_SIZE >> 12, TEGRA_PCIE_EXTC_BASE, 342 0xfe10000000 >> 8 | 0, }, 343 344 /* 1:1 prefetchable MMIO mapping */ 345 { TEGRA_PCIE_PMEM_SIZE >> 12, TEGRA_PCIE_PMEM_BASE, 346 TEGRA_PCIE_PMEM_BASE >> 8 | 1, }, 347 }; 348 349 for (i = 0; i < AFI_AXI_NBAR; i++) { 350 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 351 AFI_AXI_BARi_SZ(i), 0); 352 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 353 AFI_AXI_BARi_START(i), 0); 354 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 355 AFI_FPCI_BARi(i), 0); 356 } 357 358 for (i = 0; i < __arraycount(pcie_init_table); i++) { 359 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 360 AFI_AXI_BARi_START(i), pcie_init_table[i].base); 361 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 362 AFI_FPCI_BARi(i), pcie_init_table[i].fpci); 363 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 364 AFI_AXI_BARi_SZ(i), pcie_init_table[i].size); 365 } 366 } 367 368 static void 369 tegra_pcie_enable(struct tegra_pcie_softc *sc) 370 { 371 /* disable MSI */ 372 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 373 AFI_MSI_BAR_SZ_REG, 0); 374 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 375 AFI_MSI_FPCI_BAR_ST_REG, 0); 376 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 377 AFI_MSI_AXI_BAR_ST_REG, 0); 378 379 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 380 AFI_SM_INTR_ENABLE_REG, 0xffffffff); 381 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 382 AFI_AFI_INTR_ENABLE_REG, 0); 383 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_INTR_CODE_REG, 0); 384 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 385 AFI_INTR_MASK_REG, AFI_INTR_MASK_INT); 386 } 387 388 static void 389 tegra_pcie_conf_frag_map(struct tegra_pcie_softc * const sc, uint bus, 390 uint frg) 391 { 392 bus_addr_t a; 393 394 KASSERT(bus >= 1); 395 KASSERT(bus < TEGRA_PCIE_NBUS); 396 KASSERT(frg < TEGRA_PCIE_ECFB); 397 398 if (sc->sc_bsh_extc[bus-1][frg] != 0) { 399 device_printf(sc->sc_dev, "bus %u fragment %#x already " 400 "mapped\n", bus, frg); 401 return; 402 } 403 404 a = TEGRA_PCIE_EXTC_BASE + (bus << 16) + (frg << 24); 405 if (bus_space_map(sc->sc_bst, a, 1 << 16, 0, 406 &sc->sc_bsh_extc[bus-1][frg]) != 0) 407 device_printf(sc->sc_dev, "couldn't map PCIE " 408 "configuration for bus %u fragment %#x", bus, frg); 409 } 410 411 /* map non-non-extended configuration space for full bus range */ 412 static void 413 tegra_pcie_conf_map_bus(struct tegra_pcie_softc * const sc, uint bus) 414 { 415 uint i; 416 417 for (i = 1; i < TEGRA_PCIE_ECFB; i++) { 418 tegra_pcie_conf_frag_map(sc, bus, i); 419 } 420 } 421 422 /* map non-extended configuration space for full bus range */ 423 static void 424 tegra_pcie_conf_map_buses(struct tegra_pcie_softc * const sc) 425 { 426 uint b; 427 428 for (b = 1; b < TEGRA_PCIE_NBUS; b++) { 429 tegra_pcie_conf_frag_map(sc, b, 0); 430 } 431 } 432 433 void 434 tegra_pcie_init(pci_chipset_tag_t pc, void *priv) 435 { 436 pc->pc_conf_v = priv; 437 pc->pc_attach_hook = tegra_pcie_attach_hook; 438 pc->pc_bus_maxdevs = tegra_pcie_bus_maxdevs; 439 pc->pc_make_tag = tegra_pcie_make_tag; 440 pc->pc_decompose_tag = tegra_pcie_decompose_tag; 441 pc->pc_conf_read = tegra_pcie_conf_read; 442 pc->pc_conf_write = tegra_pcie_conf_write; 443 pc->pc_conf_hook = tegra_pcie_conf_hook; 444 pc->pc_conf_interrupt = tegra_pcie_conf_interrupt; 445 446 pc->pc_intr_v = priv; 447 pc->pc_intr_map = tegra_pcie_intr_map; 448 pc->pc_intr_string = tegra_pcie_intr_string; 449 pc->pc_intr_evcnt = tegra_pcie_intr_evcnt; 450 pc->pc_intr_setattr = tegra_pcie_intr_setattr; 451 pc->pc_intr_establish = tegra_pcie_intr_establish; 452 pc->pc_intr_disestablish = tegra_pcie_intr_disestablish; 453 } 454 455 static void 456 tegra_pcie_attach_hook(device_t parent, device_t self, 457 struct pcibus_attach_args *pba) 458 { 459 const pci_chipset_tag_t pc = pba->pba_pc; 460 struct tegra_pcie_softc * const sc = pc->pc_conf_v; 461 462 if (pba->pba_bus >= 1) { 463 tegra_pcie_conf_map_bus(sc, pba->pba_bus); 464 } 465 } 466 467 static int 468 tegra_pcie_bus_maxdevs(void *v, int busno) 469 { 470 return busno == 0 ? 2 : 32; 471 } 472 473 static pcitag_t 474 tegra_pcie_make_tag(void *v, int b, int d, int f) 475 { 476 return (b << 16) | (d << 11) | (f << 8); 477 } 478 479 static void 480 tegra_pcie_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 481 { 482 if (bp) 483 *bp = (tag >> 16) & 0xff; 484 if (dp) 485 *dp = (tag >> 11) & 0x1f; 486 if (fp) 487 *fp = (tag >> 8) & 0x7; 488 } 489 490 static pcireg_t 491 tegra_pcie_conf_read(void *v, pcitag_t tag, int offset) 492 { 493 struct tegra_pcie_softc *sc = v; 494 bus_space_handle_t bsh; 495 int b, d, f; 496 u_int reg; 497 498 if ((unsigned int)offset >= PCI_EXTCONF_SIZE) 499 return (pcireg_t) -1; 500 501 tegra_pcie_decompose_tag(v, tag, &b, &d, &f); 502 503 if (b >= TEGRA_PCIE_NBUS) 504 return (pcireg_t) -1; 505 506 if (b == 0) { 507 if (d >= 2 || f != 0) 508 return (pcireg_t) -1; 509 reg = d * 0x1000 + offset; 510 bsh = sc->sc_bsh_rpconf; 511 } else { 512 reg = (d << 11) | (f << 8) | (offset & 0xff); 513 bsh = sc->sc_bsh_extc[b-1][(offset >> 8) & 0xf]; 514 if (bsh == 0) 515 return (pcireg_t) -1; 516 } 517 518 return bus_space_read_4(sc->sc_bst, bsh, reg); 519 } 520 521 static void 522 tegra_pcie_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 523 { 524 struct tegra_pcie_softc *sc = v; 525 bus_space_handle_t bsh; 526 int b, d, f; 527 u_int reg; 528 529 if ((unsigned int)offset >= PCI_EXTCONF_SIZE) 530 return; 531 532 tegra_pcie_decompose_tag(v, tag, &b, &d, &f); 533 534 if (b >= TEGRA_PCIE_NBUS) 535 return; 536 537 if (b == 0) { 538 if (d >= 2 || f != 0) 539 return; 540 reg = d * 0x1000 + offset; 541 bsh = sc->sc_bsh_rpconf; 542 } else { 543 reg = (d << 11) | (f << 8) | (offset & 0xff); 544 bsh = sc->sc_bsh_extc[b-1][(offset >> 8) & 0xf]; 545 if (bsh == 0) 546 return; 547 } 548 549 bus_space_write_4(sc->sc_bst, bsh, reg, val); 550 } 551 552 static int 553 tegra_pcie_conf_hook(void *v, int b, int d, int f, pcireg_t id) 554 { 555 return PCI_CONF_DEFAULT & ~PCI_CONF_ENABLE_BM; 556 } 557 558 static void 559 tegra_pcie_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, 560 int *ilinep) 561 { 562 *ilinep = 5; 563 } 564 565 static int 566 tegra_pcie_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ih) 567 { 568 if (pa->pa_intrpin == 0) 569 return EINVAL; 570 *ih = pa->pa_intrpin; 571 return 0; 572 } 573 574 static const char * 575 tegra_pcie_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 576 { 577 struct tegra_pcie_softc *sc = v; 578 579 if (ih == PCI_INTERRUPT_PIN_NONE) 580 return NULL; 581 582 if (!fdtbus_intr_str(sc->sc_phandle, 0, buf, len)) 583 return NULL; 584 585 return buf; 586 } 587 588 const struct evcnt * 589 tegra_pcie_intr_evcnt(void *v, pci_intr_handle_t ih) 590 { 591 return NULL; 592 } 593 594 static int 595 tegra_pcie_intr_setattr(void *v, pci_intr_handle_t *ih, int attr, uint64_t data) 596 { 597 switch (attr) { 598 case PCI_INTR_MPSAFE: 599 if (data) 600 *ih |= IH_MPSAFE; 601 else 602 *ih &= ~IH_MPSAFE; 603 return 0; 604 default: 605 return ENODEV; 606 } 607 } 608 609 static void * 610 tegra_pcie_intr_establish(void *v, pci_intr_handle_t ih, int ipl, 611 int (*callback)(void *), void *arg) 612 { 613 struct tegra_pcie_softc *sc = v; 614 struct tegra_pcie_ih *pcie_ih; 615 616 if (ih == 0) 617 return NULL; 618 619 pcie_ih = kmem_alloc(sizeof(*pcie_ih), KM_SLEEP); 620 pcie_ih->ih_callback = callback; 621 pcie_ih->ih_arg = arg; 622 pcie_ih->ih_ipl = ipl; 623 pcie_ih->ih_mpsafe = (ih & IH_MPSAFE) != 0; 624 625 mutex_enter(&sc->sc_lock); 626 TAILQ_INSERT_TAIL(&sc->sc_intrs, pcie_ih, ih_entry); 627 sc->sc_intrgen++; 628 mutex_exit(&sc->sc_lock); 629 630 return pcie_ih; 631 } 632 633 static void 634 tegra_pcie_intr_disestablish(void *v, void *vih) 635 { 636 struct tegra_pcie_softc *sc = v; 637 struct tegra_pcie_ih *pcie_ih = vih; 638 639 mutex_enter(&sc->sc_lock); 640 TAILQ_REMOVE(&sc->sc_intrs, pcie_ih, ih_entry); 641 mutex_exit(&sc->sc_lock); 642 643 kmem_free(pcie_ih, sizeof(*pcie_ih)); 644 } 645
Indexes created Thu Oct 02 10:09:58 GMT 2025