tegra_pcie.c revision 1.18
1 /* $NetBSD: tegra_pcie.c,v 1.18 2017/05/26 20:14:17 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_pcie.c,v 1.18 2017/05/26 20:14:17 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/extent.h> 39 #include <sys/queue.h> 40 #include <sys/mutex.h> 41 #include <sys/kmem.h> 42 43 #include <arm/cpufunc.h> 44 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pciconf.h> 48 49 #include <arm/nvidia/tegra_reg.h> 50 #include <arm/nvidia/tegra_pciereg.h> 51 #include <arm/nvidia/tegra_var.h> 52 53 #include <dev/fdt/fdtvar.h> 54 55 /* Interrupt handle flags */ 56 #define IH_MPSAFE 0x80000000 57 58 static int tegra_pcie_match(device_t, cfdata_t, void *); 59 static void tegra_pcie_attach(device_t, device_t, void *); 60 61 #define TEGRA_PCIE_NBUS 256 62 #define TEGRA_PCIE_ECFB (1<<(12 - 8)) /* extended conf frags per bus */ 63 64 struct tegra_pcie_ih { 65 int (*ih_callback)(void *); 66 void *ih_arg; 67 int ih_ipl; 68 int ih_mpsafe; 69 TAILQ_ENTRY(tegra_pcie_ih) ih_entry; 70 }; 71 72 struct tegra_pcie_softc { 73 device_t sc_dev; 74 bus_dma_tag_t sc_dmat; 75 bus_space_tag_t sc_bst; 76 bus_space_handle_t sc_bsh_afi; 77 bus_space_handle_t sc_bsh_rpconf; 78 int sc_phandle; 79 80 struct arm32_pci_chipset sc_pc; 81 82 void *sc_ih; 83 84 kmutex_t sc_lock; 85 86 TAILQ_HEAD(, tegra_pcie_ih) sc_intrs; 87 u_int sc_intrgen; 88 89 bus_space_handle_t sc_bsh_extc[TEGRA_PCIE_NBUS-1][TEGRA_PCIE_ECFB]; 90 }; 91 92 static int tegra_pcie_intr(void *); 93 static void tegra_pcie_init(pci_chipset_tag_t, void *); 94 static void tegra_pcie_enable(struct tegra_pcie_softc *); 95 static void tegra_pcie_setup(struct tegra_pcie_softc * const); 96 static void tegra_pcie_conf_frag_map(struct tegra_pcie_softc * const, 97 uint, uint); 98 static void tegra_pcie_conf_map_bus(struct tegra_pcie_softc * const, uint); 99 static void tegra_pcie_conf_map_buses(struct tegra_pcie_softc * const); 100 101 static void tegra_pcie_attach_hook(device_t, device_t, 102 struct pcibus_attach_args *); 103 static int tegra_pcie_bus_maxdevs(void *, int); 104 static pcitag_t tegra_pcie_make_tag(void *, int, int, int); 105 static void tegra_pcie_decompose_tag(void *, pcitag_t, int *, int *, int *); 106 static pcireg_t tegra_pcie_conf_read(void *, pcitag_t, int); 107 static void tegra_pcie_conf_write(void *, pcitag_t, int, pcireg_t); 108 static int tegra_pcie_conf_hook(void *, int, int, int, pcireg_t); 109 static void tegra_pcie_conf_interrupt(void *, int, int, int, int, int *); 110 111 static int tegra_pcie_intr_map(const struct pci_attach_args *, 112 pci_intr_handle_t *); 113 static const char *tegra_pcie_intr_string(void *, pci_intr_handle_t, 114 char *, size_t); 115 const struct evcnt *tegra_pcie_intr_evcnt(void *, pci_intr_handle_t); 116 static int tegra_pcie_intr_setattr(void *, pci_intr_handle_t *, int, 117 uint64_t); 118 static void * tegra_pcie_intr_establish(void *, pci_intr_handle_t, 119 int, int (*)(void *), void *); 120 static void tegra_pcie_intr_disestablish(void *, void *); 121 122 CFATTACH_DECL_NEW(tegra_pcie, sizeof(struct tegra_pcie_softc), 123 tegra_pcie_match, tegra_pcie_attach, NULL, NULL); 124 125 static int 126 tegra_pcie_match(device_t parent, cfdata_t cf, void *aux) 127 { 128 const char * const compatible[] = { 129 "nvidia,tegra210-pcie", 130 "nvidia,tegra124-pcie", 131 NULL 132 }; 133 struct fdt_attach_args * const faa = aux; 134 135 return of_match_compatible(faa->faa_phandle, compatible); 136 } 137 138 static void 139 tegra_pcie_attach(device_t parent, device_t self, void *aux) 140 { 141 struct tegra_pcie_softc * const sc = device_private(self); 142 struct fdt_attach_args * const faa = aux; 143 struct extent *ioext, *memext, *pmemext; 144 struct pcibus_attach_args pba; 145 bus_addr_t afi_addr, cs_addr; 146 bus_size_t afi_size, cs_size; 147 char intrstr[128]; 148 int error; 149 150 if (fdtbus_get_reg(faa->faa_phandle, 1, &afi_addr, &afi_size) != 0) { 151 aprint_error(": couldn't get afi registers\n"); 152 return; 153 } 154 #if notyet 155 if (fdtbus_get_reg(faa->faa_phandle, 2, &cs_addr, &cs_size) != 0) { 156 aprint_error(": couldn't get cs registers\n"); 157 return; 158 } 159 #else 160 cs_addr = TEGRA_PCIE_RPCONF_BASE; 161 cs_size = TEGRA_PCIE_RPCONF_SIZE; 162 #endif 163 164 sc->sc_dev = self; 165 sc->sc_dmat = faa->faa_dmat; 166 sc->sc_bst = faa->faa_bst; 167 sc->sc_phandle = faa->faa_phandle; 168 error = bus_space_map(sc->sc_bst, afi_addr, afi_size, 0, 169 &sc->sc_bsh_afi); 170 if (error) { 171 aprint_error(": couldn't map afi registers: %d\n", error); 172 return; 173 } 174 error = bus_space_map(sc->sc_bst, cs_addr, cs_size, 0, 175 &sc->sc_bsh_rpconf); 176 if (error) { 177 aprint_error(": couldn't map cs registers: %d\n", error); 178 return; 179 } 180 181 tegra_pcie_conf_map_buses(sc); 182 183 TAILQ_INIT(&sc->sc_intrs); 184 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 185 186 aprint_naive("\n"); 187 aprint_normal(": PCIE\n"); 188 189 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) { 190 aprint_error_dev(self, "failed to decode interrupt\n"); 191 return; 192 } 193 194 sc->sc_ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_VM, 195 FDT_INTR_MPSAFE, tegra_pcie_intr, sc); 196 if (sc->sc_ih == NULL) { 197 aprint_error_dev(self, "failed to establish interrupt on %s\n", 198 intrstr); 199 return; 200 } 201 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 202 203 tegra_pcie_setup(sc); 204 205 tegra_pcie_init(&sc->sc_pc, sc); 206 207 ioext = extent_create("pciio", TEGRA_PCIE_IO_BASE, 208 TEGRA_PCIE_IO_BASE + TEGRA_PCIE_IO_SIZE - 1, 209 NULL, 0, EX_NOWAIT); 210 memext = extent_create("pcimem", TEGRA_PCIE_MEM_BASE, 211 TEGRA_PCIE_MEM_BASE + TEGRA_PCIE_MEM_SIZE - 1, 212 NULL, 0, EX_NOWAIT); 213 pmemext = extent_create("pcipmem", TEGRA_PCIE_PMEM_BASE, 214 TEGRA_PCIE_PMEM_BASE + TEGRA_PCIE_PMEM_SIZE - 1, 215 NULL, 0, EX_NOWAIT); 216 217 error = pci_configure_bus(&sc->sc_pc, ioext, memext, pmemext, 0, 218 arm_dcache_align); 219 220 extent_destroy(ioext); 221 extent_destroy(memext); 222 extent_destroy(pmemext); 223 224 if (error) { 225 aprint_error_dev(self, "configuration failed (%d)\n", 226 error); 227 return; 228 } 229 230 tegra_pcie_enable(sc); 231 232 memset(&pba, 0, sizeof(pba)); 233 pba.pba_flags = PCI_FLAGS_MRL_OKAY | 234 PCI_FLAGS_MRM_OKAY | 235 PCI_FLAGS_MWI_OKAY | 236 PCI_FLAGS_MEM_OKAY | 237 PCI_FLAGS_IO_OKAY; 238 pba.pba_iot = sc->sc_bst; 239 pba.pba_memt = sc->sc_bst; 240 pba.pba_dmat = sc->sc_dmat; 241 pba.pba_pc = &sc->sc_pc; 242 pba.pba_bus = 0; 243 244 config_found_ia(self, "pcibus", &pba, pcibusprint); 245 } 246 247 static int 248 tegra_pcie_legacy_intr(struct tegra_pcie_softc *sc) 249 { 250 const uint32_t msg = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, 251 AFI_MSG_REG); 252 struct tegra_pcie_ih *pcie_ih; 253 int rv = 0; 254 255 if (msg & (AFI_MSG_INT0|AFI_MSG_INT1)) { 256 mutex_enter(&sc->sc_lock); 257 const u_int lastgen = sc->sc_intrgen; 258 TAILQ_FOREACH(pcie_ih, &sc->sc_intrs, ih_entry) { 259 int (*callback)(void *) = pcie_ih->ih_callback; 260 void *arg = pcie_ih->ih_arg; 261 const int mpsafe = pcie_ih->ih_mpsafe; 262 mutex_exit(&sc->sc_lock); 263 264 if (!mpsafe) 265 KERNEL_LOCK(1, curlwp); 266 rv += callback(arg); 267 if (!mpsafe) 268 KERNEL_UNLOCK_ONE(curlwp); 269 270 mutex_enter(&sc->sc_lock); 271 if (lastgen != sc->sc_intrgen) 272 break; 273 } 274 mutex_exit(&sc->sc_lock); 275 } else if (msg & (AFI_MSG_PM_PME0|AFI_MSG_PM_PME1)) { 276 device_printf(sc->sc_dev, "PM PME message; AFI_MSG=%08x\n", 277 msg); 278 } else { 279 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_MSG_REG, msg); 280 rv = 1; 281 } 282 283 return rv; 284 } 285 286 static int 287 tegra_pcie_intr(void *priv) 288 { 289 struct tegra_pcie_softc *sc = priv; 290 int rv; 291 292 const uint32_t code = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, 293 AFI_INTR_CODE_REG); 294 const uint32_t sig = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, 295 AFI_INTR_SIGNATURE_REG); 296 297 switch (__SHIFTOUT(code, AFI_INTR_CODE_INT_CODE)) { 298 case AFI_INTR_CODE_SM_MSG: 299 rv = tegra_pcie_legacy_intr(sc); 300 break; 301 default: 302 device_printf(sc->sc_dev, "intr: code %#x sig %#x\n", 303 code, sig); 304 rv = 1; 305 break; 306 } 307 308 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_INTR_CODE_REG, 0); 309 310 return rv; 311 } 312 313 static void 314 tegra_pcie_setup(struct tegra_pcie_softc * const sc) 315 { 316 size_t i; 317 318 /* 319 * Map PCI address spaces into ARM address space via 320 * HyperTransport-like "FPCI". 321 */ 322 static const struct { uint32_t size, base, fpci; } pcie_init_table[] = { 323 /* 324 * === BEWARE === 325 * 326 * We depend on our TEGRA_PCIE_IO window overlaping the 327 * TEGRA_PCIE_A1 window to allow us to use the same 328 * bus_space_tag for both PCI IO and Memory spaces. 329 * 330 * 0xfdfc000000-0xfdfdffffff is the FPCI/HyperTransport 331 * mapping for 0x0000000-0x1ffffff of PCI IO space. 332 */ 333 { TEGRA_PCIE_IO_SIZE >> 12, TEGRA_PCIE_IO_BASE, 334 (0xfdfc000000 + TEGRA_PCIE_IO_BASE) >> 8 | 0, }, 335 336 /* HyperTransport Technology Type 1 Address Format */ 337 { TEGRA_PCIE_CONF_SIZE >> 12, TEGRA_PCIE_CONF_BASE, 338 0xfdff000000 >> 8 | 0, }, 339 340 /* 1:1 MMIO mapping */ 341 { TEGRA_PCIE_MEM_SIZE >> 12, TEGRA_PCIE_MEM_BASE, 342 TEGRA_PCIE_MEM_BASE >> 8 | 1, }, 343 344 /* Extended HyperTransport Technology Type 1 Address Format */ 345 { TEGRA_PCIE_EXTC_SIZE >> 12, TEGRA_PCIE_EXTC_BASE, 346 0xfe10000000 >> 8 | 0, }, 347 348 /* 1:1 prefetchable MMIO mapping */ 349 { TEGRA_PCIE_PMEM_SIZE >> 12, TEGRA_PCIE_PMEM_BASE, 350 TEGRA_PCIE_PMEM_BASE >> 8 | 1, }, 351 }; 352 353 for (i = 0; i < AFI_AXI_NBAR; i++) { 354 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 355 AFI_AXI_BARi_SZ(i), 0); 356 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 357 AFI_AXI_BARi_START(i), 0); 358 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 359 AFI_FPCI_BARi(i), 0); 360 } 361 362 for (i = 0; i < __arraycount(pcie_init_table); i++) { 363 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 364 AFI_AXI_BARi_START(i), pcie_init_table[i].base); 365 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 366 AFI_FPCI_BARi(i), pcie_init_table[i].fpci); 367 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 368 AFI_AXI_BARi_SZ(i), pcie_init_table[i].size); 369 } 370 } 371 372 static void 373 tegra_pcie_enable(struct tegra_pcie_softc *sc) 374 { 375 /* disable MSI */ 376 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 377 AFI_MSI_BAR_SZ_REG, 0); 378 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 379 AFI_MSI_FPCI_BAR_ST_REG, 0); 380 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 381 AFI_MSI_AXI_BAR_ST_REG, 0); 382 383 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 384 AFI_SM_INTR_ENABLE_REG, 0xffffffff); 385 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 386 AFI_AFI_INTR_ENABLE_REG, 0); 387 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_INTR_CODE_REG, 0); 388 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 389 AFI_INTR_MASK_REG, AFI_INTR_MASK_INT); 390 } 391 392 static void 393 tegra_pcie_conf_frag_map(struct tegra_pcie_softc * const sc, uint bus, 394 uint frg) 395 { 396 bus_addr_t a; 397 398 KASSERT(bus >= 1); 399 KASSERT(bus < TEGRA_PCIE_NBUS); 400 KASSERT(frg < TEGRA_PCIE_ECFB); 401 402 if (sc->sc_bsh_extc[bus-1][frg] != 0) { 403 device_printf(sc->sc_dev, "bus %u fragment %#x already " 404 "mapped\n", bus, frg); 405 return; 406 } 407 408 a = TEGRA_PCIE_EXTC_BASE + (bus << 16) + (frg << 24); 409 if (bus_space_map(sc->sc_bst, a, 1 << 16, 0, 410 &sc->sc_bsh_extc[bus-1][frg]) != 0) 411 device_printf(sc->sc_dev, "couldn't map PCIE " 412 "configuration for bus %u fragment %#x", bus, frg); 413 } 414 415 /* map non-non-extended configuration space for full bus range */ 416 static void 417 tegra_pcie_conf_map_bus(struct tegra_pcie_softc * const sc, uint bus) 418 { 419 uint i; 420 421 for (i = 1; i < TEGRA_PCIE_ECFB; i++) { 422 tegra_pcie_conf_frag_map(sc, bus, i); 423 } 424 } 425 426 /* map non-extended configuration space for full bus range */ 427 static void 428 tegra_pcie_conf_map_buses(struct tegra_pcie_softc * const sc) 429 { 430 uint b; 431 432 for (b = 1; b < TEGRA_PCIE_NBUS; b++) { 433 tegra_pcie_conf_frag_map(sc, b, 0); 434 } 435 } 436 437 void 438 tegra_pcie_init(pci_chipset_tag_t pc, void *priv) 439 { 440 pc->pc_conf_v = priv; 441 pc->pc_attach_hook = tegra_pcie_attach_hook; 442 pc->pc_bus_maxdevs = tegra_pcie_bus_maxdevs; 443 pc->pc_make_tag = tegra_pcie_make_tag; 444 pc->pc_decompose_tag = tegra_pcie_decompose_tag; 445 pc->pc_conf_read = tegra_pcie_conf_read; 446 pc->pc_conf_write = tegra_pcie_conf_write; 447 pc->pc_conf_hook = tegra_pcie_conf_hook; 448 pc->pc_conf_interrupt = tegra_pcie_conf_interrupt; 449 450 pc->pc_intr_v = priv; 451 pc->pc_intr_map = tegra_pcie_intr_map; 452 pc->pc_intr_string = tegra_pcie_intr_string; 453 pc->pc_intr_evcnt = tegra_pcie_intr_evcnt; 454 pc->pc_intr_setattr = tegra_pcie_intr_setattr; 455 pc->pc_intr_establish = tegra_pcie_intr_establish; 456 pc->pc_intr_disestablish = tegra_pcie_intr_disestablish; 457 } 458 459 static void 460 tegra_pcie_attach_hook(device_t parent, device_t self, 461 struct pcibus_attach_args *pba) 462 { 463 const pci_chipset_tag_t pc = pba->pba_pc; 464 struct tegra_pcie_softc * const sc = pc->pc_conf_v; 465 466 if (pba->pba_bus >= 1) { 467 tegra_pcie_conf_map_bus(sc, pba->pba_bus); 468 } 469 } 470 471 static int 472 tegra_pcie_bus_maxdevs(void *v, int busno) 473 { 474 return busno == 0 ? 2 : 32; 475 } 476 477 static pcitag_t 478 tegra_pcie_make_tag(void *v, int b, int d, int f) 479 { 480 return (b << 16) | (d << 11) | (f << 8); 481 } 482 483 static void 484 tegra_pcie_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 485 { 486 if (bp) 487 *bp = (tag >> 16) & 0xff; 488 if (dp) 489 *dp = (tag >> 11) & 0x1f; 490 if (fp) 491 *fp = (tag >> 8) & 0x7; 492 } 493 494 static pcireg_t 495 tegra_pcie_conf_read(void *v, pcitag_t tag, int offset) 496 { 497 struct tegra_pcie_softc *sc = v; 498 bus_space_handle_t bsh; 499 int b, d, f; 500 u_int reg; 501 502 if ((unsigned int)offset >= PCI_EXTCONF_SIZE) 503 return (pcireg_t) -1; 504 505 tegra_pcie_decompose_tag(v, tag, &b, &d, &f); 506 507 if (b >= TEGRA_PCIE_NBUS) 508 return (pcireg_t) -1; 509 510 if (b == 0) { 511 if (d >= 2 || f != 0) 512 return (pcireg_t) -1; 513 reg = d * 0x1000 + offset; 514 bsh = sc->sc_bsh_rpconf; 515 } else { 516 reg = (d << 11) | (f << 8) | (offset & 0xff); 517 bsh = sc->sc_bsh_extc[b-1][(offset >> 8) & 0xf]; 518 if (bsh == 0) 519 return (pcireg_t) -1; 520 } 521 522 return bus_space_read_4(sc->sc_bst, bsh, reg); 523 } 524 525 static void 526 tegra_pcie_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 527 { 528 struct tegra_pcie_softc *sc = v; 529 bus_space_handle_t bsh; 530 int b, d, f; 531 u_int reg; 532 533 if ((unsigned int)offset >= PCI_EXTCONF_SIZE) 534 return; 535 536 tegra_pcie_decompose_tag(v, tag, &b, &d, &f); 537 538 if (b >= TEGRA_PCIE_NBUS) 539 return; 540 541 if (b == 0) { 542 if (d >= 2 || f != 0) 543 return; 544 reg = d * 0x1000 + offset; 545 bsh = sc->sc_bsh_rpconf; 546 } else { 547 reg = (d << 11) | (f << 8) | (offset & 0xff); 548 bsh = sc->sc_bsh_extc[b-1][(offset >> 8) & 0xf]; 549 if (bsh == 0) 550 return; 551 } 552 553 bus_space_write_4(sc->sc_bst, bsh, reg, val); 554 } 555 556 static int 557 tegra_pcie_conf_hook(void *v, int b, int d, int f, pcireg_t id) 558 { 559 return PCI_CONF_DEFAULT & ~PCI_CONF_ENABLE_BM; 560 } 561 562 static void 563 tegra_pcie_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, 564 int *ilinep) 565 { 566 *ilinep = 5; 567 } 568 569 static int 570 tegra_pcie_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ih) 571 { 572 if (pa->pa_intrpin == 0) 573 return EINVAL; 574 *ih = pa->pa_intrpin; 575 return 0; 576 } 577 578 static const char * 579 tegra_pcie_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 580 { 581 struct tegra_pcie_softc *sc = v; 582 583 if (ih == PCI_INTERRUPT_PIN_NONE) 584 return NULL; 585 586 if (!fdtbus_intr_str(sc->sc_phandle, 0, buf, len)) 587 return NULL; 588 589 return buf; 590 } 591 592 const struct evcnt * 593 tegra_pcie_intr_evcnt(void *v, pci_intr_handle_t ih) 594 { 595 return NULL; 596 } 597 598 static int 599 tegra_pcie_intr_setattr(void *v, pci_intr_handle_t *ih, int attr, uint64_t data) 600 { 601 switch (attr) { 602 case PCI_INTR_MPSAFE: 603 if (data) 604 *ih |= IH_MPSAFE; 605 else 606 *ih &= ~IH_MPSAFE; 607 return 0; 608 default: 609 return ENODEV; 610 } 611 } 612 613 static void * 614 tegra_pcie_intr_establish(void *v, pci_intr_handle_t ih, int ipl, 615 int (*callback)(void *), void *arg) 616 { 617 struct tegra_pcie_softc *sc = v; 618 struct tegra_pcie_ih *pcie_ih; 619 620 if (ih == 0) 621 return NULL; 622 623 pcie_ih = kmem_alloc(sizeof(*pcie_ih), KM_SLEEP); 624 pcie_ih->ih_callback = callback; 625 pcie_ih->ih_arg = arg; 626 pcie_ih->ih_ipl = ipl; 627 pcie_ih->ih_mpsafe = (ih & IH_MPSAFE) != 0; 628 629 mutex_enter(&sc->sc_lock); 630 TAILQ_INSERT_TAIL(&sc->sc_intrs, pcie_ih, ih_entry); 631 sc->sc_intrgen++; 632 mutex_exit(&sc->sc_lock); 633 634 return pcie_ih; 635 } 636 637 static void 638 tegra_pcie_intr_disestablish(void *v, void *vih) 639 { 640 struct tegra_pcie_softc *sc = v; 641 struct tegra_pcie_ih *pcie_ih = vih; 642 643 mutex_enter(&sc->sc_lock); 644 TAILQ_REMOVE(&sc->sc_intrs, pcie_ih, ih_entry); 645 mutex_exit(&sc->sc_lock); 646 647 kmem_free(pcie_ih, sizeof(*pcie_ih)); 648 } 649
Indexes created Thu Oct 02 01:09:59 GMT 2025