tegra_pcie.c revision 1.20
1 /* $NetBSD: tegra_pcie.c,v 1.20 2017/09/25 08:55:27 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_pcie.c,v 1.20 2017/09/25 08:55:27 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/extent.h> 39 #include <sys/queue.h> 40 #include <sys/mutex.h> 41 #include <sys/kmem.h> 42 43 #include <arm/cpufunc.h> 44 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pciconf.h> 48 49 #include <arm/nvidia/tegra_reg.h> 50 #include <arm/nvidia/tegra_pciereg.h> 51 #include <arm/nvidia/tegra_var.h> 52 53 #include <dev/fdt/fdtvar.h> 54 55 /* Interrupt handle flags */ 56 #define IH_MPSAFE 0x80000000 57 58 static int tegra_pcie_match(device_t, cfdata_t, void *); 59 static void tegra_pcie_attach(device_t, device_t, void *); 60 61 #define TEGRA_PCIE_NBUS 256 62 #define TEGRA_PCIE_ECFB (1<<(12 - 8)) /* extended conf frags per bus */ 63 64 struct tegra_pcie_ih { 65 int (*ih_callback)(void *); 66 void *ih_arg; 67 int ih_ipl; 68 int ih_mpsafe; 69 TAILQ_ENTRY(tegra_pcie_ih) ih_entry; 70 }; 71 72 struct tegra_pcie_softc { 73 device_t sc_dev; 74 bus_dma_tag_t sc_dmat; 75 bus_space_tag_t sc_bst; 76 bus_space_handle_t sc_bsh_afi; 77 bus_space_handle_t sc_bsh_rpconf; 78 int sc_phandle; 79 80 struct arm32_pci_chipset sc_pc; 81 82 void *sc_ih; 83 84 kmutex_t sc_lock; 85 86 TAILQ_HEAD(, tegra_pcie_ih) sc_intrs; 87 u_int sc_intrgen; 88 89 bus_space_handle_t sc_bsh_extc[TEGRA_PCIE_NBUS-1][TEGRA_PCIE_ECFB]; 90 }; 91 92 static int tegra_pcie_intr(void *); 93 static void tegra_pcie_init(pci_chipset_tag_t, void *); 94 static void tegra_pcie_enable(struct tegra_pcie_softc *); 95 static void tegra_pcie_enable_clocks(struct tegra_pcie_softc *); 96 static void tegra_pcie_setup(struct tegra_pcie_softc * const); 97 static void tegra_pcie_conf_frag_map(struct tegra_pcie_softc * const, 98 uint, uint); 99 static void tegra_pcie_conf_map_bus(struct tegra_pcie_softc * const, uint); 100 static void tegra_pcie_conf_map_buses(struct tegra_pcie_softc * const); 101 102 static void tegra_pcie_attach_hook(device_t, device_t, 103 struct pcibus_attach_args *); 104 static int tegra_pcie_bus_maxdevs(void *, int); 105 static pcitag_t tegra_pcie_make_tag(void *, int, int, int); 106 static void tegra_pcie_decompose_tag(void *, pcitag_t, int *, int *, int *); 107 static pcireg_t tegra_pcie_conf_read(void *, pcitag_t, int); 108 static void tegra_pcie_conf_write(void *, pcitag_t, int, pcireg_t); 109 static int tegra_pcie_conf_hook(void *, int, int, int, pcireg_t); 110 static void tegra_pcie_conf_interrupt(void *, int, int, int, int, int *); 111 112 static int tegra_pcie_intr_map(const struct pci_attach_args *, 113 pci_intr_handle_t *); 114 static const char *tegra_pcie_intr_string(void *, pci_intr_handle_t, 115 char *, size_t); 116 const struct evcnt *tegra_pcie_intr_evcnt(void *, pci_intr_handle_t); 117 static int tegra_pcie_intr_setattr(void *, pci_intr_handle_t *, int, 118 uint64_t); 119 static void * tegra_pcie_intr_establish(void *, pci_intr_handle_t, 120 int, int (*)(void *), void *); 121 static void tegra_pcie_intr_disestablish(void *, void *); 122 123 CFATTACH_DECL_NEW(tegra_pcie, sizeof(struct tegra_pcie_softc), 124 tegra_pcie_match, tegra_pcie_attach, NULL, NULL); 125 126 static int 127 tegra_pcie_match(device_t parent, cfdata_t cf, void *aux) 128 { 129 const char * const compatible[] = { 130 "nvidia,tegra210-pcie", 131 "nvidia,tegra124-pcie", 132 NULL 133 }; 134 struct fdt_attach_args * const faa = aux; 135 136 return of_match_compatible(faa->faa_phandle, compatible); 137 } 138 139 static void 140 tegra_pcie_attach(device_t parent, device_t self, void *aux) 141 { 142 struct tegra_pcie_softc * const sc = device_private(self); 143 struct fdt_attach_args * const faa = aux; 144 struct extent *ioext, *memext, *pmemext; 145 struct pcibus_attach_args pba; 146 bus_addr_t afi_addr, cs_addr; 147 bus_size_t afi_size, cs_size; 148 char intrstr[128]; 149 int error; 150 151 if (fdtbus_get_reg(faa->faa_phandle, 1, &afi_addr, &afi_size) != 0) { 152 aprint_error(": couldn't get afi registers\n"); 153 return; 154 } 155 #if notyet 156 if (fdtbus_get_reg(faa->faa_phandle, 2, &cs_addr, &cs_size) != 0) { 157 aprint_error(": couldn't get cs registers\n"); 158 return; 159 } 160 #else 161 cs_addr = TEGRA_PCIE_RPCONF_BASE; 162 cs_size = TEGRA_PCIE_RPCONF_SIZE; 163 #endif 164 165 sc->sc_dev = self; 166 sc->sc_dmat = faa->faa_dmat; 167 sc->sc_bst = faa->faa_bst; 168 sc->sc_phandle = faa->faa_phandle; 169 error = bus_space_map(sc->sc_bst, afi_addr, afi_size, 0, 170 &sc->sc_bsh_afi); 171 if (error) { 172 aprint_error(": couldn't map afi registers: %d\n", error); 173 return; 174 } 175 error = bus_space_map(sc->sc_bst, cs_addr, cs_size, 0, 176 &sc->sc_bsh_rpconf); 177 if (error) { 178 aprint_error(": couldn't map cs registers: %d\n", error); 179 return; 180 } 181 182 tegra_pcie_conf_map_buses(sc); 183 184 TAILQ_INIT(&sc->sc_intrs); 185 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 186 187 aprint_naive("\n"); 188 aprint_normal(": PCIE\n"); 189 190 tegra_pcie_enable_clocks(sc); 191 192 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) { 193 aprint_error_dev(self, "failed to decode interrupt\n"); 194 return; 195 } 196 197 sc->sc_ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_VM, 198 FDT_INTR_MPSAFE, tegra_pcie_intr, sc); 199 if (sc->sc_ih == NULL) { 200 aprint_error_dev(self, "failed to establish interrupt on %s\n", 201 intrstr); 202 return; 203 } 204 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 205 206 tegra_pcie_setup(sc); 207 208 tegra_pcie_init(&sc->sc_pc, sc); 209 210 ioext = extent_create("pciio", TEGRA_PCIE_IO_BASE, 211 TEGRA_PCIE_IO_BASE + TEGRA_PCIE_IO_SIZE - 1, 212 NULL, 0, EX_NOWAIT); 213 memext = extent_create("pcimem", TEGRA_PCIE_MEM_BASE, 214 TEGRA_PCIE_MEM_BASE + TEGRA_PCIE_MEM_SIZE - 1, 215 NULL, 0, EX_NOWAIT); 216 pmemext = extent_create("pcipmem", TEGRA_PCIE_PMEM_BASE, 217 TEGRA_PCIE_PMEM_BASE + TEGRA_PCIE_PMEM_SIZE - 1, 218 NULL, 0, EX_NOWAIT); 219 220 error = pci_configure_bus(&sc->sc_pc, ioext, memext, pmemext, 0, 221 arm_dcache_align); 222 223 extent_destroy(ioext); 224 extent_destroy(memext); 225 extent_destroy(pmemext); 226 227 if (error) { 228 aprint_error_dev(self, "configuration failed (%d)\n", 229 error); 230 return; 231 } 232 233 tegra_pcie_enable(sc); 234 235 memset(&pba, 0, sizeof(pba)); 236 pba.pba_flags = PCI_FLAGS_MRL_OKAY | 237 PCI_FLAGS_MRM_OKAY | 238 PCI_FLAGS_MWI_OKAY | 239 PCI_FLAGS_MEM_OKAY | 240 PCI_FLAGS_IO_OKAY; 241 pba.pba_iot = sc->sc_bst; 242 pba.pba_memt = sc->sc_bst; 243 pba.pba_dmat = sc->sc_dmat; 244 pba.pba_pc = &sc->sc_pc; 245 pba.pba_bus = 0; 246 247 config_found_ia(self, "pcibus", &pba, pcibusprint); 248 } 249 250 static int 251 tegra_pcie_legacy_intr(struct tegra_pcie_softc *sc) 252 { 253 const uint32_t msg = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, 254 AFI_MSG_REG); 255 struct tegra_pcie_ih *pcie_ih; 256 int rv = 0; 257 258 if (msg & (AFI_MSG_INT0|AFI_MSG_INT1)) { 259 mutex_enter(&sc->sc_lock); 260 const u_int lastgen = sc->sc_intrgen; 261 TAILQ_FOREACH(pcie_ih, &sc->sc_intrs, ih_entry) { 262 int (*callback)(void *) = pcie_ih->ih_callback; 263 void *arg = pcie_ih->ih_arg; 264 const int mpsafe = pcie_ih->ih_mpsafe; 265 mutex_exit(&sc->sc_lock); 266 267 if (!mpsafe) 268 KERNEL_LOCK(1, curlwp); 269 rv += callback(arg); 270 if (!mpsafe) 271 KERNEL_UNLOCK_ONE(curlwp); 272 273 mutex_enter(&sc->sc_lock); 274 if (lastgen != sc->sc_intrgen) 275 break; 276 } 277 mutex_exit(&sc->sc_lock); 278 } else if (msg & (AFI_MSG_PM_PME0|AFI_MSG_PM_PME1)) { 279 device_printf(sc->sc_dev, "PM PME message; AFI_MSG=%08x\n", 280 msg); 281 } else { 282 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_MSG_REG, msg); 283 rv = 1; 284 } 285 286 return rv; 287 } 288 289 static int 290 tegra_pcie_intr(void *priv) 291 { 292 struct tegra_pcie_softc *sc = priv; 293 int rv; 294 295 const uint32_t code = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, 296 AFI_INTR_CODE_REG); 297 const uint32_t sig = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, 298 AFI_INTR_SIGNATURE_REG); 299 300 switch (__SHIFTOUT(code, AFI_INTR_CODE_INT_CODE)) { 301 case AFI_INTR_CODE_SM_MSG: 302 rv = tegra_pcie_legacy_intr(sc); 303 break; 304 default: 305 device_printf(sc->sc_dev, "intr: code %#x sig %#x\n", 306 code, sig); 307 rv = 1; 308 break; 309 } 310 311 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_INTR_CODE_REG, 0); 312 313 return rv; 314 } 315 316 static void 317 tegra_pcie_enable_clocks(struct tegra_pcie_softc * const sc) 318 { 319 const char *clock_names[] = { "pex", "afi", "pll_e", "cml" }; 320 const char *reset_names[] = { "pex", "afi", "pcie_x" }; 321 struct fdtbus_reset *rst; 322 struct clk *clk; 323 int n; 324 325 for (n = 0; n < __arraycount(clock_names); n++) { 326 clk = fdtbus_clock_get(sc->sc_phandle, clock_names[n]); 327 if (clk == NULL || clk_enable(clk) != 0) 328 aprint_error_dev(sc->sc_dev, "couldn't enable clock %s\n", 329 clock_names[n]); 330 } 331 332 for (n = 0; n < __arraycount(reset_names); n++) { 333 rst = fdtbus_reset_get(sc->sc_phandle, reset_names[n]); 334 if (rst == NULL || fdtbus_reset_deassert(rst) != 0) 335 aprint_error_dev(sc->sc_dev, "couldn't de-assert reset %s\n", 336 reset_names[n]); 337 } 338 } 339 340 static void 341 tegra_pcie_setup(struct tegra_pcie_softc * const sc) 342 { 343 size_t i; 344 345 /* 346 * Map PCI address spaces into ARM address space via 347 * HyperTransport-like "FPCI". 348 */ 349 static const struct { uint32_t size, base, fpci; } pcie_init_table[] = { 350 /* 351 * === BEWARE === 352 * 353 * We depend on our TEGRA_PCIE_IO window overlaping the 354 * TEGRA_PCIE_A1 window to allow us to use the same 355 * bus_space_tag for both PCI IO and Memory spaces. 356 * 357 * 0xfdfc000000-0xfdfdffffff is the FPCI/HyperTransport 358 * mapping for 0x0000000-0x1ffffff of PCI IO space. 359 */ 360 { TEGRA_PCIE_IO_SIZE >> 12, TEGRA_PCIE_IO_BASE, 361 (0xfdfc000000 + TEGRA_PCIE_IO_BASE) >> 8 | 0, }, 362 363 /* HyperTransport Technology Type 1 Address Format */ 364 { TEGRA_PCIE_CONF_SIZE >> 12, TEGRA_PCIE_CONF_BASE, 365 0xfdff000000 >> 8 | 0, }, 366 367 /* 1:1 MMIO mapping */ 368 { TEGRA_PCIE_MEM_SIZE >> 12, TEGRA_PCIE_MEM_BASE, 369 TEGRA_PCIE_MEM_BASE >> 8 | 1, }, 370 371 /* Extended HyperTransport Technology Type 1 Address Format */ 372 { TEGRA_PCIE_EXTC_SIZE >> 12, TEGRA_PCIE_EXTC_BASE, 373 0xfe10000000 >> 8 | 0, }, 374 375 /* 1:1 prefetchable MMIO mapping */ 376 { TEGRA_PCIE_PMEM_SIZE >> 12, TEGRA_PCIE_PMEM_BASE, 377 TEGRA_PCIE_PMEM_BASE >> 8 | 1, }, 378 }; 379 380 for (i = 0; i < AFI_AXI_NBAR; i++) { 381 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 382 AFI_AXI_BARi_SZ(i), 0); 383 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 384 AFI_AXI_BARi_START(i), 0); 385 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 386 AFI_FPCI_BARi(i), 0); 387 } 388 389 for (i = 0; i < __arraycount(pcie_init_table); i++) { 390 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 391 AFI_AXI_BARi_START(i), pcie_init_table[i].base); 392 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 393 AFI_FPCI_BARi(i), pcie_init_table[i].fpci); 394 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 395 AFI_AXI_BARi_SZ(i), pcie_init_table[i].size); 396 } 397 } 398 399 static void 400 tegra_pcie_enable(struct tegra_pcie_softc *sc) 401 { 402 /* disable MSI */ 403 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 404 AFI_MSI_BAR_SZ_REG, 0); 405 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 406 AFI_MSI_FPCI_BAR_ST_REG, 0); 407 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 408 AFI_MSI_AXI_BAR_ST_REG, 0); 409 410 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 411 AFI_SM_INTR_ENABLE_REG, 0xffffffff); 412 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 413 AFI_AFI_INTR_ENABLE_REG, 0); 414 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_INTR_CODE_REG, 0); 415 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 416 AFI_INTR_MASK_REG, AFI_INTR_MASK_INT); 417 } 418 419 static void 420 tegra_pcie_conf_frag_map(struct tegra_pcie_softc * const sc, uint bus, 421 uint frg) 422 { 423 bus_addr_t a; 424 425 KASSERT(bus >= 1); 426 KASSERT(bus < TEGRA_PCIE_NBUS); 427 KASSERT(frg < TEGRA_PCIE_ECFB); 428 429 if (sc->sc_bsh_extc[bus-1][frg] != 0) { 430 device_printf(sc->sc_dev, "bus %u fragment %#x already " 431 "mapped\n", bus, frg); 432 return; 433 } 434 435 a = TEGRA_PCIE_EXTC_BASE + (bus << 16) + (frg << 24); 436 if (bus_space_map(sc->sc_bst, a, 1 << 16, 0, 437 &sc->sc_bsh_extc[bus-1][frg]) != 0) 438 device_printf(sc->sc_dev, "couldn't map PCIE " 439 "configuration for bus %u fragment %#x", bus, frg); 440 } 441 442 /* map non-non-extended configuration space for full bus range */ 443 static void 444 tegra_pcie_conf_map_bus(struct tegra_pcie_softc * const sc, uint bus) 445 { 446 uint i; 447 448 for (i = 1; i < TEGRA_PCIE_ECFB; i++) { 449 tegra_pcie_conf_frag_map(sc, bus, i); 450 } 451 } 452 453 /* map non-extended configuration space for full bus range */ 454 static void 455 tegra_pcie_conf_map_buses(struct tegra_pcie_softc * const sc) 456 { 457 uint b; 458 459 for (b = 1; b < TEGRA_PCIE_NBUS; b++) { 460 tegra_pcie_conf_frag_map(sc, b, 0); 461 } 462 } 463 464 void 465 tegra_pcie_init(pci_chipset_tag_t pc, void *priv) 466 { 467 pc->pc_conf_v = priv; 468 pc->pc_attach_hook = tegra_pcie_attach_hook; 469 pc->pc_bus_maxdevs = tegra_pcie_bus_maxdevs; 470 pc->pc_make_tag = tegra_pcie_make_tag; 471 pc->pc_decompose_tag = tegra_pcie_decompose_tag; 472 pc->pc_conf_read = tegra_pcie_conf_read; 473 pc->pc_conf_write = tegra_pcie_conf_write; 474 pc->pc_conf_hook = tegra_pcie_conf_hook; 475 pc->pc_conf_interrupt = tegra_pcie_conf_interrupt; 476 477 pc->pc_intr_v = priv; 478 pc->pc_intr_map = tegra_pcie_intr_map; 479 pc->pc_intr_string = tegra_pcie_intr_string; 480 pc->pc_intr_evcnt = tegra_pcie_intr_evcnt; 481 pc->pc_intr_setattr = tegra_pcie_intr_setattr; 482 pc->pc_intr_establish = tegra_pcie_intr_establish; 483 pc->pc_intr_disestablish = tegra_pcie_intr_disestablish; 484 } 485 486 static void 487 tegra_pcie_attach_hook(device_t parent, device_t self, 488 struct pcibus_attach_args *pba) 489 { 490 const pci_chipset_tag_t pc = pba->pba_pc; 491 struct tegra_pcie_softc * const sc = pc->pc_conf_v; 492 493 if (pba->pba_bus >= 1) { 494 tegra_pcie_conf_map_bus(sc, pba->pba_bus); 495 } 496 } 497 498 static int 499 tegra_pcie_bus_maxdevs(void *v, int busno) 500 { 501 return busno == 0 ? 2 : 32; 502 } 503 504 static pcitag_t 505 tegra_pcie_make_tag(void *v, int b, int d, int f) 506 { 507 return (b << 16) | (d << 11) | (f << 8); 508 } 509 510 static void 511 tegra_pcie_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 512 { 513 if (bp) 514 *bp = (tag >> 16) & 0xff; 515 if (dp) 516 *dp = (tag >> 11) & 0x1f; 517 if (fp) 518 *fp = (tag >> 8) & 0x7; 519 } 520 521 static pcireg_t 522 tegra_pcie_conf_read(void *v, pcitag_t tag, int offset) 523 { 524 struct tegra_pcie_softc *sc = v; 525 bus_space_handle_t bsh; 526 int b, d, f; 527 u_int reg; 528 529 if ((unsigned int)offset >= PCI_EXTCONF_SIZE) 530 return (pcireg_t) -1; 531 532 tegra_pcie_decompose_tag(v, tag, &b, &d, &f); 533 534 if (b >= TEGRA_PCIE_NBUS) 535 return (pcireg_t) -1; 536 537 if (b == 0) { 538 if (d >= 2 || f != 0) 539 return (pcireg_t) -1; 540 reg = d * 0x1000 + offset; 541 bsh = sc->sc_bsh_rpconf; 542 } else { 543 reg = (d << 11) | (f << 8) | (offset & 0xff); 544 bsh = sc->sc_bsh_extc[b-1][(offset >> 8) & 0xf]; 545 if (bsh == 0) 546 return (pcireg_t) -1; 547 } 548 549 return bus_space_read_4(sc->sc_bst, bsh, reg); 550 } 551 552 static void 553 tegra_pcie_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 554 { 555 struct tegra_pcie_softc *sc = v; 556 bus_space_handle_t bsh; 557 int b, d, f; 558 u_int reg; 559 560 if ((unsigned int)offset >= PCI_EXTCONF_SIZE) 561 return; 562 563 tegra_pcie_decompose_tag(v, tag, &b, &d, &f); 564 565 if (b >= TEGRA_PCIE_NBUS) 566 return; 567 568 if (b == 0) { 569 if (d >= 2 || f != 0) 570 return; 571 reg = d * 0x1000 + offset; 572 bsh = sc->sc_bsh_rpconf; 573 } else { 574 reg = (d << 11) | (f << 8) | (offset & 0xff); 575 bsh = sc->sc_bsh_extc[b-1][(offset >> 8) & 0xf]; 576 if (bsh == 0) 577 return; 578 } 579 580 bus_space_write_4(sc->sc_bst, bsh, reg, val); 581 } 582 583 static int 584 tegra_pcie_conf_hook(void *v, int b, int d, int f, pcireg_t id) 585 { 586 return PCI_CONF_DEFAULT & ~PCI_CONF_ENABLE_BM; 587 } 588 589 static void 590 tegra_pcie_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, 591 int *ilinep) 592 { 593 *ilinep = 5; 594 } 595 596 static int 597 tegra_pcie_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ih) 598 { 599 if (pa->pa_intrpin == 0) 600 return EINVAL; 601 *ih = pa->pa_intrpin; 602 return 0; 603 } 604 605 static const char * 606 tegra_pcie_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 607 { 608 struct tegra_pcie_softc *sc = v; 609 610 if (ih == PCI_INTERRUPT_PIN_NONE) 611 return NULL; 612 613 if (!fdtbus_intr_str(sc->sc_phandle, 0, buf, len)) 614 return NULL; 615 616 return buf; 617 } 618 619 const struct evcnt * 620 tegra_pcie_intr_evcnt(void *v, pci_intr_handle_t ih) 621 { 622 return NULL; 623 } 624 625 static int 626 tegra_pcie_intr_setattr(void *v, pci_intr_handle_t *ih, int attr, uint64_t data) 627 { 628 switch (attr) { 629 case PCI_INTR_MPSAFE: 630 if (data) 631 *ih |= IH_MPSAFE; 632 else 633 *ih &= ~IH_MPSAFE; 634 return 0; 635 default: 636 return ENODEV; 637 } 638 } 639 640 static void * 641 tegra_pcie_intr_establish(void *v, pci_intr_handle_t ih, int ipl, 642 int (*callback)(void *), void *arg) 643 { 644 struct tegra_pcie_softc *sc = v; 645 struct tegra_pcie_ih *pcie_ih; 646 647 if (ih == 0) 648 return NULL; 649 650 pcie_ih = kmem_alloc(sizeof(*pcie_ih), KM_SLEEP); 651 pcie_ih->ih_callback = callback; 652 pcie_ih->ih_arg = arg; 653 pcie_ih->ih_ipl = ipl; 654 pcie_ih->ih_mpsafe = (ih & IH_MPSAFE) != 0; 655 656 mutex_enter(&sc->sc_lock); 657 TAILQ_INSERT_TAIL(&sc->sc_intrs, pcie_ih, ih_entry); 658 sc->sc_intrgen++; 659 mutex_exit(&sc->sc_lock); 660 661 return pcie_ih; 662 } 663 664 static void 665 tegra_pcie_intr_disestablish(void *v, void *vih) 666 { 667 struct tegra_pcie_softc *sc = v; 668 struct tegra_pcie_ih *pcie_ih = vih; 669 670 mutex_enter(&sc->sc_lock); 671 TAILQ_REMOVE(&sc->sc_intrs, pcie_ih, ih_entry); 672 mutex_exit(&sc->sc_lock); 673 674 kmem_free(pcie_ih, sizeof(*pcie_ih)); 675 } 676
Indexes created Thu Oct 02 07:10:07 GMT 2025