tegra_pcie.c revision 1.22
1 /* $NetBSD: tegra_pcie.c,v 1.22 2017/09/27 10:19:13 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_pcie.c,v 1.22 2017/09/27 10:19:13 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/extent.h> 39 #include <sys/queue.h> 40 #include <sys/mutex.h> 41 #include <sys/kmem.h> 42 43 #include <arm/cpufunc.h> 44 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pciconf.h> 48 49 #include <arm/nvidia/tegra_reg.h> 50 #include <arm/nvidia/tegra_pciereg.h> 51 #include <arm/nvidia/tegra_pmcreg.h> 52 #include <arm/nvidia/tegra_var.h> 53 54 #include <dev/fdt/fdtvar.h> 55 56 /* Interrupt handle flags */ 57 #define IH_MPSAFE 0x80000000 58 59 static int tegra_pcie_match(device_t, cfdata_t, void *); 60 static void tegra_pcie_attach(device_t, device_t, void *); 61 62 #define TEGRA_PCIE_NBUS 256 63 #define TEGRA_PCIE_ECFB (1<<(12 - 8)) /* extended conf frags per bus */ 64 65 struct tegra_pcie_ih { 66 int (*ih_callback)(void *); 67 void *ih_arg; 68 int ih_ipl; 69 int ih_mpsafe; 70 TAILQ_ENTRY(tegra_pcie_ih) ih_entry; 71 }; 72 73 struct tegra_pcie_softc { 74 device_t sc_dev; 75 bus_dma_tag_t sc_dmat; 76 bus_space_tag_t sc_bst; 77 bus_space_handle_t sc_bsh_afi; 78 bus_space_handle_t sc_bsh_pads; 79 bus_space_handle_t sc_bsh_rpconf; 80 int sc_phandle; 81 82 struct arm32_pci_chipset sc_pc; 83 84 void *sc_ih; 85 86 kmutex_t sc_lock; 87 88 TAILQ_HEAD(, tegra_pcie_ih) sc_intrs; 89 u_int sc_intrgen; 90 91 bus_space_handle_t sc_bsh_extc[TEGRA_PCIE_NBUS-1][TEGRA_PCIE_ECFB]; 92 }; 93 94 static int tegra_pcie_intr(void *); 95 static void tegra_pcie_init(pci_chipset_tag_t, void *); 96 static void tegra_pcie_enable(struct tegra_pcie_softc *); 97 static void tegra_pcie_enable_ports(struct tegra_pcie_softc *); 98 static void tegra_pcie_enable_clocks(struct tegra_pcie_softc *); 99 static void tegra_pcie_setup(struct tegra_pcie_softc * const); 100 static void tegra_pcie_conf_frag_map(struct tegra_pcie_softc * const, 101 uint, uint); 102 static void tegra_pcie_conf_map_bus(struct tegra_pcie_softc * const, uint); 103 static void tegra_pcie_conf_map_buses(struct tegra_pcie_softc * const); 104 105 static void tegra_pcie_attach_hook(device_t, device_t, 106 struct pcibus_attach_args *); 107 static int tegra_pcie_bus_maxdevs(void *, int); 108 static pcitag_t tegra_pcie_make_tag(void *, int, int, int); 109 static void tegra_pcie_decompose_tag(void *, pcitag_t, int *, int *, int *); 110 static pcireg_t tegra_pcie_conf_read(void *, pcitag_t, int); 111 static void tegra_pcie_conf_write(void *, pcitag_t, int, pcireg_t); 112 static int tegra_pcie_conf_hook(void *, int, int, int, pcireg_t); 113 static void tegra_pcie_conf_interrupt(void *, int, int, int, int, int *); 114 115 static int tegra_pcie_intr_map(const struct pci_attach_args *, 116 pci_intr_handle_t *); 117 static const char *tegra_pcie_intr_string(void *, pci_intr_handle_t, 118 char *, size_t); 119 const struct evcnt *tegra_pcie_intr_evcnt(void *, pci_intr_handle_t); 120 static int tegra_pcie_intr_setattr(void *, pci_intr_handle_t *, int, 121 uint64_t); 122 static void * tegra_pcie_intr_establish(void *, pci_intr_handle_t, 123 int, int (*)(void *), void *); 124 static void tegra_pcie_intr_disestablish(void *, void *); 125 126 CFATTACH_DECL_NEW(tegra_pcie, sizeof(struct tegra_pcie_softc), 127 tegra_pcie_match, tegra_pcie_attach, NULL, NULL); 128 129 static int 130 tegra_pcie_match(device_t parent, cfdata_t cf, void *aux) 131 { 132 const char * const compatible[] = { 133 "nvidia,tegra210-pcie", 134 "nvidia,tegra124-pcie", 135 NULL 136 }; 137 struct fdt_attach_args * const faa = aux; 138 139 return of_match_compatible(faa->faa_phandle, compatible); 140 } 141 142 static void 143 tegra_pcie_attach(device_t parent, device_t self, void *aux) 144 { 145 struct tegra_pcie_softc * const sc = device_private(self); 146 struct fdt_attach_args * const faa = aux; 147 struct extent *ioext, *memext, *pmemext; 148 struct pcibus_attach_args pba; 149 bus_addr_t afi_addr, cs_addr, pads_addr; 150 bus_size_t afi_size, cs_size, pads_size; 151 char intrstr[128]; 152 int error; 153 154 if (fdtbus_get_reg_byname(faa->faa_phandle, "afi", &afi_addr, &afi_size) != 0) { 155 aprint_error(": couldn't get afi registers\n"); 156 return; 157 } 158 if (fdtbus_get_reg_byname(faa->faa_phandle, "pads", &pads_addr, &pads_size) != 0) { 159 aprint_error(": couldn't get pads registers\n"); 160 return; 161 } 162 #if notyet 163 if (fdtbus_get_reg(faa->faa_phandle, 2, &cs_addr, &cs_size) != 0) { 164 aprint_error(": couldn't get cs registers\n"); 165 return; 166 } 167 #else 168 cs_addr = TEGRA_PCIE_RPCONF_BASE; 169 cs_size = TEGRA_PCIE_RPCONF_SIZE; 170 #endif 171 172 sc->sc_dev = self; 173 sc->sc_dmat = faa->faa_dmat; 174 sc->sc_bst = faa->faa_bst; 175 sc->sc_phandle = faa->faa_phandle; 176 error = bus_space_map(sc->sc_bst, afi_addr, afi_size, 0, 177 &sc->sc_bsh_afi); 178 if (error) { 179 aprint_error(": couldn't map afi registers: %d\n", error); 180 return; 181 } 182 error = bus_space_map(sc->sc_bst, pads_addr, pads_size, 0, 183 &sc->sc_bsh_pads); 184 if (error) { 185 aprint_error(": couldn't map afi registers: %d\n", error); 186 return; 187 } 188 error = bus_space_map(sc->sc_bst, cs_addr, cs_size, 0, 189 &sc->sc_bsh_rpconf); 190 if (error) { 191 aprint_error(": couldn't map cs registers: %d\n", error); 192 return; 193 } 194 195 tegra_pcie_conf_map_buses(sc); 196 197 TAILQ_INIT(&sc->sc_intrs); 198 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 199 200 aprint_naive("\n"); 201 aprint_normal(": PCIE\n"); 202 203 tegra_pmc_power(PMC_PARTID_PCX, true); 204 tegra_pmc_remove_clamping(PMC_PARTID_PCX); 205 206 tegra_pcie_enable_clocks(sc); 207 208 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) { 209 aprint_error_dev(self, "failed to decode interrupt\n"); 210 return; 211 } 212 213 sc->sc_ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_VM, 214 FDT_INTR_MPSAFE, tegra_pcie_intr, sc); 215 if (sc->sc_ih == NULL) { 216 aprint_error_dev(self, "failed to establish interrupt on %s\n", 217 intrstr); 218 return; 219 } 220 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 221 222 tegra_pcie_setup(sc); 223 224 tegra_pcie_init(&sc->sc_pc, sc); 225 226 ioext = extent_create("pciio", TEGRA_PCIE_IO_BASE, 227 TEGRA_PCIE_IO_BASE + TEGRA_PCIE_IO_SIZE - 1, 228 NULL, 0, EX_NOWAIT); 229 memext = extent_create("pcimem", TEGRA_PCIE_MEM_BASE, 230 TEGRA_PCIE_MEM_BASE + TEGRA_PCIE_MEM_SIZE - 1, 231 NULL, 0, EX_NOWAIT); 232 pmemext = extent_create("pcipmem", TEGRA_PCIE_PMEM_BASE, 233 TEGRA_PCIE_PMEM_BASE + TEGRA_PCIE_PMEM_SIZE - 1, 234 NULL, 0, EX_NOWAIT); 235 236 error = pci_configure_bus(&sc->sc_pc, ioext, memext, pmemext, 0, 237 arm_dcache_align); 238 239 extent_destroy(ioext); 240 extent_destroy(memext); 241 extent_destroy(pmemext); 242 243 if (error) { 244 aprint_error_dev(self, "configuration failed (%d)\n", 245 error); 246 return; 247 } 248 249 tegra_pcie_enable(sc); 250 251 tegra_pcie_enable_ports(sc); 252 253 memset(&pba, 0, sizeof(pba)); 254 pba.pba_flags = PCI_FLAGS_MRL_OKAY | 255 PCI_FLAGS_MRM_OKAY | 256 PCI_FLAGS_MWI_OKAY | 257 PCI_FLAGS_MEM_OKAY | 258 PCI_FLAGS_IO_OKAY; 259 pba.pba_iot = sc->sc_bst; 260 pba.pba_memt = sc->sc_bst; 261 pba.pba_dmat = sc->sc_dmat; 262 pba.pba_pc = &sc->sc_pc; 263 pba.pba_bus = 0; 264 265 config_found_ia(self, "pcibus", &pba, pcibusprint); 266 } 267 268 static int 269 tegra_pcie_legacy_intr(struct tegra_pcie_softc *sc) 270 { 271 const uint32_t msg = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, 272 AFI_MSG_REG); 273 struct tegra_pcie_ih *pcie_ih; 274 int rv = 0; 275 276 if (msg & (AFI_MSG_INT0|AFI_MSG_INT1)) { 277 mutex_enter(&sc->sc_lock); 278 const u_int lastgen = sc->sc_intrgen; 279 TAILQ_FOREACH(pcie_ih, &sc->sc_intrs, ih_entry) { 280 int (*callback)(void *) = pcie_ih->ih_callback; 281 void *arg = pcie_ih->ih_arg; 282 const int mpsafe = pcie_ih->ih_mpsafe; 283 mutex_exit(&sc->sc_lock); 284 285 if (!mpsafe) 286 KERNEL_LOCK(1, curlwp); 287 rv += callback(arg); 288 if (!mpsafe) 289 KERNEL_UNLOCK_ONE(curlwp); 290 291 mutex_enter(&sc->sc_lock); 292 if (lastgen != sc->sc_intrgen) 293 break; 294 } 295 mutex_exit(&sc->sc_lock); 296 } else if (msg & (AFI_MSG_PM_PME0|AFI_MSG_PM_PME1)) { 297 device_printf(sc->sc_dev, "PM PME message; AFI_MSG=%08x\n", 298 msg); 299 } else { 300 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_MSG_REG, msg); 301 rv = 1; 302 } 303 304 return rv; 305 } 306 307 static int 308 tegra_pcie_intr(void *priv) 309 { 310 struct tegra_pcie_softc *sc = priv; 311 int rv; 312 313 const uint32_t code = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, 314 AFI_INTR_CODE_REG); 315 const uint32_t sig = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, 316 AFI_INTR_SIGNATURE_REG); 317 318 switch (__SHIFTOUT(code, AFI_INTR_CODE_INT_CODE)) { 319 case AFI_INTR_CODE_SM_MSG: 320 rv = tegra_pcie_legacy_intr(sc); 321 break; 322 default: 323 device_printf(sc->sc_dev, "intr: code %#x sig %#x\n", 324 code, sig); 325 rv = 1; 326 break; 327 } 328 329 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_INTR_CODE_REG, 0); 330 331 return rv; 332 } 333 334 static void 335 tegra_pcie_enable_clocks(struct tegra_pcie_softc * const sc) 336 { 337 const char *clock_names[] = { "pex", "afi", "pll_e", "cml" }; 338 const char *reset_names[] = { "pex", "afi", "pcie_x" }; 339 struct fdtbus_reset *rst; 340 struct clk *clk; 341 int n; 342 343 for (n = 0; n < __arraycount(clock_names); n++) { 344 clk = fdtbus_clock_get(sc->sc_phandle, clock_names[n]); 345 if (clk == NULL || clk_enable(clk) != 0) 346 aprint_error_dev(sc->sc_dev, "couldn't enable clock %s\n", 347 clock_names[n]); 348 } 349 350 for (n = 0; n < __arraycount(reset_names); n++) { 351 rst = fdtbus_reset_get(sc->sc_phandle, reset_names[n]); 352 if (rst == NULL || fdtbus_reset_deassert(rst) != 0) 353 aprint_error_dev(sc->sc_dev, "couldn't de-assert reset %s\n", 354 reset_names[n]); 355 } 356 } 357 358 static void 359 tegra_pcie_reset_port(struct tegra_pcie_softc * const sc, int index) 360 { 361 uint32_t val; 362 363 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index)); 364 val &= ~AFI_PEXn_CTRL_RST_L; 365 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index), val); 366 367 delay(2000); 368 369 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index)); 370 val |= AFI_PEXn_CTRL_RST_L; 371 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index), val); 372 } 373 374 static void 375 tegra_pcie_enable_ports(struct tegra_pcie_softc * const sc) 376 { 377 struct fdtbus_phy *phy; 378 const u_int *data; 379 int child, len, n; 380 uint32_t val; 381 382 for (child = OF_child(sc->sc_phandle); child; child = OF_peer(child)) { 383 if (!fdtbus_status_okay(child)) 384 continue; 385 386 /* Enable PHYs */ 387 for (n = 0; (phy = fdtbus_phy_get_index(child, n)) != NULL; n++) 388 if (fdtbus_phy_enable(phy, true) != 0) 389 aprint_error_dev(sc->sc_dev, "couldn't enable %s phy #%d\n", 390 fdtbus_get_string(child, "name"), n); 391 392 data = fdtbus_get_prop(child, "reg", &len); 393 if (data == NULL || len < 4) 394 continue; 395 const u_int index = ((be32toh(data[0]) >> 11) & 0x1f) - 1; 396 397 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index)); 398 val |= AFI_PEXn_CTRL_CLKREQ_EN; 399 val |= AFI_PEXn_CTRL_REFCLK_EN; 400 val |= AFI_PEXn_CTRL_REFCLK_OVERRIDE_EN; 401 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index), val); 402 403 tegra_pcie_reset_port(sc, index); 404 405 } 406 } 407 408 static void 409 tegra_pcie_setup(struct tegra_pcie_softc * const sc) 410 { 411 uint32_t val, cfg, lanes; 412 int child, len; 413 const u_int *data; 414 size_t i; 415 416 /* Enable PLLE control */ 417 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PLLE_CONTROL_REG); 418 val &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL; 419 val |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN; 420 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PLLE_CONTROL_REG, val); 421 422 /* Disable PEX clock bias pad power down */ 423 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXBIAS_CTRL_REG, 0); 424 425 /* Configure PCIE mode and enable ports */ 426 cfg = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PCIE_CONFIG_REG); 427 cfg |= AFI_PCIE_CONFIG_PCIECn_DISABLE_DEVICE(0); 428 cfg |= AFI_PCIE_CONFIG_PCIECn_DISABLE_DEVICE(1); 429 cfg &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG; 430 431 lanes = 0; 432 for (child = OF_child(sc->sc_phandle); child; child = OF_peer(child)) { 433 if (!fdtbus_status_okay(child)) 434 continue; 435 data = fdtbus_get_prop(child, "reg", &len); 436 if (data == NULL || len < 4) 437 continue; 438 const u_int index = ((be32toh(data[0]) >> 11) & 0x1f) - 1; 439 if (of_getprop_uint32(child, "nvidia,num-lanes", &val) != 0) 440 continue; 441 lanes |= (val << (index << 3)); 442 cfg &= ~AFI_PCIE_CONFIG_PCIECn_DISABLE_DEVICE(index); 443 } 444 445 switch (lanes) { 446 case 0x0104: 447 aprint_normal_dev(sc->sc_dev, "lane config: x4 x1\n"); 448 cfg |= __SHIFTIN(AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_4_1, 449 AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG); 450 break; 451 case 0x0102: 452 aprint_normal_dev(sc->sc_dev, "lane config: x2 x1\n"); 453 cfg |= __SHIFTIN(AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_2_1, 454 AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG); 455 break; 456 } 457 458 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PCIE_CONFIG_REG, cfg); 459 460 /* Configure refclk pad */ 461 const char * const tegra124_compat[] = { "nvidia,tegra124-pcie", NULL }; 462 if (of_match_compatible(sc->sc_phandle, tegra124_compat)) 463 bus_space_write_4(sc->sc_bst, sc->sc_bsh_pads, PADS_REFCLK_CFG0_REG, 464 0x44ac44ac); 465 const char * const tegra210_compat[] = { "nvidia,tegra210-pcie", NULL }; 466 if (of_match_compatible(sc->sc_phandle, tegra210_compat)) 467 bus_space_write_4(sc->sc_bst, sc->sc_bsh_pads, PADS_REFCLK_CFG0_REG, 468 0x90b890b8); 469 470 /* 471 * Map PCI address spaces into ARM address space via 472 * HyperTransport-like "FPCI". 473 */ 474 static const struct { uint32_t size, base, fpci; } pcie_init_table[] = { 475 /* 476 * === BEWARE === 477 * 478 * We depend on our TEGRA_PCIE_IO window overlaping the 479 * TEGRA_PCIE_A1 window to allow us to use the same 480 * bus_space_tag for both PCI IO and Memory spaces. 481 * 482 * 0xfdfc000000-0xfdfdffffff is the FPCI/HyperTransport 483 * mapping for 0x0000000-0x1ffffff of PCI IO space. 484 */ 485 { TEGRA_PCIE_IO_SIZE >> 12, TEGRA_PCIE_IO_BASE, 486 (0xfdfc000000 + TEGRA_PCIE_IO_BASE) >> 8 | 0, }, 487 488 /* HyperTransport Technology Type 1 Address Format */ 489 { TEGRA_PCIE_CONF_SIZE >> 12, TEGRA_PCIE_CONF_BASE, 490 0xfdff000000 >> 8 | 0, }, 491 492 /* 1:1 MMIO mapping */ 493 { TEGRA_PCIE_MEM_SIZE >> 12, TEGRA_PCIE_MEM_BASE, 494 TEGRA_PCIE_MEM_BASE >> 8 | 1, }, 495 496 /* Extended HyperTransport Technology Type 1 Address Format */ 497 { TEGRA_PCIE_EXTC_SIZE >> 12, TEGRA_PCIE_EXTC_BASE, 498 0xfe10000000 >> 8 | 0, }, 499 500 /* 1:1 prefetchable MMIO mapping */ 501 { TEGRA_PCIE_PMEM_SIZE >> 12, TEGRA_PCIE_PMEM_BASE, 502 TEGRA_PCIE_PMEM_BASE >> 8 | 1, }, 503 }; 504 505 for (i = 0; i < AFI_AXI_NBAR; i++) { 506 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 507 AFI_AXI_BARi_SZ(i), 0); 508 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 509 AFI_AXI_BARi_START(i), 0); 510 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 511 AFI_FPCI_BARi(i), 0); 512 } 513 514 for (i = 0; i < __arraycount(pcie_init_table); i++) { 515 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 516 AFI_AXI_BARi_START(i), pcie_init_table[i].base); 517 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 518 AFI_FPCI_BARi(i), pcie_init_table[i].fpci); 519 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 520 AFI_AXI_BARi_SZ(i), pcie_init_table[i].size); 521 } 522 } 523 524 static void 525 tegra_pcie_enable(struct tegra_pcie_softc *sc) 526 { 527 /* disable MSI */ 528 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 529 AFI_MSI_BAR_SZ_REG, 0); 530 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 531 AFI_MSI_FPCI_BAR_ST_REG, 0); 532 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 533 AFI_MSI_AXI_BAR_ST_REG, 0); 534 535 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 536 AFI_SM_INTR_ENABLE_REG, 0xffffffff); 537 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 538 AFI_AFI_INTR_ENABLE_REG, 0); 539 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_INTR_CODE_REG, 0); 540 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 541 AFI_INTR_MASK_REG, AFI_INTR_MASK_INT); 542 } 543 544 static void 545 tegra_pcie_conf_frag_map(struct tegra_pcie_softc * const sc, uint bus, 546 uint frg) 547 { 548 bus_addr_t a; 549 550 KASSERT(bus >= 1); 551 KASSERT(bus < TEGRA_PCIE_NBUS); 552 KASSERT(frg < TEGRA_PCIE_ECFB); 553 554 if (sc->sc_bsh_extc[bus-1][frg] != 0) { 555 device_printf(sc->sc_dev, "bus %u fragment %#x already " 556 "mapped\n", bus, frg); 557 return; 558 } 559 560 a = TEGRA_PCIE_EXTC_BASE + (bus << 16) + (frg << 24); 561 if (bus_space_map(sc->sc_bst, a, 1 << 16, 0, 562 &sc->sc_bsh_extc[bus-1][frg]) != 0) 563 device_printf(sc->sc_dev, "couldn't map PCIE " 564 "configuration for bus %u fragment %#x", bus, frg); 565 } 566 567 /* map non-non-extended configuration space for full bus range */ 568 static void 569 tegra_pcie_conf_map_bus(struct tegra_pcie_softc * const sc, uint bus) 570 { 571 uint i; 572 573 for (i = 1; i < TEGRA_PCIE_ECFB; i++) { 574 tegra_pcie_conf_frag_map(sc, bus, i); 575 } 576 } 577 578 /* map non-extended configuration space for full bus range */ 579 static void 580 tegra_pcie_conf_map_buses(struct tegra_pcie_softc * const sc) 581 { 582 uint b; 583 584 for (b = 1; b < TEGRA_PCIE_NBUS; b++) { 585 tegra_pcie_conf_frag_map(sc, b, 0); 586 } 587 } 588 589 void 590 tegra_pcie_init(pci_chipset_tag_t pc, void *priv) 591 { 592 pc->pc_conf_v = priv; 593 pc->pc_attach_hook = tegra_pcie_attach_hook; 594 pc->pc_bus_maxdevs = tegra_pcie_bus_maxdevs; 595 pc->pc_make_tag = tegra_pcie_make_tag; 596 pc->pc_decompose_tag = tegra_pcie_decompose_tag; 597 pc->pc_conf_read = tegra_pcie_conf_read; 598 pc->pc_conf_write = tegra_pcie_conf_write; 599 pc->pc_conf_hook = tegra_pcie_conf_hook; 600 pc->pc_conf_interrupt = tegra_pcie_conf_interrupt; 601 602 pc->pc_intr_v = priv; 603 pc->pc_intr_map = tegra_pcie_intr_map; 604 pc->pc_intr_string = tegra_pcie_intr_string; 605 pc->pc_intr_evcnt = tegra_pcie_intr_evcnt; 606 pc->pc_intr_setattr = tegra_pcie_intr_setattr; 607 pc->pc_intr_establish = tegra_pcie_intr_establish; 608 pc->pc_intr_disestablish = tegra_pcie_intr_disestablish; 609 } 610 611 static void 612 tegra_pcie_attach_hook(device_t parent, device_t self, 613 struct pcibus_attach_args *pba) 614 { 615 const pci_chipset_tag_t pc = pba->pba_pc; 616 struct tegra_pcie_softc * const sc = pc->pc_conf_v; 617 618 if (pba->pba_bus >= 1) { 619 tegra_pcie_conf_map_bus(sc, pba->pba_bus); 620 } 621 } 622 623 static int 624 tegra_pcie_bus_maxdevs(void *v, int busno) 625 { 626 return busno == 0 ? 2 : 32; 627 } 628 629 static pcitag_t 630 tegra_pcie_make_tag(void *v, int b, int d, int f) 631 { 632 return (b << 16) | (d << 11) | (f << 8); 633 } 634 635 static void 636 tegra_pcie_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 637 { 638 if (bp) 639 *bp = (tag >> 16) & 0xff; 640 if (dp) 641 *dp = (tag >> 11) & 0x1f; 642 if (fp) 643 *fp = (tag >> 8) & 0x7; 644 } 645 646 static pcireg_t 647 tegra_pcie_conf_read(void *v, pcitag_t tag, int offset) 648 { 649 struct tegra_pcie_softc *sc = v; 650 bus_space_handle_t bsh; 651 int b, d, f; 652 u_int reg; 653 654 if ((unsigned int)offset >= PCI_EXTCONF_SIZE) 655 return (pcireg_t) -1; 656 657 tegra_pcie_decompose_tag(v, tag, &b, &d, &f); 658 659 if (b >= TEGRA_PCIE_NBUS) 660 return (pcireg_t) -1; 661 662 if (b == 0) { 663 if (d >= 2 || f != 0) 664 return (pcireg_t) -1; 665 reg = d * 0x1000 + offset; 666 bsh = sc->sc_bsh_rpconf; 667 } else { 668 reg = (d << 11) | (f << 8) | (offset & 0xff); 669 bsh = sc->sc_bsh_extc[b-1][(offset >> 8) & 0xf]; 670 if (bsh == 0) 671 return (pcireg_t) -1; 672 } 673 674 return bus_space_read_4(sc->sc_bst, bsh, reg); 675 } 676 677 static void 678 tegra_pcie_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 679 { 680 struct tegra_pcie_softc *sc = v; 681 bus_space_handle_t bsh; 682 int b, d, f; 683 u_int reg; 684 685 if ((unsigned int)offset >= PCI_EXTCONF_SIZE) 686 return; 687 688 tegra_pcie_decompose_tag(v, tag, &b, &d, &f); 689 690 if (b >= TEGRA_PCIE_NBUS) 691 return; 692 693 if (b == 0) { 694 if (d >= 2 || f != 0) 695 return; 696 reg = d * 0x1000 + offset; 697 bsh = sc->sc_bsh_rpconf; 698 } else { 699 reg = (d << 11) | (f << 8) | (offset & 0xff); 700 bsh = sc->sc_bsh_extc[b-1][(offset >> 8) & 0xf]; 701 if (bsh == 0) 702 return; 703 } 704 705 bus_space_write_4(sc->sc_bst, bsh, reg, val); 706 } 707 708 static int 709 tegra_pcie_conf_hook(void *v, int b, int d, int f, pcireg_t id) 710 { 711 return PCI_CONF_DEFAULT & ~PCI_CONF_ENABLE_BM; 712 } 713 714 static void 715 tegra_pcie_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, 716 int *ilinep) 717 { 718 *ilinep = 5; 719 } 720 721 static int 722 tegra_pcie_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ih) 723 { 724 if (pa->pa_intrpin == 0) 725 return EINVAL; 726 *ih = pa->pa_intrpin; 727 return 0; 728 } 729 730 static const char * 731 tegra_pcie_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 732 { 733 struct tegra_pcie_softc *sc = v; 734 735 if (ih == PCI_INTERRUPT_PIN_NONE) 736 return NULL; 737 738 if (!fdtbus_intr_str(sc->sc_phandle, 0, buf, len)) 739 return NULL; 740 741 return buf; 742 } 743 744 const struct evcnt * 745 tegra_pcie_intr_evcnt(void *v, pci_intr_handle_t ih) 746 { 747 return NULL; 748 } 749 750 static int 751 tegra_pcie_intr_setattr(void *v, pci_intr_handle_t *ih, int attr, uint64_t data) 752 { 753 switch (attr) { 754 case PCI_INTR_MPSAFE: 755 if (data) 756 *ih |= IH_MPSAFE; 757 else 758 *ih &= ~IH_MPSAFE; 759 return 0; 760 default: 761 return ENODEV; 762 } 763 } 764 765 static void * 766 tegra_pcie_intr_establish(void *v, pci_intr_handle_t ih, int ipl, 767 int (*callback)(void *), void *arg) 768 { 769 struct tegra_pcie_softc *sc = v; 770 struct tegra_pcie_ih *pcie_ih; 771 772 if (ih == 0) 773 return NULL; 774 775 pcie_ih = kmem_alloc(sizeof(*pcie_ih), KM_SLEEP); 776 pcie_ih->ih_callback = callback; 777 pcie_ih->ih_arg = arg; 778 pcie_ih->ih_ipl = ipl; 779 pcie_ih->ih_mpsafe = (ih & IH_MPSAFE) != 0; 780 781 mutex_enter(&sc->sc_lock); 782 TAILQ_INSERT_TAIL(&sc->sc_intrs, pcie_ih, ih_entry); 783 sc->sc_intrgen++; 784 mutex_exit(&sc->sc_lock); 785 786 return pcie_ih; 787 } 788 789 static void 790 tegra_pcie_intr_disestablish(void *v, void *vih) 791 { 792 struct tegra_pcie_softc *sc = v; 793 struct tegra_pcie_ih *pcie_ih = vih; 794 795 mutex_enter(&sc->sc_lock); 796 TAILQ_REMOVE(&sc->sc_intrs, pcie_ih, ih_entry); 797 mutex_exit(&sc->sc_lock); 798 799 kmem_free(pcie_ih, sizeof(*pcie_ih)); 800 } 801
Indexes created Thu Oct 02 10:09:58 GMT 2025