tegra_pcie.c revision 1.3
1 /* $NetBSD: tegra_pcie.c,v 1.3 2015/10/02 05:22:50 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "locators.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: tegra_pcie.c,v 1.3 2015/10/02 05:22:50 msaitoh Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/extent.h> 41 #include <sys/queue.h> 42 #include <sys/mutex.h> 43 #include <sys/kmem.h> 44 45 #include <arm/cpufunc.h> 46 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pciconf.h> 50 51 #include <arm/nvidia/tegra_reg.h> 52 #include <arm/nvidia/tegra_pciereg.h> 53 #include <arm/nvidia/tegra_var.h> 54 55 static int tegra_pcie_match(device_t, cfdata_t, void *); 56 static void tegra_pcie_attach(device_t, device_t, void *); 57 58 struct tegra_pcie_ih { 59 int (*ih_callback)(void *); 60 void *ih_arg; 61 int ih_ipl; 62 TAILQ_ENTRY(tegra_pcie_ih) ih_entry; 63 }; 64 65 struct tegra_pcie_softc { 66 device_t sc_dev; 67 bus_dma_tag_t sc_dmat; 68 bus_space_tag_t sc_bst; 69 bus_space_handle_t sc_bsh_afi; 70 bus_space_handle_t sc_bsh_a1; 71 bus_space_handle_t sc_bsh_a2; 72 int sc_intr; 73 74 struct arm32_pci_chipset sc_pc; 75 76 void *sc_ih; 77 78 kmutex_t sc_lock; 79 80 TAILQ_HEAD(, tegra_pcie_ih) sc_intrs; 81 u_int sc_intrgen; 82 }; 83 84 static int tegra_pcie_intr(void *); 85 static void tegra_pcie_init(pci_chipset_tag_t, void *); 86 static void tegra_pcie_enable(struct tegra_pcie_softc *); 87 88 static void tegra_pcie_attach_hook(device_t, device_t, 89 struct pcibus_attach_args *); 90 static int tegra_pcie_bus_maxdevs(void *, int); 91 static pcitag_t tegra_pcie_make_tag(void *, int, int, int); 92 static void tegra_pcie_decompose_tag(void *, pcitag_t, int *, int *, int *); 93 static pcireg_t tegra_pcie_conf_read(void *, pcitag_t, int); 94 static void tegra_pcie_conf_write(void *, pcitag_t, int, pcireg_t); 95 static int tegra_pcie_conf_hook(void *, int, int, int, pcireg_t); 96 static void tegra_pcie_conf_interrupt(void *, int, int, int, int, int *); 97 98 static int tegra_pcie_intr_map(const struct pci_attach_args *, 99 pci_intr_handle_t *); 100 static const char *tegra_pcie_intr_string(void *, pci_intr_handle_t, 101 char *, size_t); 102 const struct evcnt *tegra_pcie_intr_evcnt(void *, pci_intr_handle_t); 103 static void * tegra_pcie_intr_establish(void *, pci_intr_handle_t, 104 int, int (*)(void *), void *); 105 static void tegra_pcie_intr_disestablish(void *, void *); 106 107 CFATTACH_DECL_NEW(tegra_pcie, sizeof(struct tegra_pcie_softc), 108 tegra_pcie_match, tegra_pcie_attach, NULL, NULL); 109 110 static int 111 tegra_pcie_match(device_t parent, cfdata_t cf, void *aux) 112 { 113 return 1; 114 } 115 116 static void 117 tegra_pcie_attach(device_t parent, device_t self, void *aux) 118 { 119 struct tegra_pcie_softc * const sc = device_private(self); 120 struct tegraio_attach_args * const tio = aux; 121 const struct tegra_locators * const loc = &tio->tio_loc; 122 struct extent *memext, *pmemext; 123 struct pcibus_attach_args pba; 124 int error; 125 126 sc->sc_dev = self; 127 #if notyet 128 sc->sc_dmat = tio->tio_coherent_dmat; 129 #else 130 sc->sc_dmat = tio->tio_dmat; 131 #endif 132 sc->sc_bst = tio->tio_bst; 133 sc->sc_intr = loc->loc_intr; 134 if (bus_space_map(sc->sc_bst, TEGRA_PCIE_AFI_BASE, TEGRA_PCIE_AFI_SIZE, 135 0, &sc->sc_bsh_afi) != 0) 136 panic("couldn't map PCIE AFI"); 137 if (bus_space_map(sc->sc_bst, TEGRA_PCIE_A1_BASE, TEGRA_PCIE_A1_SIZE, 138 0, &sc->sc_bsh_a1) != 0) 139 panic("couldn't map PCIE A1"); 140 if (bus_space_map(sc->sc_bst, TEGRA_PCIE_A2_BASE, TEGRA_PCIE_A2_SIZE, 141 0, &sc->sc_bsh_a2) != 0) 142 panic("couldn't map PCIE A2"); 143 144 TAILQ_INIT(&sc->sc_intrs); 145 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 146 147 aprint_naive("\n"); 148 aprint_normal(": PCIE\n"); 149 150 sc->sc_ih = intr_establish(loc->loc_intr, IPL_VM, IST_LEVEL, 151 tegra_pcie_intr, sc); 152 if (sc->sc_ih == NULL) { 153 aprint_error_dev(self, "failed to establish interrupt %d\n", 154 loc->loc_intr); 155 return; 156 } 157 aprint_normal_dev(self, "interrupting on irq %d\n", loc->loc_intr); 158 159 tegra_pcie_init(&sc->sc_pc, sc); 160 161 memext = extent_create("pcimem", TEGRA_PCIE_MEM_BASE, 162 TEGRA_PCIE_MEM_BASE + TEGRA_PCIE_MEM_SIZE - 1, 163 NULL, 0, EX_NOWAIT); 164 pmemext = extent_create("pcipmem", TEGRA_PCIE_PMEM_BASE, 165 TEGRA_PCIE_PMEM_BASE + TEGRA_PCIE_PMEM_SIZE - 1, 166 NULL, 0, EX_NOWAIT); 167 168 error = pci_configure_bus(&sc->sc_pc, NULL, memext, pmemext, 0, 169 arm_dcache_align); 170 171 extent_destroy(memext); 172 extent_destroy(pmemext); 173 174 if (error) { 175 aprint_error_dev(self, "configuration failed (%d)\n", 176 error); 177 return; 178 } 179 180 tegra_pcie_enable(sc); 181 182 memset(&pba, 0, sizeof(pba)); 183 pba.pba_flags = PCI_FLAGS_MRL_OKAY | 184 PCI_FLAGS_MRM_OKAY | 185 PCI_FLAGS_MWI_OKAY | 186 PCI_FLAGS_MEM_OKAY; 187 pba.pba_memt = sc->sc_bst; 188 pba.pba_dmat = sc->sc_dmat; 189 pba.pba_pc = &sc->sc_pc; 190 pba.pba_bus = 0; 191 192 config_found_ia(self, "pcibus", &pba, pcibusprint); 193 } 194 195 static int 196 tegra_pcie_intr(void *priv) 197 { 198 struct tegra_pcie_softc *sc = priv; 199 struct tegra_pcie_ih *pcie_ih; 200 201 const uint32_t code = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, 202 AFI_INTR_CODE_REG); 203 const uint32_t sig = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, 204 AFI_INTR_SIGNATURE_REG); 205 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_INTR_CODE_REG, 0); 206 207 switch (__SHIFTOUT(code, AFI_INTR_CODE_INT_CODE)) { 208 case AFI_INTR_CODE_SM_MSG: 209 mutex_enter(&sc->sc_lock); 210 const u_int lastgen = sc->sc_intrgen; 211 TAILQ_FOREACH(pcie_ih, &sc->sc_intrs, ih_entry) { 212 int (*callback)(void *) = pcie_ih->ih_callback; 213 void *arg = pcie_ih->ih_arg; 214 mutex_exit(&sc->sc_lock); 215 const int rv = callback(arg); 216 if (rv) 217 return rv; 218 mutex_enter(&sc->sc_lock); 219 if (lastgen != sc->sc_intrgen) 220 break; 221 } 222 mutex_exit(&sc->sc_lock); 223 return 0; 224 default: 225 device_printf(sc->sc_dev, "intr: code %#x sig %#x\n", 226 code, sig); 227 return 1; 228 } 229 } 230 231 static void 232 tegra_pcie_enable(struct tegra_pcie_softc *sc) 233 { 234 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 235 AFI_SM_INTR_ENABLE_REG, 0xffffffff); 236 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 237 AFI_AFI_INTR_ENABLE_REG, 0); 238 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_INTR_CODE_REG, 0); 239 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 240 AFI_INTR_MASK_REG, AFI_INTR_MASK_INT); 241 } 242 243 void 244 tegra_pcie_init(pci_chipset_tag_t pc, void *priv) 245 { 246 pc->pc_conf_v = priv; 247 pc->pc_attach_hook = tegra_pcie_attach_hook; 248 pc->pc_bus_maxdevs = tegra_pcie_bus_maxdevs; 249 pc->pc_make_tag = tegra_pcie_make_tag; 250 pc->pc_decompose_tag = tegra_pcie_decompose_tag; 251 pc->pc_conf_read = tegra_pcie_conf_read; 252 pc->pc_conf_write = tegra_pcie_conf_write; 253 pc->pc_conf_hook = tegra_pcie_conf_hook; 254 pc->pc_conf_interrupt = tegra_pcie_conf_interrupt; 255 256 pc->pc_intr_v = priv; 257 pc->pc_intr_map = tegra_pcie_intr_map; 258 pc->pc_intr_string = tegra_pcie_intr_string; 259 pc->pc_intr_evcnt = tegra_pcie_intr_evcnt; 260 pc->pc_intr_establish = tegra_pcie_intr_establish; 261 pc->pc_intr_disestablish = tegra_pcie_intr_disestablish; 262 } 263 264 static void 265 tegra_pcie_attach_hook(device_t parent, device_t self, 266 struct pcibus_attach_args *pba) 267 { 268 } 269 270 static int 271 tegra_pcie_bus_maxdevs(void *v, int busno) 272 { 273 return busno == 0 ? 2 : 32; 274 } 275 276 static pcitag_t 277 tegra_pcie_make_tag(void *v, int b, int d, int f) 278 { 279 return (b << 16) | (d << 11) | (f << 8); 280 } 281 282 static void 283 tegra_pcie_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 284 { 285 if (bp) 286 *bp = (tag >> 16) & 0xff; 287 if (dp) 288 *dp = (tag >> 11) & 0x1f; 289 if (fp) 290 *fp = (tag >> 8) & 0x7; 291 } 292 293 static pcireg_t 294 tegra_pcie_conf_read(void *v, pcitag_t tag, int offset) 295 { 296 struct tegra_pcie_softc *sc = v; 297 bus_space_handle_t bsh; 298 int b, d, f; 299 u_int reg; 300 301 if ((unsigned int)offset >= PCI_EXTCONF_SIZE) 302 return (pcireg_t) -1; 303 304 tegra_pcie_decompose_tag(v, tag, &b, &d, &f); 305 306 if (b == 0) { 307 reg = d * 0x1000 + offset; 308 bsh = sc->sc_bsh_a1; 309 } else { 310 reg = tag | offset; 311 bsh = sc->sc_bsh_a2; 312 } 313 314 return bus_space_read_4(sc->sc_bst, bsh, reg); 315 } 316 317 static void 318 tegra_pcie_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 319 { 320 struct tegra_pcie_softc *sc = v; 321 bus_space_handle_t bsh; 322 int b, d, f; 323 u_int reg; 324 325 if ((unsigned int)offset >= PCI_EXTCONF_SIZE) 326 return; 327 328 tegra_pcie_decompose_tag(v, tag, &b, &d, &f); 329 330 if (b == 0) { 331 reg = d * 0x1000 + offset; 332 bsh = sc->sc_bsh_a1; 333 } else { 334 reg = tag | offset; 335 bsh = sc->sc_bsh_a2; 336 } 337 338 bus_space_write_4(sc->sc_bst, bsh, reg, val); 339 } 340 341 static int 342 tegra_pcie_conf_hook(void *v, int b, int d, int f, pcireg_t id) 343 { 344 return PCI_CONF_ENABLE_MEM | PCI_CONF_MAP_MEM | PCI_CONF_ENABLE_BM; 345 } 346 347 static void 348 tegra_pcie_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, 349 int *ilinep) 350 { 351 *ilinep = 5; 352 } 353 354 static int 355 tegra_pcie_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ih) 356 { 357 if (pa->pa_intrpin == 0) 358 return EINVAL; 359 *ih = pa->pa_intrpin; 360 return 0; 361 } 362 363 static const char * 364 tegra_pcie_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 365 { 366 struct tegra_pcie_softc *sc = v; 367 368 if (ih == PCI_INTERRUPT_PIN_NONE) 369 return NULL; 370 371 snprintf(buf, len, "irq %d", sc->sc_intr); 372 return buf; 373 } 374 375 const struct evcnt * 376 tegra_pcie_intr_evcnt(void *v, pci_intr_handle_t ih) 377 { 378 return NULL; 379 } 380 381 static void * 382 tegra_pcie_intr_establish(void *v, pci_intr_handle_t ih, int ipl, 383 int (*callback)(void *), void *arg) 384 { 385 struct tegra_pcie_softc *sc = v; 386 struct tegra_pcie_ih *pcie_ih; 387 388 if (ih == 0) 389 return NULL; 390 391 pcie_ih = kmem_alloc(sizeof(*pcie_ih), KM_SLEEP); 392 pcie_ih->ih_callback = callback; 393 pcie_ih->ih_arg = arg; 394 pcie_ih->ih_ipl = ipl; 395 396 mutex_enter(&sc->sc_lock); 397 TAILQ_INSERT_TAIL(&sc->sc_intrs, pcie_ih, ih_entry); 398 sc->sc_intrgen++; 399 mutex_exit(&sc->sc_lock); 400 401 return pcie_ih; 402 } 403 404 static void 405 tegra_pcie_intr_disestablish(void *v, void *vih) 406 { 407 struct tegra_pcie_softc *sc = v; 408 struct tegra_pcie_ih *pcie_ih = vih; 409 410 mutex_enter(&sc->sc_lock); 411 TAILQ_REMOVE(&sc->sc_intrs, pcie_ih, ih_entry); 412 mutex_exit(&sc->sc_lock); 413 414 kmem_free(pcie_ih, sizeof(*pcie_ih)); 415 } 416
Indexes created Thu Oct 02 10:09:58 GMT 2025