tegra_pcie.c revision 1.7
1 /* $NetBSD: tegra_pcie.c,v 1.7 2015/11/13 18:58:17 jakllsch Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "locators.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: tegra_pcie.c,v 1.7 2015/11/13 18:58:17 jakllsch Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/extent.h> 41 #include <sys/queue.h> 42 #include <sys/mutex.h> 43 #include <sys/kmem.h> 44 45 #include <arm/cpufunc.h> 46 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pciconf.h> 50 51 #include <arm/nvidia/tegra_reg.h> 52 #include <arm/nvidia/tegra_pciereg.h> 53 #include <arm/nvidia/tegra_var.h> 54 55 static int tegra_pcie_match(device_t, cfdata_t, void *); 56 static void tegra_pcie_attach(device_t, device_t, void *); 57 58 struct tegra_pcie_ih { 59 int (*ih_callback)(void *); 60 void *ih_arg; 61 int ih_ipl; 62 TAILQ_ENTRY(tegra_pcie_ih) ih_entry; 63 }; 64 65 struct tegra_pcie_softc { 66 device_t sc_dev; 67 bus_dma_tag_t sc_dmat; 68 bus_space_tag_t sc_bst; 69 bus_space_handle_t sc_bsh_afi; 70 bus_space_handle_t sc_bsh_a1; 71 bus_space_handle_t sc_bsh_a2; 72 int sc_intr; 73 74 struct arm32_pci_chipset sc_pc; 75 76 void *sc_ih; 77 78 kmutex_t sc_lock; 79 80 TAILQ_HEAD(, tegra_pcie_ih) sc_intrs; 81 u_int sc_intrgen; 82 }; 83 84 static int tegra_pcie_intr(void *); 85 static void tegra_pcie_init(pci_chipset_tag_t, void *); 86 static void tegra_pcie_enable(struct tegra_pcie_softc *); 87 88 static void tegra_pcie_attach_hook(device_t, device_t, 89 struct pcibus_attach_args *); 90 static int tegra_pcie_bus_maxdevs(void *, int); 91 static pcitag_t tegra_pcie_make_tag(void *, int, int, int); 92 static void tegra_pcie_decompose_tag(void *, pcitag_t, int *, int *, int *); 93 static pcireg_t tegra_pcie_conf_read(void *, pcitag_t, int); 94 static void tegra_pcie_conf_write(void *, pcitag_t, int, pcireg_t); 95 static int tegra_pcie_conf_hook(void *, int, int, int, pcireg_t); 96 static void tegra_pcie_conf_interrupt(void *, int, int, int, int, int *); 97 98 static int tegra_pcie_intr_map(const struct pci_attach_args *, 99 pci_intr_handle_t *); 100 static const char *tegra_pcie_intr_string(void *, pci_intr_handle_t, 101 char *, size_t); 102 const struct evcnt *tegra_pcie_intr_evcnt(void *, pci_intr_handle_t); 103 static void * tegra_pcie_intr_establish(void *, pci_intr_handle_t, 104 int, int (*)(void *), void *); 105 static void tegra_pcie_intr_disestablish(void *, void *); 106 107 CFATTACH_DECL_NEW(tegra_pcie, sizeof(struct tegra_pcie_softc), 108 tegra_pcie_match, tegra_pcie_attach, NULL, NULL); 109 110 static int 111 tegra_pcie_match(device_t parent, cfdata_t cf, void *aux) 112 { 113 return 1; 114 } 115 116 static void 117 tegra_pcie_attach(device_t parent, device_t self, void *aux) 118 { 119 struct tegra_pcie_softc * const sc = device_private(self); 120 struct tegraio_attach_args * const tio = aux; 121 const struct tegra_locators * const loc = &tio->tio_loc; 122 struct extent *memext, *pmemext; 123 struct pcibus_attach_args pba; 124 int error; 125 126 sc->sc_dev = self; 127 #if notyet 128 sc->sc_dmat = tio->tio_coherent_dmat; 129 #else 130 sc->sc_dmat = tio->tio_dmat; 131 #endif 132 sc->sc_bst = tio->tio_bst; 133 sc->sc_intr = loc->loc_intr; 134 if (bus_space_map(sc->sc_bst, TEGRA_PCIE_AFI_BASE, TEGRA_PCIE_AFI_SIZE, 135 0, &sc->sc_bsh_afi) != 0) 136 panic("couldn't map PCIE AFI"); 137 if (bus_space_map(sc->sc_bst, TEGRA_PCIE_A1_BASE, TEGRA_PCIE_A1_SIZE, 138 0, &sc->sc_bsh_a1) != 0) 139 panic("couldn't map PCIE A1"); 140 if (bus_space_map(sc->sc_bst, TEGRA_PCIE_A2_BASE, TEGRA_PCIE_A2_SIZE, 141 0, &sc->sc_bsh_a2) != 0) 142 panic("couldn't map PCIE A2"); 143 144 TAILQ_INIT(&sc->sc_intrs); 145 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 146 147 aprint_naive("\n"); 148 aprint_normal(": PCIE\n"); 149 150 sc->sc_ih = intr_establish(loc->loc_intr, IPL_VM, IST_LEVEL, 151 tegra_pcie_intr, sc); 152 if (sc->sc_ih == NULL) { 153 aprint_error_dev(self, "failed to establish interrupt %d\n", 154 loc->loc_intr); 155 return; 156 } 157 aprint_normal_dev(self, "interrupting on irq %d\n", loc->loc_intr); 158 159 tegra_pcie_init(&sc->sc_pc, sc); 160 161 memext = extent_create("pcimem", TEGRA_PCIE_MEM_BASE, 162 TEGRA_PCIE_MEM_BASE + TEGRA_PCIE_MEM_SIZE - 1, 163 NULL, 0, EX_NOWAIT); 164 pmemext = extent_create("pcipmem", TEGRA_PCIE_PMEM_BASE, 165 TEGRA_PCIE_PMEM_BASE + TEGRA_PCIE_PMEM_SIZE - 1, 166 NULL, 0, EX_NOWAIT); 167 168 error = pci_configure_bus(&sc->sc_pc, NULL, memext, pmemext, 0, 169 arm_dcache_align); 170 171 extent_destroy(memext); 172 extent_destroy(pmemext); 173 174 if (error) { 175 aprint_error_dev(self, "configuration failed (%d)\n", 176 error); 177 return; 178 } 179 180 tegra_pcie_enable(sc); 181 182 memset(&pba, 0, sizeof(pba)); 183 pba.pba_flags = PCI_FLAGS_MRL_OKAY | 184 PCI_FLAGS_MRM_OKAY | 185 PCI_FLAGS_MWI_OKAY | 186 PCI_FLAGS_MEM_OKAY; 187 pba.pba_memt = sc->sc_bst; 188 pba.pba_dmat = sc->sc_dmat; 189 pba.pba_pc = &sc->sc_pc; 190 pba.pba_bus = 0; 191 192 config_found_ia(self, "pcibus", &pba, pcibusprint); 193 } 194 195 static int 196 tegra_pcie_legacy_intr(struct tegra_pcie_softc *sc) 197 { 198 const uint32_t msg = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, 199 AFI_MSG_REG); 200 struct tegra_pcie_ih *pcie_ih; 201 int rv = 0; 202 203 if (msg & (AFI_MSG_INT0|AFI_MSG_INT1)) { 204 mutex_enter(&sc->sc_lock); 205 const u_int lastgen = sc->sc_intrgen; 206 TAILQ_FOREACH(pcie_ih, &sc->sc_intrs, ih_entry) { 207 int (*callback)(void *) = pcie_ih->ih_callback; 208 void *arg = pcie_ih->ih_arg; 209 mutex_exit(&sc->sc_lock); 210 rv += callback(arg); 211 mutex_enter(&sc->sc_lock); 212 if (lastgen != sc->sc_intrgen) 213 break; 214 } 215 mutex_exit(&sc->sc_lock); 216 } else if (msg & (AFI_MSG_PM_PME0|AFI_MSG_PM_PME1)) { 217 device_printf(sc->sc_dev, "PM PME message; AFI_MSG=%08x\n", 218 msg); 219 } else { 220 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_MSG_REG, msg); 221 rv = 1; 222 } 223 224 return rv; 225 } 226 227 static int 228 tegra_pcie_intr(void *priv) 229 { 230 struct tegra_pcie_softc *sc = priv; 231 232 const uint32_t code = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, 233 AFI_INTR_CODE_REG); 234 const uint32_t sig = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, 235 AFI_INTR_SIGNATURE_REG); 236 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_INTR_CODE_REG, 0); 237 238 switch (__SHIFTOUT(code, AFI_INTR_CODE_INT_CODE)) { 239 case AFI_INTR_CODE_SM_MSG: 240 return tegra_pcie_legacy_intr(sc); 241 default: 242 device_printf(sc->sc_dev, "intr: code %#x sig %#x\n", 243 code, sig); 244 return 1; 245 } 246 } 247 248 static void 249 tegra_pcie_enable(struct tegra_pcie_softc *sc) 250 { 251 /* disable MSI */ 252 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 253 AFI_MSI_BAR_SZ_REG, 0); 254 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 255 AFI_MSI_FPCI_BAR_ST_REG, 0); 256 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 257 AFI_MSI_AXI_BAR_ST_REG, 0); 258 259 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 260 AFI_SM_INTR_ENABLE_REG, 0xffffffff); 261 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 262 AFI_AFI_INTR_ENABLE_REG, 0); 263 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_INTR_CODE_REG, 0); 264 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 265 AFI_INTR_MASK_REG, AFI_INTR_MASK_INT); 266 } 267 268 void 269 tegra_pcie_init(pci_chipset_tag_t pc, void *priv) 270 { 271 pc->pc_conf_v = priv; 272 pc->pc_attach_hook = tegra_pcie_attach_hook; 273 pc->pc_bus_maxdevs = tegra_pcie_bus_maxdevs; 274 pc->pc_make_tag = tegra_pcie_make_tag; 275 pc->pc_decompose_tag = tegra_pcie_decompose_tag; 276 pc->pc_conf_read = tegra_pcie_conf_read; 277 pc->pc_conf_write = tegra_pcie_conf_write; 278 pc->pc_conf_hook = tegra_pcie_conf_hook; 279 pc->pc_conf_interrupt = tegra_pcie_conf_interrupt; 280 281 pc->pc_intr_v = priv; 282 pc->pc_intr_map = tegra_pcie_intr_map; 283 pc->pc_intr_string = tegra_pcie_intr_string; 284 pc->pc_intr_evcnt = tegra_pcie_intr_evcnt; 285 pc->pc_intr_establish = tegra_pcie_intr_establish; 286 pc->pc_intr_disestablish = tegra_pcie_intr_disestablish; 287 } 288 289 static void 290 tegra_pcie_attach_hook(device_t parent, device_t self, 291 struct pcibus_attach_args *pba) 292 { 293 } 294 295 static int 296 tegra_pcie_bus_maxdevs(void *v, int busno) 297 { 298 return busno == 0 ? 2 : 32; 299 } 300 301 static pcitag_t 302 tegra_pcie_make_tag(void *v, int b, int d, int f) 303 { 304 return (b << 16) | (d << 11) | (f << 8); 305 } 306 307 static void 308 tegra_pcie_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 309 { 310 if (bp) 311 *bp = (tag >> 16) & 0xff; 312 if (dp) 313 *dp = (tag >> 11) & 0x1f; 314 if (fp) 315 *fp = (tag >> 8) & 0x7; 316 } 317 318 static pcireg_t 319 tegra_pcie_conf_read(void *v, pcitag_t tag, int offset) 320 { 321 struct tegra_pcie_softc *sc = v; 322 bus_space_handle_t bsh; 323 int b, d, f; 324 u_int reg; 325 326 if ((unsigned int)offset >= PCI_EXTCONF_SIZE) 327 return (pcireg_t) -1; 328 329 tegra_pcie_decompose_tag(v, tag, &b, &d, &f); 330 331 if (b == 0) { 332 if (d >= 2 || f != 0) 333 return (pcireg_t) -1; 334 reg = d * 0x1000 + offset; 335 bsh = sc->sc_bsh_a1; 336 } else { 337 if ((unsigned int)offset >= PCI_CONF_SIZE) 338 return (pcireg_t) -1; 339 reg = tag | offset; 340 bsh = sc->sc_bsh_a2; 341 } 342 343 return bus_space_read_4(sc->sc_bst, bsh, reg); 344 } 345 346 static void 347 tegra_pcie_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 348 { 349 struct tegra_pcie_softc *sc = v; 350 bus_space_handle_t bsh; 351 int b, d, f; 352 u_int reg; 353 354 if ((unsigned int)offset >= PCI_EXTCONF_SIZE) 355 return; 356 357 tegra_pcie_decompose_tag(v, tag, &b, &d, &f); 358 359 if (b == 0) { 360 if (d >= 2 || f != 0) 361 return; 362 reg = d * 0x1000 + offset; 363 bsh = sc->sc_bsh_a1; 364 } else { 365 if ((unsigned int)offset >= PCI_CONF_SIZE) 366 return; 367 reg = tag | offset; 368 bsh = sc->sc_bsh_a2; 369 } 370 371 bus_space_write_4(sc->sc_bst, bsh, reg, val); 372 } 373 374 static int 375 tegra_pcie_conf_hook(void *v, int b, int d, int f, pcireg_t id) 376 { 377 return PCI_CONF_ENABLE_MEM | PCI_CONF_MAP_MEM | PCI_CONF_ENABLE_BM; 378 } 379 380 static void 381 tegra_pcie_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, 382 int *ilinep) 383 { 384 *ilinep = 5; 385 } 386 387 static int 388 tegra_pcie_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ih) 389 { 390 if (pa->pa_intrpin == 0) 391 return EINVAL; 392 *ih = pa->pa_intrpin; 393 return 0; 394 } 395 396 static const char * 397 tegra_pcie_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 398 { 399 struct tegra_pcie_softc *sc = v; 400 401 if (ih == PCI_INTERRUPT_PIN_NONE) 402 return NULL; 403 404 snprintf(buf, len, "irq %d", sc->sc_intr); 405 return buf; 406 } 407 408 const struct evcnt * 409 tegra_pcie_intr_evcnt(void *v, pci_intr_handle_t ih) 410 { 411 return NULL; 412 } 413 414 static void * 415 tegra_pcie_intr_establish(void *v, pci_intr_handle_t ih, int ipl, 416 int (*callback)(void *), void *arg) 417 { 418 struct tegra_pcie_softc *sc = v; 419 struct tegra_pcie_ih *pcie_ih; 420 421 if (ih == 0) 422 return NULL; 423 424 pcie_ih = kmem_alloc(sizeof(*pcie_ih), KM_SLEEP); 425 pcie_ih->ih_callback = callback; 426 pcie_ih->ih_arg = arg; 427 pcie_ih->ih_ipl = ipl; 428 429 mutex_enter(&sc->sc_lock); 430 TAILQ_INSERT_TAIL(&sc->sc_intrs, pcie_ih, ih_entry); 431 sc->sc_intrgen++; 432 mutex_exit(&sc->sc_lock); 433 434 return pcie_ih; 435 } 436 437 static void 438 tegra_pcie_intr_disestablish(void *v, void *vih) 439 { 440 struct tegra_pcie_softc *sc = v; 441 struct tegra_pcie_ih *pcie_ih = vih; 442 443 mutex_enter(&sc->sc_lock); 444 TAILQ_REMOVE(&sc->sc_intrs, pcie_ih, ih_entry); 445 mutex_exit(&sc->sc_lock); 446 447 kmem_free(pcie_ih, sizeof(*pcie_ih)); 448 } 449
Indexes created Thu Oct 02 10:09:58 GMT 2025