tegra_pciereg.h revision 1.1.2.3
1 1.1.2.3 skrll /* $NetBSD: tegra_pciereg.h,v 1.1.2.3 2015/12/27 12:09:31 skrll Exp $ */ 2 1.1.2.2 skrll 3 1.1.2.2 skrll /*- 4 1.1.2.2 skrll * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 1.1.2.2 skrll * All rights reserved. 6 1.1.2.2 skrll * 7 1.1.2.2 skrll * Redistribution and use in source and binary forms, with or without 8 1.1.2.2 skrll * modification, are permitted provided that the following conditions 9 1.1.2.2 skrll * are met: 10 1.1.2.2 skrll * 1. Redistributions of source code must retain the above copyright 11 1.1.2.2 skrll * notice, this list of conditions and the following disclaimer. 12 1.1.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 13 1.1.2.2 skrll * notice, this list of conditions and the following disclaimer in the 14 1.1.2.2 skrll * documentation and/or other materials provided with the distribution. 15 1.1.2.2 skrll * 16 1.1.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 1.1.2.2 skrll * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 1.1.2.2 skrll * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 1.1.2.2 skrll * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 1.1.2.2 skrll * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 1.1.2.2 skrll * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 1.1.2.2 skrll * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 1.1.2.2 skrll * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 1.1.2.2 skrll * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.1.2.2 skrll * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.1.2.2 skrll * SUCH DAMAGE. 27 1.1.2.2 skrll */ 28 1.1.2.2 skrll 29 1.1.2.2 skrll #ifndef _ARM_TEGRA_PCIEREG_H 30 1.1.2.2 skrll #define _ARM_TEGRA_PCIEREG_H 31 1.1.2.2 skrll 32 1.1.2.2 skrll /* AFI */ 33 1.1.2.3 skrll #define AFI_AXI_NBAR 9 34 1.1.2.3 skrll 35 1.1.2.3 skrll #define AFI_AXI_BARi_SZ(i) ((i) < 6 ? \ 36 1.1.2.3 skrll 0x000 + ((i) - 0) * 0x04 : \ 37 1.1.2.3 skrll 0x134 + ((i) - 6) * 0x04) 38 1.1.2.3 skrll 39 1.1.2.3 skrll #define AFI_AXI_BARi_START(i) ((i) < 6 ? \ 40 1.1.2.3 skrll 0x018 + ((i) - 0) * 0x04 : \ 41 1.1.2.3 skrll 0x140 + ((i) - 6) * 0x04) 42 1.1.2.3 skrll 43 1.1.2.3 skrll #define AFI_FPCI_BARi(i) ((i) < 6 ? \ 44 1.1.2.3 skrll 0x030 + ((i) - 0) * 0x04 : \ 45 1.1.2.3 skrll 0x14c + ((i) - 6) * 0x04) 46 1.1.2.3 skrll 47 1.1.2.3 skrll #define AFI_MSI_BAR_SZ_REG 0x60 48 1.1.2.3 skrll #define AFI_MSI_FPCI_BAR_ST_REG 0x64 49 1.1.2.3 skrll #define AFI_MSI_AXI_BAR_ST_REG 0x68 50 1.1.2.2 skrll #define AFI_INTR_MASK_REG 0xb4 51 1.1.2.2 skrll #define AFI_INTR_CODE_REG 0xb8 52 1.1.2.2 skrll #define AFI_INTR_SIGNATURE_REG 0xbc 53 1.1.2.2 skrll #define AFI_SM_INTR_ENABLE_REG 0xc4 54 1.1.2.2 skrll #define AFI_AFI_INTR_ENABLE_REG 0xc8 55 1.1.2.3 skrll #define AFI_MSG_REG 0x190 56 1.1.2.2 skrll 57 1.1.2.2 skrll #define AFI_INTR_MASK_MSI __BIT(8) 58 1.1.2.2 skrll #define AFI_INTR_MASK_INT __BIT(0) 59 1.1.2.2 skrll 60 1.1.2.2 skrll #define AFI_INTR_CODE_INT_CODE __BITS(4,0) 61 1.1.2.2 skrll #define AFI_INTR_CODE_SM_MSG 6 62 1.1.2.2 skrll 63 1.1.2.3 skrll #define AFI_MSG_INT1 __BITS(27,24) 64 1.1.2.3 skrll #define AFI_MSG_PM_PME1 __BIT(20) 65 1.1.2.3 skrll #define AFI_MSG_INT0 __BITS(11,8) 66 1.1.2.3 skrll #define AFI_MSG_PM_PME0 __BIT(4) 67 1.1.2.3 skrll 68 1.1.2.2 skrll #endif /* _ARM_TEGRA_PCIEREG_H */ 69
Indexes created Tue Oct 28 12:10:06 GMT 2025