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tegra_pciereg.h revision 1.3 
      1 /* $NetBSD: tegra_pciereg.h,v 1.3 2015/11/14 01:38:58 jakllsch Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #ifndef _ARM_TEGRA_PCIEREG_H
     30 #define _ARM_TEGRA_PCIEREG_H
     31 
     32 /* AFI */
     33 #define AFI_AXI_NBAR		9
     34 
     35 #define AFI_AXI_BARi_SZ(i)	((i) < 6 ? \
     36     0x000 + ((i) - 0) * 0x04 : \
     37     0x134 + ((i) - 6) * 0x04)
     38 
     39 #define AFI_AXI_BARi_START(i)	((i) < 6 ? \
     40     0x018 + ((i) - 0) * 0x04 : \
     41     0x140 + ((i) - 6) * 0x04)
     42 
     43 #define AFI_FPCI_BARi(i)	((i) < 6 ? \
     44     0x030 + ((i) - 0) * 0x04 : \
     45     0x14c + ((i) - 6) * 0x04)
     46 
     47 #define AFI_MSI_BAR_SZ_REG	0x60
     48 #define AFI_MSI_FPCI_BAR_ST_REG	0x64
     49 #define AFI_MSI_AXI_BAR_ST_REG	0x68
     50 #define AFI_INTR_MASK_REG	0xb4
     51 #define AFI_INTR_CODE_REG	0xb8
     52 #define AFI_INTR_SIGNATURE_REG	0xbc
     53 #define AFI_SM_INTR_ENABLE_REG	0xc4
     54 #define AFI_AFI_INTR_ENABLE_REG	0xc8
     55 #define AFI_MSG_REG		0x190
     56 
     57 #define AFI_INTR_MASK_MSI	__BIT(8)
     58 #define AFI_INTR_MASK_INT	__BIT(0)
     59 
     60 #define AFI_INTR_CODE_INT_CODE	__BITS(4,0)
     61 #define AFI_INTR_CODE_SM_MSG	6
     62 
     63 #define AFI_MSG_INT1		__BITS(27,24)
     64 #define AFI_MSG_PM_PME1		__BIT(20)
     65 #define AFI_MSG_INT0		__BITS(11,8)
     66 #define AFI_MSG_PM_PME0		__BIT(4)
     67 
     68 #endif /* _ARM_TEGRA_PCIEREG_H */
     69