tegra_soc.c revision 1.2.2.3
1 1.2.2.3 skrll /* $NetBSD: tegra_soc.c,v 1.2.2.3 2015/06/06 14:39:56 skrll Exp $ */ 2 1.2.2.2 skrll 3 1.2.2.2 skrll /*- 4 1.2.2.2 skrll * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 1.2.2.2 skrll * All rights reserved. 6 1.2.2.2 skrll * 7 1.2.2.2 skrll * Redistribution and use in source and binary forms, with or without 8 1.2.2.2 skrll * modification, are permitted provided that the following conditions 9 1.2.2.2 skrll * are met: 10 1.2.2.2 skrll * 1. Redistributions of source code must retain the above copyright 11 1.2.2.2 skrll * notice, this list of conditions and the following disclaimer. 12 1.2.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 13 1.2.2.2 skrll * notice, this list of conditions and the following disclaimer in the 14 1.2.2.2 skrll * documentation and/or other materials provided with the distribution. 15 1.2.2.2 skrll * 16 1.2.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 1.2.2.2 skrll * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 1.2.2.2 skrll * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 1.2.2.2 skrll * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 1.2.2.2 skrll * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 1.2.2.2 skrll * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 1.2.2.2 skrll * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 1.2.2.2 skrll * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 1.2.2.2 skrll * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.2.2.2 skrll * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.2.2.2 skrll * SUCH DAMAGE. 27 1.2.2.2 skrll */ 28 1.2.2.2 skrll 29 1.2.2.2 skrll #include "opt_tegra.h" 30 1.2.2.2 skrll #include "opt_multiprocessor.h" 31 1.2.2.2 skrll 32 1.2.2.2 skrll #include <sys/cdefs.h> 33 1.2.2.3 skrll __KERNEL_RCSID(0, "$NetBSD: tegra_soc.c,v 1.2.2.3 2015/06/06 14:39:56 skrll Exp $"); 34 1.2.2.2 skrll 35 1.2.2.2 skrll #define _ARM32_BUS_DMA_PRIVATE 36 1.2.2.2 skrll #include <sys/param.h> 37 1.2.2.2 skrll #include <sys/bus.h> 38 1.2.2.2 skrll #include <sys/cpu.h> 39 1.2.2.2 skrll #include <sys/device.h> 40 1.2.2.2 skrll 41 1.2.2.2 skrll #include <uvm/uvm_extern.h> 42 1.2.2.2 skrll 43 1.2.2.2 skrll #include <arm/bootconfig.h> 44 1.2.2.2 skrll #include <arm/cpufunc.h> 45 1.2.2.2 skrll 46 1.2.2.2 skrll #include <arm/nvidia/tegra_reg.h> 47 1.2.2.2 skrll #include <arm/nvidia/tegra_apbreg.h> 48 1.2.2.2 skrll #include <arm/nvidia/tegra_mcreg.h> 49 1.2.2.2 skrll #include <arm/nvidia/tegra_var.h> 50 1.2.2.2 skrll 51 1.2.2.2 skrll bus_space_handle_t tegra_host1x_bsh; 52 1.2.2.3 skrll bus_space_handle_t tegra_ppsb_bsh; 53 1.2.2.2 skrll bus_space_handle_t tegra_apb_bsh; 54 1.2.2.2 skrll bus_space_handle_t tegra_ahb_a2_bsh; 55 1.2.2.2 skrll 56 1.2.2.2 skrll struct arm32_bus_dma_tag tegra_dma_tag = { 57 1.2.2.2 skrll _BUS_DMAMAP_FUNCS, 58 1.2.2.2 skrll _BUS_DMAMEM_FUNCS, 59 1.2.2.2 skrll _BUS_DMATAG_FUNCS, 60 1.2.2.2 skrll }; 61 1.2.2.2 skrll 62 1.2.2.3 skrll static struct arm32_dma_range tegra_coherent_dma_ranges[] = { 63 1.2.2.3 skrll [0] = { 64 1.2.2.3 skrll .dr_sysbase = TEGRA_EXTMEM_BASE, 65 1.2.2.3 skrll .dr_busbase = TEGRA_EXTMEM_BASE, 66 1.2.2.3 skrll .dr_flags = _BUS_DMAMAP_COHERENT, 67 1.2.2.3 skrll }, 68 1.2.2.3 skrll }; 69 1.2.2.3 skrll 70 1.2.2.3 skrll struct arm32_bus_dma_tag tegra_coherent_dma_tag = { 71 1.2.2.3 skrll ._ranges = tegra_coherent_dma_ranges, 72 1.2.2.3 skrll ._nranges = __arraycount(tegra_coherent_dma_ranges), 73 1.2.2.3 skrll _BUS_DMAMAP_FUNCS, 74 1.2.2.3 skrll _BUS_DMAMEM_FUNCS, 75 1.2.2.3 skrll _BUS_DMATAG_FUNCS, 76 1.2.2.3 skrll }; 77 1.2.2.3 skrll 78 1.2.2.2 skrll static void tegra_mpinit(void); 79 1.2.2.2 skrll 80 1.2.2.2 skrll void 81 1.2.2.2 skrll tegra_bootstrap(void) 82 1.2.2.2 skrll { 83 1.2.2.3 skrll if (bus_space_map(&armv7_generic_bs_tag, 84 1.2.2.2 skrll TEGRA_HOST1X_BASE, TEGRA_HOST1X_SIZE, 0, 85 1.2.2.3 skrll &tegra_host1x_bsh) != 0) 86 1.2.2.3 skrll panic("couldn't map HOST1X"); 87 1.2.2.3 skrll if (bus_space_map(&armv7_generic_bs_tag, 88 1.2.2.3 skrll TEGRA_PPSB_BASE, TEGRA_PPSB_SIZE, 0, 89 1.2.2.3 skrll &tegra_ppsb_bsh) != 0) 90 1.2.2.3 skrll panic("couldn't map PPSB"); 91 1.2.2.3 skrll if (bus_space_map(&armv7_generic_bs_tag, 92 1.2.2.2 skrll TEGRA_APB_BASE, TEGRA_APB_SIZE, 0, 93 1.2.2.3 skrll &tegra_apb_bsh) != 0) 94 1.2.2.3 skrll panic("couldn't map APB"); 95 1.2.2.3 skrll if (bus_space_map(&armv7_generic_bs_tag, 96 1.2.2.2 skrll TEGRA_AHB_A2_BASE, TEGRA_AHB_A2_SIZE, 0, 97 1.2.2.3 skrll &tegra_ahb_a2_bsh) != 0) 98 1.2.2.3 skrll panic("couldn't map AHB A2"); 99 1.2.2.2 skrll 100 1.2.2.3 skrll curcpu()->ci_data.cpu_cc_freq = tegra_car_pllx_rate(); 101 1.2.2.2 skrll 102 1.2.2.2 skrll tegra_mpinit(); 103 1.2.2.3 skrll } 104 1.2.2.3 skrll 105 1.2.2.3 skrll void 106 1.2.2.3 skrll tegra_dma_bootstrap(psize_t psize) 107 1.2.2.3 skrll { 108 1.2.2.3 skrll tegra_coherent_dma_ranges[0].dr_len = psize; 109 1.2.2.3 skrll } 110 1.2.2.3 skrll 111 1.2.2.3 skrll void 112 1.2.2.3 skrll tegra_cpuinit(void) 113 1.2.2.3 skrll { 114 1.2.2.3 skrll switch (tegra_chip_id()) { 115 1.2.2.3 skrll #ifdef SOC_TEGRA124 116 1.2.2.3 skrll case CHIP_ID_TEGRA124: 117 1.2.2.3 skrll tegra124_cpuinit(); 118 1.2.2.3 skrll break; 119 1.2.2.2 skrll #endif 120 1.2.2.3 skrll } 121 1.2.2.3 skrll 122 1.2.2.3 skrll tegra_cpufreq_init(); 123 1.2.2.2 skrll } 124 1.2.2.2 skrll 125 1.2.2.2 skrll static void 126 1.2.2.2 skrll tegra_mpinit(void) 127 1.2.2.2 skrll { 128 1.2.2.3 skrll #if defined(MULTIPROCESSOR) 129 1.2.2.2 skrll switch (tegra_chip_id()) { 130 1.2.2.2 skrll #ifdef SOC_TEGRA124 131 1.2.2.2 skrll case CHIP_ID_TEGRA124: 132 1.2.2.2 skrll tegra124_mpinit(); 133 1.2.2.2 skrll break; 134 1.2.2.2 skrll #endif 135 1.2.2.2 skrll default: 136 1.2.2.2 skrll panic("Unsupported SOC ID %#x", tegra_chip_id()); 137 1.2.2.2 skrll } 138 1.2.2.2 skrll #endif 139 1.2.2.3 skrll } 140 1.2.2.2 skrll 141 1.2.2.2 skrll u_int 142 1.2.2.2 skrll tegra_chip_id(void) 143 1.2.2.2 skrll { 144 1.2.2.2 skrll static u_int chip_id = 0; 145 1.2.2.2 skrll 146 1.2.2.2 skrll if (!chip_id) { 147 1.2.2.2 skrll const bus_space_tag_t bst = &armv7_generic_bs_tag; 148 1.2.2.2 skrll const bus_space_handle_t bsh = tegra_apb_bsh; 149 1.2.2.2 skrll const uint32_t v = bus_space_read_4(bst, bsh, 150 1.2.2.2 skrll APB_MISC_GP_HIDREV_0_REG); 151 1.2.2.2 skrll chip_id = __SHIFTOUT(v, APB_MISC_GP_HIDREV_0_CHIPID); 152 1.2.2.2 skrll } 153 1.2.2.2 skrll 154 1.2.2.2 skrll return chip_id; 155 1.2.2.2 skrll } 156 1.2.2.2 skrll 157 1.2.2.2 skrll const char * 158 1.2.2.2 skrll tegra_chip_name(void) 159 1.2.2.2 skrll { 160 1.2.2.2 skrll switch (tegra_chip_id()) { 161 1.2.2.2 skrll case CHIP_ID_TEGRA124: return "Tegra K1 (T124)"; 162 1.2.2.2 skrll case CHIP_ID_TEGRA132: return "Tegra K1 (T132)"; 163 1.2.2.2 skrll default: return "Unknown Tegra SoC"; 164 1.2.2.2 skrll } 165 1.2.2.2 skrll } 166
Indexes created Tue Oct 14 15:09:51 GMT 2025