tegra_soc.c revision 1.7 1 1.7 jmcneill /* $NetBSD: tegra_soc.c,v 1.7 2015/11/19 22:09:16 jmcneill Exp $ */
2 1.1 jmcneill
3 1.1 jmcneill /*-
4 1.1 jmcneill * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca>
5 1.1 jmcneill * All rights reserved.
6 1.1 jmcneill *
7 1.1 jmcneill * Redistribution and use in source and binary forms, with or without
8 1.1 jmcneill * modification, are permitted provided that the following conditions
9 1.1 jmcneill * are met:
10 1.1 jmcneill * 1. Redistributions of source code must retain the above copyright
11 1.1 jmcneill * notice, this list of conditions and the following disclaimer.
12 1.1 jmcneill * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 jmcneill * notice, this list of conditions and the following disclaimer in the
14 1.1 jmcneill * documentation and/or other materials provided with the distribution.
15 1.1 jmcneill *
16 1.1 jmcneill * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 1.1 jmcneill * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 1.1 jmcneill * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 1.1 jmcneill * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 1.1 jmcneill * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 1.1 jmcneill * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 1.1 jmcneill * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 1.1 jmcneill * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 1.1 jmcneill * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 1.1 jmcneill * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 1.1 jmcneill * SUCH DAMAGE.
27 1.1 jmcneill */
28 1.1 jmcneill
29 1.1 jmcneill #include "opt_tegra.h"
30 1.1 jmcneill #include "opt_multiprocessor.h"
31 1.1 jmcneill
32 1.1 jmcneill #include <sys/cdefs.h>
33 1.7 jmcneill __KERNEL_RCSID(0, "$NetBSD: tegra_soc.c,v 1.7 2015/11/19 22:09:16 jmcneill Exp $");
34 1.1 jmcneill
35 1.1 jmcneill #define _ARM32_BUS_DMA_PRIVATE
36 1.1 jmcneill #include <sys/param.h>
37 1.1 jmcneill #include <sys/bus.h>
38 1.1 jmcneill #include <sys/cpu.h>
39 1.1 jmcneill #include <sys/device.h>
40 1.1 jmcneill
41 1.1 jmcneill #include <uvm/uvm_extern.h>
42 1.1 jmcneill
43 1.1 jmcneill #include <arm/bootconfig.h>
44 1.1 jmcneill #include <arm/cpufunc.h>
45 1.1 jmcneill
46 1.1 jmcneill #include <arm/nvidia/tegra_reg.h>
47 1.1 jmcneill #include <arm/nvidia/tegra_apbreg.h>
48 1.1 jmcneill #include <arm/nvidia/tegra_mcreg.h>
49 1.1 jmcneill #include <arm/nvidia/tegra_var.h>
50 1.1 jmcneill
51 1.3 jmcneill bus_space_handle_t tegra_ppsb_bsh;
52 1.1 jmcneill bus_space_handle_t tegra_apb_bsh;
53 1.1 jmcneill
54 1.1 jmcneill struct arm32_bus_dma_tag tegra_dma_tag = {
55 1.1 jmcneill _BUS_DMAMAP_FUNCS,
56 1.1 jmcneill _BUS_DMAMEM_FUNCS,
57 1.1 jmcneill _BUS_DMATAG_FUNCS,
58 1.1 jmcneill };
59 1.1 jmcneill
60 1.1 jmcneill static void tegra_mpinit(void);
61 1.1 jmcneill
62 1.1 jmcneill void
63 1.1 jmcneill tegra_bootstrap(void)
64 1.1 jmcneill {
65 1.3 jmcneill if (bus_space_map(&armv7_generic_bs_tag,
66 1.3 jmcneill TEGRA_PPSB_BASE, TEGRA_PPSB_SIZE, 0,
67 1.3 jmcneill &tegra_ppsb_bsh) != 0)
68 1.3 jmcneill panic("couldn't map PPSB");
69 1.3 jmcneill if (bus_space_map(&armv7_generic_bs_tag,
70 1.2 jmcneill TEGRA_APB_BASE, TEGRA_APB_SIZE, 0,
71 1.3 jmcneill &tegra_apb_bsh) != 0)
72 1.3 jmcneill panic("couldn't map APB");
73 1.1 jmcneill
74 1.4 jmcneill curcpu()->ci_data.cpu_cc_freq = tegra_car_pllx_rate();
75 1.1 jmcneill
76 1.1 jmcneill tegra_mpinit();
77 1.1 jmcneill }
78 1.1 jmcneill
79 1.5 jmcneill void
80 1.5 jmcneill tegra_dma_bootstrap(psize_t psize)
81 1.5 jmcneill {
82 1.5 jmcneill }
83 1.5 jmcneill
84 1.6 jmcneill void
85 1.6 jmcneill tegra_cpuinit(void)
86 1.6 jmcneill {
87 1.6 jmcneill switch (tegra_chip_id()) {
88 1.6 jmcneill #ifdef SOC_TEGRA124
89 1.6 jmcneill case CHIP_ID_TEGRA124:
90 1.6 jmcneill tegra124_cpuinit();
91 1.6 jmcneill break;
92 1.6 jmcneill #endif
93 1.6 jmcneill }
94 1.6 jmcneill
95 1.6 jmcneill tegra_cpufreq_init();
96 1.6 jmcneill }
97 1.6 jmcneill
98 1.1 jmcneill static void
99 1.1 jmcneill tegra_mpinit(void)
100 1.1 jmcneill {
101 1.3 jmcneill #if defined(MULTIPROCESSOR)
102 1.1 jmcneill switch (tegra_chip_id()) {
103 1.1 jmcneill #ifdef SOC_TEGRA124
104 1.1 jmcneill case CHIP_ID_TEGRA124:
105 1.1 jmcneill tegra124_mpinit();
106 1.1 jmcneill break;
107 1.1 jmcneill #endif
108 1.1 jmcneill default:
109 1.1 jmcneill panic("Unsupported SOC ID %#x", tegra_chip_id());
110 1.1 jmcneill }
111 1.3 jmcneill #endif
112 1.1 jmcneill }
113 1.1 jmcneill
114 1.1 jmcneill u_int
115 1.1 jmcneill tegra_chip_id(void)
116 1.1 jmcneill {
117 1.1 jmcneill static u_int chip_id = 0;
118 1.1 jmcneill
119 1.1 jmcneill if (!chip_id) {
120 1.2 jmcneill const bus_space_tag_t bst = &armv7_generic_bs_tag;
121 1.1 jmcneill const bus_space_handle_t bsh = tegra_apb_bsh;
122 1.1 jmcneill const uint32_t v = bus_space_read_4(bst, bsh,
123 1.1 jmcneill APB_MISC_GP_HIDREV_0_REG);
124 1.1 jmcneill chip_id = __SHIFTOUT(v, APB_MISC_GP_HIDREV_0_CHIPID);
125 1.1 jmcneill }
126 1.1 jmcneill
127 1.1 jmcneill return chip_id;
128 1.1 jmcneill }
129 1.1 jmcneill
130 1.1 jmcneill const char *
131 1.1 jmcneill tegra_chip_name(void)
132 1.1 jmcneill {
133 1.1 jmcneill switch (tegra_chip_id()) {
134 1.1 jmcneill case CHIP_ID_TEGRA124: return "Tegra K1 (T124)";
135 1.1 jmcneill case CHIP_ID_TEGRA132: return "Tegra K1 (T132)";
136 1.1 jmcneill default: return "Unknown Tegra SoC";
137 1.1 jmcneill }
138 1.1 jmcneill }
139