tegra_soc.c revision 1.1 1 /* $NetBSD: tegra_soc.c,v 1.1 2015/03/29 10:41:59 jmcneill Exp $ */
2
3 /*-
4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include "opt_tegra.h"
30 #include "opt_multiprocessor.h"
31
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(0, "$NetBSD: tegra_soc.c,v 1.1 2015/03/29 10:41:59 jmcneill Exp $");
34
35 #define _ARM32_BUS_DMA_PRIVATE
36 #include <sys/param.h>
37 #include <sys/bus.h>
38 #include <sys/cpu.h>
39 #include <sys/device.h>
40
41 #include <uvm/uvm_extern.h>
42
43 #include <arm/bootconfig.h>
44 #include <arm/cpufunc.h>
45
46 #include <arm/nvidia/tegra_reg.h>
47 #include <arm/nvidia/tegra_apbreg.h>
48 #include <arm/nvidia/tegra_mcreg.h>
49 #include <arm/nvidia/tegra_var.h>
50
51 bus_space_handle_t tegra_host1x_bsh;
52 bus_space_handle_t tegra_apb_bsh;
53 bus_space_handle_t tegra_ahb_a2_bsh;
54
55 struct arm32_bus_dma_tag tegra_dma_tag = {
56 _BUS_DMAMAP_FUNCS,
57 _BUS_DMAMEM_FUNCS,
58 _BUS_DMATAG_FUNCS,
59 };
60
61 #if defined(MULTIPROCESSOR)
62 static void tegra_mpinit(void);
63 #endif
64
65 void
66 tegra_bootstrap(void)
67 {
68 bus_space_map(&tegra_bs_tag, TEGRA_HOST1X_BASE, TEGRA_HOST1X_SIZE, 0,
69 &tegra_host1x_bsh);
70 bus_space_map(&tegra_bs_tag, TEGRA_APB_BASE, TEGRA_APB_SIZE, 0,
71 &tegra_apb_bsh);
72 bus_space_map(&tegra_bs_tag, TEGRA_AHB_A2_BASE, TEGRA_AHB_A2_SIZE, 0,
73 &tegra_ahb_a2_bsh);
74
75 curcpu()->ci_data.cpu_cc_freq = 696000000; /* XXX */
76
77 #if defined(MULTIPROCESSOR)
78 tegra_mpinit();
79 #endif
80 }
81
82 #if defined(MULTIPROCESSOR)
83 static void
84 tegra_mpinit(void)
85 {
86 switch (tegra_chip_id()) {
87 #ifdef SOC_TEGRA124
88 case CHIP_ID_TEGRA124:
89 tegra124_mpinit();
90 break;
91 #endif
92 default:
93 panic("Unsupported SOC ID %#x", tegra_chip_id());
94 }
95 }
96 #endif
97
98 u_int
99 tegra_chip_id(void)
100 {
101 static u_int chip_id = 0;
102
103 if (!chip_id) {
104 const bus_space_tag_t bst = &tegra_bs_tag;
105 const bus_space_handle_t bsh = tegra_apb_bsh;
106 const uint32_t v = bus_space_read_4(bst, bsh,
107 APB_MISC_GP_HIDREV_0_REG);
108 chip_id = __SHIFTOUT(v, APB_MISC_GP_HIDREV_0_CHIPID);
109 }
110
111 return chip_id;
112 }
113
114 const char *
115 tegra_chip_name(void)
116 {
117 switch (tegra_chip_id()) {
118 case CHIP_ID_TEGRA124: return "Tegra K1 (T124)";
119 case CHIP_ID_TEGRA132: return "Tegra K1 (T132)";
120 default: return "Unknown Tegra SoC";
121 }
122 }
123