tegra_soc.c revision 1.2.2.4 1 /* $NetBSD: tegra_soc.c,v 1.2.2.4 2015/12/27 12:09:31 skrll Exp $ */
2
3 /*-
4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include "opt_tegra.h"
30 #include "opt_multiprocessor.h"
31
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(0, "$NetBSD: tegra_soc.c,v 1.2.2.4 2015/12/27 12:09:31 skrll Exp $");
34
35 #define _ARM32_BUS_DMA_PRIVATE
36 #include <sys/param.h>
37 #include <sys/bus.h>
38 #include <sys/cpu.h>
39 #include <sys/device.h>
40
41 #include <uvm/uvm_extern.h>
42
43 #include <arm/bootconfig.h>
44 #include <arm/cpufunc.h>
45
46 #include <arm/nvidia/tegra_reg.h>
47 #include <arm/nvidia/tegra_apbreg.h>
48 #include <arm/nvidia/tegra_mcreg.h>
49 #include <arm/nvidia/tegra_var.h>
50
51 bus_space_handle_t tegra_ppsb_bsh;
52 bus_space_handle_t tegra_apb_bsh;
53
54 struct arm32_bus_dma_tag tegra_dma_tag = {
55 _BUS_DMAMAP_FUNCS,
56 _BUS_DMAMEM_FUNCS,
57 _BUS_DMATAG_FUNCS,
58 };
59
60 static void tegra_mpinit(void);
61
62 void
63 tegra_bootstrap(void)
64 {
65 if (bus_space_map(&armv7_generic_bs_tag,
66 TEGRA_PPSB_BASE, TEGRA_PPSB_SIZE, 0,
67 &tegra_ppsb_bsh) != 0)
68 panic("couldn't map PPSB");
69 if (bus_space_map(&armv7_generic_bs_tag,
70 TEGRA_APB_BASE, TEGRA_APB_SIZE, 0,
71 &tegra_apb_bsh) != 0)
72 panic("couldn't map APB");
73
74 tegra_mpinit();
75 }
76
77 void
78 tegra_dma_bootstrap(psize_t psize)
79 {
80 }
81
82 void
83 tegra_cpuinit(void)
84 {
85 switch (tegra_chip_id()) {
86 #ifdef SOC_TEGRA124
87 case CHIP_ID_TEGRA124:
88 tegra124_cpuinit();
89 break;
90 #endif
91 }
92
93 tegra_cpufreq_init();
94 }
95
96 static void
97 tegra_mpinit(void)
98 {
99 #if defined(MULTIPROCESSOR)
100 switch (tegra_chip_id()) {
101 #ifdef SOC_TEGRA124
102 case CHIP_ID_TEGRA124:
103 tegra124_mpinit();
104 break;
105 #endif
106 default:
107 panic("Unsupported SOC ID %#x", tegra_chip_id());
108 }
109 #endif
110 }
111
112 u_int
113 tegra_chip_id(void)
114 {
115 static u_int chip_id = 0;
116
117 if (!chip_id) {
118 const bus_space_tag_t bst = &armv7_generic_bs_tag;
119 const bus_space_handle_t bsh = tegra_apb_bsh;
120 const uint32_t v = bus_space_read_4(bst, bsh,
121 APB_MISC_GP_HIDREV_0_REG);
122 chip_id = __SHIFTOUT(v, APB_MISC_GP_HIDREV_0_CHIPID);
123 }
124
125 return chip_id;
126 }
127
128 const char *
129 tegra_chip_name(void)
130 {
131 switch (tegra_chip_id()) {
132 case CHIP_ID_TEGRA124: return "Tegra K1 (T124)";
133 case CHIP_ID_TEGRA132: return "Tegra K1 (T132)";
134 default: return "Unknown Tegra SoC";
135 }
136 }
137