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tegra_soc.c revision 1.6 
      1 /* $NetBSD: tegra_soc.c,v 1.6 2015/05/13 11:06:13 jmcneill Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #include "opt_tegra.h"
     30 #include "opt_multiprocessor.h"
     31 
     32 #include <sys/cdefs.h>
     33 __KERNEL_RCSID(0, "$NetBSD: tegra_soc.c,v 1.6 2015/05/13 11:06:13 jmcneill Exp $");
     34 
     35 #define	_ARM32_BUS_DMA_PRIVATE
     36 #include <sys/param.h>
     37 #include <sys/bus.h>
     38 #include <sys/cpu.h>
     39 #include <sys/device.h>
     40 
     41 #include <uvm/uvm_extern.h>
     42 
     43 #include <arm/bootconfig.h>
     44 #include <arm/cpufunc.h>
     45 
     46 #include <arm/nvidia/tegra_reg.h>
     47 #include <arm/nvidia/tegra_apbreg.h>
     48 #include <arm/nvidia/tegra_mcreg.h>
     49 #include <arm/nvidia/tegra_var.h>
     50 
     51 bus_space_handle_t tegra_host1x_bsh;
     52 bus_space_handle_t tegra_ppsb_bsh;
     53 bus_space_handle_t tegra_apb_bsh;
     54 bus_space_handle_t tegra_ahb_a2_bsh;
     55 
     56 struct arm32_bus_dma_tag tegra_dma_tag = {
     57 	_BUS_DMAMAP_FUNCS,
     58 	_BUS_DMAMEM_FUNCS,
     59 	_BUS_DMATAG_FUNCS,
     60 };
     61 
     62 static struct arm32_dma_range tegra_coherent_dma_ranges[] = {
     63 	[0] = {
     64 		.dr_sysbase = TEGRA_EXTMEM_BASE,
     65 		.dr_busbase = TEGRA_EXTMEM_BASE,
     66 		.dr_flags = _BUS_DMAMAP_COHERENT,
     67 	},
     68 };
     69 
     70 struct arm32_bus_dma_tag tegra_coherent_dma_tag = {
     71 	._ranges = tegra_coherent_dma_ranges,
     72 	._nranges = __arraycount(tegra_coherent_dma_ranges),
     73 	_BUS_DMAMAP_FUNCS,
     74 	_BUS_DMAMEM_FUNCS,
     75 	_BUS_DMATAG_FUNCS,
     76 };
     77 
     78 static void	tegra_mpinit(void);
     79 
     80 void
     81 tegra_bootstrap(void)
     82 {
     83 	if (bus_space_map(&armv7_generic_bs_tag,
     84 	    TEGRA_HOST1X_BASE, TEGRA_HOST1X_SIZE, 0,
     85 	    &tegra_host1x_bsh) != 0)
     86 		panic("couldn't map HOST1X");
     87 	if (bus_space_map(&armv7_generic_bs_tag,
     88 	    TEGRA_PPSB_BASE, TEGRA_PPSB_SIZE, 0,
     89 	    &tegra_ppsb_bsh) != 0)
     90 		panic("couldn't map PPSB");
     91 	if (bus_space_map(&armv7_generic_bs_tag,
     92 	    TEGRA_APB_BASE, TEGRA_APB_SIZE, 0,
     93 	    &tegra_apb_bsh) != 0)
     94 		panic("couldn't map APB");
     95 	if (bus_space_map(&armv7_generic_bs_tag,
     96 	    TEGRA_AHB_A2_BASE, TEGRA_AHB_A2_SIZE, 0,
     97 	    &tegra_ahb_a2_bsh) != 0)
     98 		panic("couldn't map AHB A2");
     99 
    100 	curcpu()->ci_data.cpu_cc_freq = tegra_car_pllx_rate();
    101 
    102 	tegra_mpinit();
    103 }
    104 
    105 void
    106 tegra_dma_bootstrap(psize_t psize)
    107 {
    108 	tegra_coherent_dma_ranges[0].dr_len = psize;
    109 }
    110 
    111 void
    112 tegra_cpuinit(void)
    113 {
    114 	switch (tegra_chip_id()) {
    115 #ifdef SOC_TEGRA124
    116 	case CHIP_ID_TEGRA124:
    117 		tegra124_cpuinit();
    118 		break;
    119 #endif
    120 	}
    121 
    122 	tegra_cpufreq_init();
    123 }
    124 
    125 static void
    126 tegra_mpinit(void)
    127 {
    128 #if defined(MULTIPROCESSOR)
    129 	switch (tegra_chip_id()) {
    130 #ifdef SOC_TEGRA124
    131 	case CHIP_ID_TEGRA124:
    132 		tegra124_mpinit();
    133 		break;
    134 #endif
    135 	default:
    136 		panic("Unsupported SOC ID %#x", tegra_chip_id());
    137 	}
    138 #endif
    139 }
    140 
    141 u_int
    142 tegra_chip_id(void)
    143 {
    144 	static u_int chip_id = 0;
    145 
    146 	if (!chip_id) {
    147 		const bus_space_tag_t bst = &armv7_generic_bs_tag;
    148 		const bus_space_handle_t bsh = tegra_apb_bsh;
    149 		const uint32_t v = bus_space_read_4(bst, bsh,
    150 		    APB_MISC_GP_HIDREV_0_REG);
    151 		chip_id = __SHIFTOUT(v, APB_MISC_GP_HIDREV_0_CHIPID);
    152 	}
    153 
    154 	return chip_id;
    155 }
    156 
    157 const char *
    158 tegra_chip_name(void)
    159 {
    160 	switch (tegra_chip_id()) {
    161 	case CHIP_ID_TEGRA124:	return "Tegra K1 (T124)";
    162 	case CHIP_ID_TEGRA132:	return "Tegra K1 (T132)";
    163 	default:		return "Unknown Tegra SoC";
    164 	}
    165 }
    166