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tegra_soc.c revision 1.9.2.1 
      1 /* $NetBSD: tegra_soc.c,v 1.9.2.1 2017/04/26 02:53:01 pgoyette Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #include "opt_tegra.h"
     30 #include "opt_multiprocessor.h"
     31 
     32 #include <sys/cdefs.h>
     33 __KERNEL_RCSID(0, "$NetBSD: tegra_soc.c,v 1.9.2.1 2017/04/26 02:53:01 pgoyette Exp $");
     34 
     35 #define	_ARM32_BUS_DMA_PRIVATE
     36 #include <sys/param.h>
     37 #include <sys/bus.h>
     38 #include <sys/cpu.h>
     39 #include <sys/device.h>
     40 
     41 #include <uvm/uvm_extern.h>
     42 
     43 #include <arm/bootconfig.h>
     44 #include <arm/cpufunc.h>
     45 
     46 #include <arm/nvidia/tegra_reg.h>
     47 #include <arm/nvidia/tegra_apbreg.h>
     48 #include <arm/nvidia/tegra_mcreg.h>
     49 #include <arm/nvidia/tegra_var.h>
     50 
     51 bus_space_handle_t tegra_host1x_bsh;
     52 bus_space_handle_t tegra_ppsb_bsh;
     53 bus_space_handle_t tegra_apb_bsh;
     54 bus_space_handle_t tegra_ahb_a2_bsh;
     55 
     56 struct arm32_bus_dma_tag tegra_dma_tag = {
     57 	_BUS_DMAMAP_FUNCS,
     58 	_BUS_DMAMEM_FUNCS,
     59 	_BUS_DMATAG_FUNCS,
     60 };
     61 
     62 static void	tegra_mpinit(void);
     63 
     64 void
     65 tegra_bootstrap(void)
     66 {
     67 	if (bus_space_map(&armv7_generic_bs_tag,
     68 	    TEGRA_HOST1X_BASE, TEGRA_HOST1X_SIZE, 0,
     69 	    &tegra_host1x_bsh) != 0)
     70 		panic("couldn't map HOST1X");
     71 	if (bus_space_map(&armv7_generic_bs_tag,
     72 	    TEGRA_PPSB_BASE, TEGRA_PPSB_SIZE, 0,
     73 	    &tegra_ppsb_bsh) != 0)
     74 		panic("couldn't map PPSB");
     75 	if (bus_space_map(&armv7_generic_bs_tag,
     76 	    TEGRA_APB_BASE, TEGRA_APB_SIZE, 0,
     77 	    &tegra_apb_bsh) != 0)
     78 		panic("couldn't map APB");
     79 	if (bus_space_map(&armv7_generic_bs_tag,
     80 	    TEGRA_AHB_A2_BASE, TEGRA_AHB_A2_SIZE, 0,
     81 	    &tegra_ahb_a2_bsh) != 0)
     82 		panic("couldn't map AHB A2");
     83 
     84 	tegra_mpinit();
     85 }
     86 
     87 void
     88 tegra_dma_bootstrap(psize_t psize)
     89 {
     90 }
     91 
     92 static void
     93 tegra_mpinit(void)
     94 {
     95 #if defined(MULTIPROCESSOR)
     96 	switch (tegra_chip_id()) {
     97 #ifdef SOC_TEGRA124
     98 	case CHIP_ID_TEGRA124:
     99 		tegra124_mpinit();
    100 		break;
    101 #endif
    102 	default:
    103 		panic("Unsupported SOC ID %#x", tegra_chip_id());
    104 	}
    105 #endif
    106 }
    107 
    108 u_int
    109 tegra_chip_id(void)
    110 {
    111 	static u_int chip_id = 0;
    112 
    113 	if (!chip_id) {
    114 		const bus_space_tag_t bst = &armv7_generic_bs_tag;
    115 		const bus_space_handle_t bsh = tegra_apb_bsh;
    116 		const uint32_t v = bus_space_read_4(bst, bsh,
    117 		    APB_MISC_GP_HIDREV_0_REG);
    118 		chip_id = __SHIFTOUT(v, APB_MISC_GP_HIDREV_0_CHIPID);
    119 	}
    120 
    121 	return chip_id;
    122 }
    123 
    124 const char *
    125 tegra_chip_name(void)
    126 {
    127 	switch (tegra_chip_id()) {
    128 	case CHIP_ID_TEGRA124:	return "Tegra K1 (T124)";
    129 	case CHIP_ID_TEGRA132:	return "Tegra K1 (T132)";
    130 	default:		return "Unknown Tegra SoC";
    131 	}
    132 }
    133