tegra_timer.c revision 1.1.2.2
1 1.1.2.2 skrll /* $NetBSD: tegra_timer.c,v 1.1.2.2 2015/06/06 14:39:56 skrll Exp $ */ 2 1.1.2.2 skrll 3 1.1.2.2 skrll /*- 4 1.1.2.2 skrll * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 1.1.2.2 skrll * All rights reserved. 6 1.1.2.2 skrll * 7 1.1.2.2 skrll * Redistribution and use in source and binary forms, with or without 8 1.1.2.2 skrll * modification, are permitted provided that the following conditions 9 1.1.2.2 skrll * are met: 10 1.1.2.2 skrll * 1. Redistributions of source code must retain the above copyright 11 1.1.2.2 skrll * notice, this list of conditions and the following disclaimer. 12 1.1.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 13 1.1.2.2 skrll * notice, this list of conditions and the following disclaimer in the 14 1.1.2.2 skrll * documentation and/or other materials provided with the distribution. 15 1.1.2.2 skrll * 16 1.1.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 1.1.2.2 skrll * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 1.1.2.2 skrll * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 1.1.2.2 skrll * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 1.1.2.2 skrll * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 1.1.2.2 skrll * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 1.1.2.2 skrll * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 1.1.2.2 skrll * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 1.1.2.2 skrll * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.1.2.2 skrll * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.1.2.2 skrll * SUCH DAMAGE. 27 1.1.2.2 skrll */ 28 1.1.2.2 skrll 29 1.1.2.2 skrll #include <sys/cdefs.h> 30 1.1.2.2 skrll __KERNEL_RCSID(0, "$NetBSD: tegra_timer.c,v 1.1.2.2 2015/06/06 14:39:56 skrll Exp $"); 31 1.1.2.2 skrll 32 1.1.2.2 skrll #include <sys/param.h> 33 1.1.2.2 skrll #include <sys/bus.h> 34 1.1.2.2 skrll #include <sys/device.h> 35 1.1.2.2 skrll #include <sys/intr.h> 36 1.1.2.2 skrll #include <sys/systm.h> 37 1.1.2.2 skrll #include <sys/kernel.h> 38 1.1.2.2 skrll #include <sys/wdog.h> 39 1.1.2.2 skrll 40 1.1.2.2 skrll #include <dev/sysmon/sysmonvar.h> 41 1.1.2.2 skrll 42 1.1.2.2 skrll #include <arm/nvidia/tegra_reg.h> 43 1.1.2.2 skrll #include <arm/nvidia/tegra_timerreg.h> 44 1.1.2.2 skrll #include <arm/nvidia/tegra_var.h> 45 1.1.2.2 skrll 46 1.1.2.2 skrll #define TEGRA_TIMER_WDOG_PERIOD_DEFAULT 10 47 1.1.2.2 skrll 48 1.1.2.2 skrll static int tegra_timer_match(device_t, cfdata_t, void *); 49 1.1.2.2 skrll static void tegra_timer_attach(device_t, device_t, void *); 50 1.1.2.2 skrll 51 1.1.2.2 skrll struct tegra_timer_softc { 52 1.1.2.2 skrll device_t sc_dev; 53 1.1.2.2 skrll bus_space_tag_t sc_bst; 54 1.1.2.2 skrll bus_space_handle_t sc_bsh; 55 1.1.2.2 skrll 56 1.1.2.2 skrll struct sysmon_wdog sc_smw; 57 1.1.2.2 skrll }; 58 1.1.2.2 skrll 59 1.1.2.2 skrll static int tegra_timer_wdt_setmode(struct sysmon_wdog *); 60 1.1.2.2 skrll static int tegra_timer_wdt_tickle(struct sysmon_wdog *); 61 1.1.2.2 skrll 62 1.1.2.2 skrll CFATTACH_DECL_NEW(tegra_timer, sizeof(struct tegra_timer_softc), 63 1.1.2.2 skrll tegra_timer_match, tegra_timer_attach, NULL, NULL); 64 1.1.2.2 skrll 65 1.1.2.2 skrll #define TIMER_READ(sc, reg) \ 66 1.1.2.2 skrll bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 67 1.1.2.2 skrll #define TIMER_WRITE(sc, reg, val) \ 68 1.1.2.2 skrll bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 69 1.1.2.2 skrll #define TIMER_SET_CLEAR(sc, reg, set, clr) \ 70 1.1.2.2 skrll tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (set), (clr)) 71 1.1.2.2 skrll 72 1.1.2.2 skrll static int 73 1.1.2.2 skrll tegra_timer_match(device_t parent, cfdata_t cf, void *aux) 74 1.1.2.2 skrll { 75 1.1.2.2 skrll return 1; 76 1.1.2.2 skrll } 77 1.1.2.2 skrll 78 1.1.2.2 skrll static void 79 1.1.2.2 skrll tegra_timer_attach(device_t parent, device_t self, void *aux) 80 1.1.2.2 skrll { 81 1.1.2.2 skrll struct tegra_timer_softc * const sc = device_private(self); 82 1.1.2.2 skrll struct tegraio_attach_args * const tio = aux; 83 1.1.2.2 skrll const struct tegra_locators * const loc = &tio->tio_loc; 84 1.1.2.2 skrll 85 1.1.2.2 skrll sc->sc_dev = self; 86 1.1.2.2 skrll sc->sc_bst = tio->tio_bst; 87 1.1.2.2 skrll bus_space_subregion(tio->tio_bst, tio->tio_bsh, 88 1.1.2.2 skrll loc->loc_offset, loc->loc_size, &sc->sc_bsh); 89 1.1.2.2 skrll 90 1.1.2.2 skrll aprint_naive("\n"); 91 1.1.2.2 skrll aprint_normal(": Timers\n"); 92 1.1.2.2 skrll 93 1.1.2.2 skrll sc->sc_smw.smw_name = device_xname(self); 94 1.1.2.2 skrll sc->sc_smw.smw_cookie = sc; 95 1.1.2.2 skrll sc->sc_smw.smw_setmode = tegra_timer_wdt_setmode; 96 1.1.2.2 skrll sc->sc_smw.smw_tickle = tegra_timer_wdt_tickle; 97 1.1.2.2 skrll sc->sc_smw.smw_period = TEGRA_TIMER_WDOG_PERIOD_DEFAULT; 98 1.1.2.2 skrll 99 1.1.2.2 skrll aprint_normal_dev(self, "default watchdog period is %u seconds\n", 100 1.1.2.2 skrll sc->sc_smw.smw_period); 101 1.1.2.2 skrll 102 1.1.2.2 skrll if (sysmon_wdog_register(&sc->sc_smw) != 0) 103 1.1.2.2 skrll aprint_error_dev(self, "couldn't register with sysmon\n"); 104 1.1.2.2 skrll } 105 1.1.2.2 skrll 106 1.1.2.2 skrll static int 107 1.1.2.2 skrll tegra_timer_wdt_setmode(struct sysmon_wdog *smw) 108 1.1.2.2 skrll { 109 1.1.2.2 skrll struct tegra_timer_softc * const sc = smw->smw_cookie; 110 1.1.2.2 skrll 111 1.1.2.2 skrll if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 112 1.1.2.2 skrll TIMER_SET_CLEAR(sc, TMR1_PTV_REG, 0, TMR_PTV_EN); 113 1.1.2.2 skrll tegra_car_wdt_enable(1, false); 114 1.1.2.2 skrll } else { 115 1.1.2.2 skrll if (smw->smw_period == WDOG_PERIOD_DEFAULT) { 116 1.1.2.2 skrll sc->sc_smw.smw_period = TEGRA_TIMER_WDOG_PERIOD_DEFAULT; 117 1.1.2.2 skrll } else if (smw->smw_period == 0 || smw->smw_period > 1000) { 118 1.1.2.2 skrll return EINVAL; 119 1.1.2.2 skrll } else { 120 1.1.2.2 skrll sc->sc_smw.smw_period = smw->smw_period; 121 1.1.2.2 skrll } 122 1.1.2.2 skrll u_int tval = (sc->sc_smw.smw_period * 1000000) / 2; 123 1.1.2.2 skrll TIMER_WRITE(sc, TMR1_PTV_REG, 124 1.1.2.2 skrll TMR_PTV_EN | TMR_PTV_PER | __SHIFTIN(tval, TMR_PTV_VAL)); 125 1.1.2.2 skrll TIMER_WRITE(sc, TMR1_PCR_REG, TMR_PCR_INTR_CLR); 126 1.1.2.2 skrll tegra_car_wdt_enable(1, true); 127 1.1.2.2 skrll } 128 1.1.2.2 skrll 129 1.1.2.2 skrll return 0; 130 1.1.2.2 skrll } 131 1.1.2.2 skrll 132 1.1.2.2 skrll static int 133 1.1.2.2 skrll tegra_timer_wdt_tickle(struct sysmon_wdog *smw) 134 1.1.2.2 skrll { 135 1.1.2.2 skrll struct tegra_timer_softc * const sc = smw->smw_cookie; 136 1.1.2.2 skrll 137 1.1.2.2 skrll TIMER_WRITE(sc, TMR1_PCR_REG, TMR_PCR_INTR_CLR); 138 1.1.2.2 skrll 139 1.1.2.2 skrll return 0; 140 1.1.2.2 skrll } 141
Indexes created Tue Sep 30 20:09:53 GMT 2025